1/* 2 * 53c710 driver. Modified from Drew Eckhardts driver 3 * for 53c810 by Richard Hirst [richard@sleepie.demon.co.uk] 4 * 5 * I have left the code for the 53c8xx family in here, because it didn't 6 * seem worth removing it. The possibility of IO_MAPPED chips rather 7 * than MEMORY_MAPPED remains, in case someone wants to add support for 8 * 53c710 chips on Intel PCs (some older machines have them on the 9 * motherboard). 10 * 11 * NOTE THERE MAY BE PROBLEMS WITH CASTS IN read8 AND Co. 12 */ 13 14/* 15 * NCR 53c{7,8}0x0 driver, header file 16 * 17 * Sponsored by 18 * iX Multiuser Multitasking Magazine 19 * Hannover, Germany 20 * hm@ix.de 21 * 22 * Copyright 1993, 1994, 1995 Drew Eckhardt 23 * Visionary Computing 24 * (Unix and Linux consulting and custom programming) 25 * drew@PoohSticks.ORG 26 * +1 (303) 786-7975 27 * 28 * TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation. 29 * 30 * PRE-ALPHA 31 * 32 * For more information, please consult 33 * 34 * NCR 53C700/53C700-66 35 * SCSI I/O Processor 36 * Data Manual 37 * 38 * NCR 53C810 39 * PCI-SCSI I/O Processor 40 * Data Manual 41 * 42 * NCR Microelectronics 43 * 1635 Aeroplaza Drive 44 * Colorado Springs, CO 80916 45 * +1 (719) 578-3400 46 * 47 * Toll free literature number 48 * +1 (800) 334-5454 49 * 50 */ 51 52#ifndef NCR53c710_H 53#define NCR53c710_H 54 55#ifndef HOSTS_C 56 57/* SCSI control 0 rw, default = 0xc0 */ 58#define SCNTL0_REG 0x00 59#define SCNTL0_ARB1 0x80 /* 0 0 = simple arbitration */ 60#define SCNTL0_ARB2 0x40 /* 1 1 = full arbitration */ 61#define SCNTL0_STRT 0x20 /* Start Sequence */ 62#define SCNTL0_WATN 0x10 /* Select with ATN */ 63#define SCNTL0_EPC 0x08 /* Enable parity checking */ 64/* Bit 2 is reserved on 800 series chips */ 65#define SCNTL0_EPG_700 0x04 /* Enable parity generation */ 66#define SCNTL0_AAP 0x02 /* ATN/ on parity error */ 67#define SCNTL0_TRG 0x01 /* Target mode */ 68 69/* SCSI control 1 rw, default = 0x00 */ 70 71#define SCNTL1_REG 0x01 72#define SCNTL1_EXC 0x80 /* Extra Clock Cycle of Data setup */ 73#define SCNTL1_ADB 0x40 /* contents of SODL on bus */ 74#define SCNTL1_ESR_700 0x20 /* Enable SIOP response to selection 75 and reselection */ 76#define SCNTL1_DHP_800 0x20 /* Disable halt on parity error or ATN 77 target mode only */ 78#define SCNTL1_CON 0x10 /* Connected */ 79#define SCNTL1_RST 0x08 /* SCSI RST/ */ 80#define SCNTL1_AESP 0x04 /* Force bad parity */ 81#define SCNTL1_SND_700 0x02 /* Start SCSI send */ 82#define SCNTL1_IARB_800 0x02 /* Immediate Arbitration, start 83 arbitration immediately after 84 busfree is detected */ 85#define SCNTL1_RCV_700 0x01 /* Start SCSI receive */ 86#define SCNTL1_SST_800 0x01 /* Start SCSI transfer */ 87 88/* SCSI control 2 rw, */ 89 90#define SCNTL2_REG_800 0x02 91#define SCNTL2_800_SDU 0x80 /* SCSI disconnect unexpected */ 92 93/* SCSI control 3 rw */ 94 95#define SCNTL3_REG_800 0x03 96#define SCNTL3_800_SCF_SHIFT 4 97#define SCNTL3_800_SCF_MASK 0x70 98#define SCNTL3_800_SCF2 0x40 /* Synchronous divisor */ 99#define SCNTL3_800_SCF1 0x20 /* 0x00 = SCLK/3 */ 100#define SCNTL3_800_SCF0 0x10 /* 0x10 = SCLK/1 */ 101 /* 0x20 = SCLK/1.5 102 0x30 = SCLK/2 103 0x40 = SCLK/3 */ 104 105#define SCNTL3_800_CCF_SHIFT 0 106#define SCNTL3_800_CCF_MASK 0x07 107#define SCNTL3_800_CCF2 0x04 /* 0x00 50.01 to 66 */ 108#define SCNTL3_800_CCF1 0x02 /* 0x01 16.67 to 25 */ 109#define SCNTL3_800_CCF0 0x01 /* 0x02 25.01 - 37.5 110 0x03 37.51 - 50 111 0x04 50.01 - 66 */ 112 113/* 114 * SCSI destination ID rw - the appropriate bit is set for the selected 115 * target ID. This is written by the SCSI SCRIPTS processor. 116 * default = 0x00 117 */ 118#define SDID_REG_700 0x02 119#define SDID_REG_800 0x06 120 121#define GP_REG_800 0x07 /* General purpose IO */ 122#define GP_800_IO1 0x02 123#define GP_800_IO2 0x01 124 125/* SCSI interrupt enable rw, default = 0x00 */ 126#define SIEN_REG_700 0x03 127#define SIEN0_REG_800 0x40 128#define SIEN_MA 0x80 /* Phase mismatch (ini) or ATN (tgt) */ 129#define SIEN_FC 0x40 /* Function complete */ 130#define SIEN_700_STO 0x20 /* Selection or reselection timeout */ 131#define SIEN_800_SEL 0x20 /* Selected */ 132#define SIEN_700_SEL 0x10 /* Selected or reselected */ 133#define SIEN_800_RESEL 0x10 /* Reselected */ 134#define SIEN_SGE 0x08 /* SCSI gross error */ 135#define SIEN_UDC 0x04 /* Unexpected disconnect */ 136#define SIEN_RST 0x02 /* SCSI RST/ received */ 137#define SIEN_PAR 0x01 /* Parity error */ 138 139/* 140 * SCSI chip ID rw 141 * NCR53c700 : 142 * When arbitrating, the highest bit is used, when reselection or selection 143 * occurs, the chip responds to all IDs for which a bit is set. 144 * default = 0x00 145 * NCR53c810 : 146 * Uses bit mapping 147 */ 148#define SCID_REG 0x04 149/* Bit 7 is reserved on 800 series chips */ 150#define SCID_800_RRE 0x40 /* Enable response to reselection */ 151#define SCID_800_SRE 0x20 /* Enable response to selection */ 152/* Bits four and three are reserved on 800 series chips */ 153#define SCID_800_ENC_MASK 0x07 /* Encoded SCSI ID */ 154 155/* SCSI transfer rw, default = 0x00 */ 156#define SXFER_REG 0x05 157#define SXFER_DHP 0x80 /* Disable halt on parity */ 158 159#define SXFER_TP2 0x40 /* Transfer period msb */ 160#define SXFER_TP1 0x20 161#define SXFER_TP0 0x10 /* lsb */ 162#define SXFER_TP_MASK 0x70 163#define SXFER_TP_SHIFT 5 164#define SXFER_TP_4 0x00 /* Divisors */ 165#define SXFER_TP_5 0x10<<1 166#define SXFER_TP_6 0x20<<1 167#define SXFER_TP_7 0x30<<1 168#define SXFER_TP_8 0x40<<1 169#define SXFER_TP_9 0x50<<1 170#define SXFER_TP_10 0x60<<1 171#define SXFER_TP_11 0x70<<1 172 173#define SXFER_MO3 0x08 /* Max offset msb */ 174#define SXFER_MO2 0x04 175#define SXFER_MO1 0x02 176#define SXFER_MO0 0x01 /* lsb */ 177#define SXFER_MO_MASK 0x0f 178#define SXFER_MO_SHIFT 0 179 180/* 181 * SCSI output data latch rw 182 * The contents of this register are driven onto the SCSI bus when 183 * the Assert Data Bus bit of the SCNTL1 register is set and 184 * the CD, IO, and MSG bits of the SOCL register match the SCSI phase 185 */ 186#define SODL_REG_700 0x06 187#define SODL_REG_800 0x54 188 189 190/* 191 * SCSI output control latch rw, default = 0 192 * Note that when the chip is being manually programmed as an initiator, 193 * the MSG, CD, and IO bits must be set correctly for the phase the target 194 * is driving the bus in. Otherwise no data transfer will occur due to 195 * phase mismatch. 196 */ 197 198#define SOCL_REG 0x07 199#define SOCL_REQ 0x80 /* REQ */ 200#define SOCL_ACK 0x40 /* ACK */ 201#define SOCL_BSY 0x20 /* BSY */ 202#define SOCL_SEL 0x10 /* SEL */ 203#define SOCL_ATN 0x08 /* ATN */ 204#define SOCL_MSG 0x04 /* MSG */ 205#define SOCL_CD 0x02 /* C/D */ 206#define SOCL_IO 0x01 /* I/O */ 207 208/* 209 * SCSI first byte received latch ro 210 * This register contains the first byte received during a block MOVE 211 * SCSI SCRIPTS instruction, including 212 * 213 * Initiator mode Target mode 214 * Message in Command 215 * Status Message out 216 * Data in Data out 217 * 218 * It also contains the selecting or reselecting device's ID and our 219 * ID. 220 * 221 * Note that this is the register the various IF conditionals can 222 * operate on. 223 */ 224#define SFBR_REG 0x08 225 226/* 227 * SCSI input data latch ro 228 * In initiator mode, data is latched into this register on the rising 229 * edge of REQ/. In target mode, data is latched on the rising edge of 230 * ACK/ 231 */ 232#define SIDL_REG_700 0x09 233#define SIDL_REG_800 0x50 234 235/* 236 * SCSI bus data lines ro 237 * This register reflects the instantaneous status of the SCSI data 238 * lines. Note that SCNTL0 must be set to disable parity checking, 239 * otherwise reading this register will latch new parity. 240 */ 241#define SBDL_REG_700 0x0a 242#define SBDL_REG_800 0x58 243 244#define SSID_REG_800 0x0a 245#define SSID_800_VAL 0x80 /* Exactly two bits asserted at sel */ 246#define SSID_800_ENCID_MASK 0x07 /* Device which performed operation */ 247 248 249/* 250 * SCSI bus control lines rw, 251 * instantaneous readout of control lines 252 */ 253#define SBCL_REG 0x0b 254#define SBCL_REQ 0x80 /* REQ ro */ 255#define SBCL_ACK 0x40 /* ACK ro */ 256#define SBCL_BSY 0x20 /* BSY ro */ 257#define SBCL_SEL 0x10 /* SEL ro */ 258#define SBCL_ATN 0x08 /* ATN ro */ 259#define SBCL_MSG 0x04 /* MSG ro */ 260#define SBCL_CD 0x02 /* C/D ro */ 261#define SBCL_IO 0x01 /* I/O ro */ 262#define SBCL_PHASE_CMDOUT SBCL_CD 263#define SBCL_PHASE_DATAIN SBCL_IO 264#define SBCL_PHASE_DATAOUT 0 265#define SBCL_PHASE_MSGIN (SBCL_CD|SBCL_IO|SBCL_MSG) 266#define SBCL_PHASE_MSGOUT (SBCL_CD|SBCL_MSG) 267#define SBCL_PHASE_STATIN (SBCL_CD|SBCL_IO) 268#define SBCL_PHASE_MASK (SBCL_CD|SBCL_IO|SBCL_MSG) 269/* 270 * Synchronous SCSI Clock Control bits 271 * 0 - set by DCNTL 272 * 1 - SCLK / 1.0 273 * 2 - SCLK / 1.5 274 * 3 - SCLK / 2.0 275 */ 276#define SBCL_SSCF1 0x02 /* wo, -66 only */ 277#define SBCL_SSCF0 0x01 /* wo, -66 only */ 278#define SBCL_SSCF_MASK 0x03 279 280/* DMA status ro */ 281#define DSTAT_REG 0x0c 282#define DSTAT_DFE 0x80 /* DMA FIFO empty */ 283#define DSTAT_800_MDPE 0x40 /* Master Data Parity Error */ 284#define DSTAT_800_BF 0x20 /* Bus Fault */ 285#define DSTAT_ABRT 0x10 /* Aborted - set on error */ 286#define DSTAT_SSI 0x08 /* SCRIPTS single step interrupt */ 287#define DSTAT_SIR 0x04 /* SCRIPTS interrupt received - 288 set when INT instruction is 289 executed */ 290#define DSTAT_WTD 0x02 /* Watchdog timeout detected */ 291#define DSTAT_OPC 0x01 /* Illegal instruction */ 292#define DSTAT_800_IID 0x01 /* Same thing, different name */ 293 294 295/* NCR53c800 moves this stuff into SIST0 */ 296#define SSTAT0_REG 0x0d /* SCSI status 0 ro */ 297#define SIST0_REG_800 0x42 298#define SSTAT0_MA 0x80 /* ini : phase mismatch, 299 * tgt : ATN/ asserted 300 */ 301#define SSTAT0_CMP 0x40 /* function complete */ 302#define SSTAT0_700_STO 0x20 /* Selection or reselection timeout */ 303#define SIST0_800_SEL 0x20 /* Selected */ 304#define SSTAT0_700_SEL 0x10 /* Selected or reselected */ 305#define SIST0_800_RSL 0x10 /* Reselected */ 306#define SSTAT0_SGE 0x08 /* SCSI gross error */ 307#define SSTAT0_UDC 0x04 /* Unexpected disconnect */ 308#define SSTAT0_RST 0x02 /* SCSI RST/ received */ 309#define SSTAT0_PAR 0x01 /* Parity error */ 310 311/* And uses SSTAT0 for what was SSTAT1 */ 312 313#define SSTAT1_REG 0x0e /* SCSI status 1 ro */ 314#define SSTAT1_ILF 0x80 /* SIDL full */ 315#define SSTAT1_ORF 0x40 /* SODR full */ 316#define SSTAT1_OLF 0x20 /* SODL full */ 317#define SSTAT1_AIP 0x10 /* Arbitration in progress */ 318#define SSTAT1_LOA 0x08 /* Lost arbitration */ 319#define SSTAT1_WOA 0x04 /* Won arbitration */ 320#define SSTAT1_RST 0x02 /* Instant readout of RST/ */ 321#define SSTAT1_SDP 0x01 /* Instant readout of SDP/ */ 322 323#define SSTAT2_REG 0x0f /* SCSI status 2 ro */ 324#define SSTAT2_FF3 0x80 /* number of bytes in synchronous */ 325#define SSTAT2_FF2 0x40 /* data FIFO */ 326#define SSTAT2_FF1 0x20 327#define SSTAT2_FF0 0x10 328#define SSTAT2_FF_MASK 0xf0 329#define SSTAT2_FF_SHIFT 4 330 331/* 332 * Latched signals, latched on the leading edge of REQ/ for initiators, 333 * ACK/ for targets. 334 */ 335#define SSTAT2_SDP 0x08 /* SDP */ 336#define SSTAT2_MSG 0x04 /* MSG */ 337#define SSTAT2_CD 0x02 /* C/D */ 338#define SSTAT2_IO 0x01 /* I/O */ 339#define SSTAT2_PHASE_CMDOUT SSTAT2_CD 340#define SSTAT2_PHASE_DATAIN SSTAT2_IO 341#define SSTAT2_PHASE_DATAOUT 0 342#define SSTAT2_PHASE_MSGIN (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG) 343#define SSTAT2_PHASE_MSGOUT (SSTAT2_CD|SSTAT2_MSG) 344#define SSTAT2_PHASE_STATIN (SSTAT2_CD|SSTAT2_IO) 345#define SSTAT2_PHASE_MASK (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG) 346 347 348/* NCR53c700-66 only */ 349#define SCRATCHA_REG_00 0x10 /* through 0x13 Scratch A rw */ 350/* NCR53c710 and higher */ 351#define DSA_REG 0x10 /* DATA structure address */ 352 353#define CTEST0_REG_700 0x14 /* Chip test 0 ro */ 354#define CTEST0_REG_800 0x18 /* Chip test 0 rw, general purpose */ 355/* 0x80 - 0x04 are reserved */ 356#define CTEST0_700_RTRG 0x02 /* Real target mode */ 357#define CTEST0_700_DDIR 0x01 /* Data direction, 1 = 358 * SCSI bus to host, 0 = 359 * host to SCSI. 360 */ 361 362#define CTEST1_REG_700 0x15 /* Chip test 1 ro */ 363#define CTEST1_REG_800 0x19 /* Chip test 1 ro */ 364#define CTEST1_FMT3 0x80 /* Identify which byte lanes are empty */ 365#define CTEST1_FMT2 0x40 /* in the DMA FIFO */ 366#define CTEST1_FMT1 0x20 367#define CTEST1_FMT0 0x10 368 369#define CTEST1_FFL3 0x08 /* Identify which bytes lanes are full */ 370#define CTEST1_FFL2 0x04 /* in the DMA FIFO */ 371#define CTEST1_FFL1 0x02 372#define CTEST1_FFL0 0x01 373 374#define CTEST2_REG_700 0x16 /* Chip test 2 ro */ 375#define CTEST2_REG_800 0x1a /* Chip test 2 ro */ 376 377#define CTEST2_800_DDIR 0x80 /* 1 = SCSI->host */ 378#define CTEST2_800_SIGP 0x40 /* A copy of SIGP in ISTAT. 379 Reading this register clears */ 380#define CTEST2_800_CIO 0x20 /* Configured as IO */. 381#define CTEST2_800_CM 0x10 /* Configured as memory */ 382 383/* 0x80 - 0x40 are reserved on 700 series chips */ 384#define CTEST2_700_SOFF 0x20 /* SCSI Offset Compare, 385 * As an initiator, this bit is 386 * one when the synchronous offset 387 * is zero, as a target this bit 388 * is one when the synchronous 389 * offset is at the maximum 390 * defined in SXFER 391 */ 392#define CTEST2_700_SFP 0x10 /* SCSI FIFO parity bit, 393 * reading CTEST3 unloads a byte 394 * from the FIFO and sets this 395 */ 396#define CTEST2_700_DFP 0x08 /* DMA FIFO parity bit, 397 * reading CTEST6 unloads a byte 398 * from the FIFO and sets this 399 */ 400#define CTEST2_TEOP 0x04 /* SCSI true end of process, 401 * indicates a totally finished 402 * transfer 403 */ 404#define CTEST2_DREQ 0x02 /* Data request signal */ 405/* 0x01 is reserved on 700 series chips */ 406#define CTEST2_800_DACK 0x01 407 408/* 409 * Chip test 3 ro 410 * Unloads the bottom byte of the eight deep SCSI synchronous FIFO, 411 * check SSTAT2 FIFO full bits to determine size. Note that a GROSS 412 * error results if a read is attempted on this register. Also note 413 * that 16 and 32 bit reads of this register will cause corruption. 414 */ 415#define CTEST3_REG_700 0x17 416/* Chip test 3 rw */ 417#define CTEST3_REG_800 0x1b 418#define CTEST3_800_V3 0x80 /* Chip revision */ 419#define CTEST3_800_V2 0x40 420#define CTEST3_800_V1 0x20 421#define CTEST3_800_V0 0x10 422#define CTEST3_800_FLF 0x08 /* Flush DMA FIFO */ 423#define CTEST3_800_CLF 0x04 /* Clear DMA FIFO */ 424#define CTEST3_800_FM 0x02 /* Fetch mode pin */ 425/* bit 0 is reserved on 800 series chips */ 426 427#define CTEST4_REG_700 0x18 /* Chip test 4 rw */ 428#define CTEST4_REG_800 0x21 /* Chip test 4 rw */ 429/* 0x80 is reserved on 700 series chips */ 430#define CTEST4_800_BDIS 0x80 /* Burst mode disable */ 431#define CTEST4_ZMOD 0x40 /* High impedance mode */ 432#define CTEST4_SZM 0x20 /* SCSI bus high impedance */ 433#define CTEST4_700_SLBE 0x10 /* SCSI loopback enabled */ 434#define CTEST4_800_SRTM 0x10 /* Shadow Register Test Mode */ 435#define CTEST4_700_SFWR 0x08 /* SCSI FIFO write enable, 436 * redirects writes from SODL 437 * to the SCSI FIFO. 438 */ 439#define CTEST4_800_MPEE 0x08 /* Enable parity checking 440 during master cycles on PCI 441 bus */ 442 443/* 444 * These bits send the contents of the CTEST6 register to the appropriate 445 * byte lane of the 32 bit DMA FIFO. Normal operation is zero, otherwise 446 * the high bit means the low two bits select the byte lane. 447 */ 448#define CTEST4_FBL2 0x04 449#define CTEST4_FBL1 0x02 450#define CTEST4_FBL0 0x01 451#define CTEST4_FBL_MASK 0x07 452#define CTEST4_FBL_0 0x04 /* Select DMA FIFO byte lane 0 */ 453#define CTEST4_FBL_1 0x05 /* Select DMA FIFO byte lane 1 */ 454#define CTEST4_FBL_2 0x06 /* Select DMA FIFO byte lane 2 */ 455#define CTEST4_FBL_3 0x07 /* Select DMA FIFO byte lane 3 */ 456#define CTEST4_800_SAVE (CTEST4_800_BDIS) 457 458 459#define CTEST5_REG_700 0x19 /* Chip test 5 rw */ 460#define CTEST5_REG_800 0x22 /* Chip test 5 rw */ 461/* 462 * Clock Address Incrementor. When set, it increments the 463 * DNAD register to the next bus size boundary. It automatically 464 * resets itself when the operation is complete. 465 */ 466#define CTEST5_ADCK 0x80 467/* 468 * Clock Byte Counter. When set, it decrements the DBC register to 469 * the next bus size boundary. 470 */ 471#define CTEST5_BBCK 0x40 472/* 473 * Reset SCSI Offset. Setting this bit to 1 clears the current offset 474 * pointer in the SCSI synchronous offset counter (SSTAT). This bit 475 * is set to 1 if a SCSI Gross Error Condition occurs. The offset should 476 * be cleared when a synchronous transfer fails. When written, it is 477 * automatically cleared after the SCSI synchronous offset counter is 478 * reset. 479 */ 480/* Bit 5 is reserved on 800 series chips */ 481#define CTEST5_700_ROFF 0x20 482/* 483 * Master Control for Set or Reset pulses. When 1, causes the low 484 * four bits of register to set when set, 0 causes the low bits to 485 * clear when set. 486 */ 487#define CTEST5_MASR 0x10 488#define CTEST5_DDIR 0x08 /* DMA direction */ 489/* 490 * Bits 2-0 are reserved on 800 series chips 491 */ 492#define CTEST5_700_EOP 0x04 /* End of process */ 493#define CTEST5_700_DREQ 0x02 /* Data request */ 494#define CTEST5_700_DACK 0x01 /* Data acknowledge */ 495 496/* 497 * Chip test 6 rw - writing to this register writes to the byte 498 * lane in the DMA FIFO as determined by the FBL bits in the CTEST4 499 * register. 500 */ 501#define CTEST6_REG_700 0x1a 502#define CTEST6_REG_800 0x23 503 504#define CTEST7_REG 0x1b /* Chip test 7 rw */ 505/* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */ 506#define CTEST7_10_CDIS 0x80 /* Cache burst disable */ 507#define CTEST7_10_SC1 0x40 /* Snoop control bits */ 508#define CTEST7_10_SC0 0x20 509#define CTEST7_10_SC_MASK 0x60 510/* 0x20 is reserved on the NCR53c700 */ 511#define CTEST7_0060_FM 0x20 /* Fetch mode */ 512#define CTEST7_STD 0x10 /* Selection timeout disable */ 513#define CTEST7_DFP 0x08 /* DMA FIFO parity bit for CTEST6 */ 514#define CTEST7_EVP 0x04 /* 1 = host bus even parity, 0 = odd */ 515#define CTEST7_10_TT1 0x02 /* Transfer type */ 516#define CTEST7_00_DC 0x02 /* Set to drive DC low during instruction 517 fetch */ 518#define CTEST7_DIFF 0x01 /* Differential mode */ 519 520#define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF ) 521 522 523#define TEMP_REG 0x1c /* through 0x1f Temporary stack rw */ 524 525#define DFIFO_REG 0x20 /* DMA FIFO rw */ 526/* 527 * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been 528 * moved into the CTEST8 register. 529 */ 530#define DFIFO_00_FLF 0x80 /* Flush DMA FIFO to memory */ 531#define DFIFO_00_CLF 0x40 /* Clear DMA and SCSI FIFOs */ 532#define DFIFO_BO6 0x40 533#define DFIFO_BO5 0x20 534#define DFIFO_BO4 0x10 535#define DFIFO_BO3 0x08 536#define DFIFO_BO2 0x04 537#define DFIFO_BO1 0x02 538#define DFIFO_BO0 0x01 539#define DFIFO_10_BO_MASK 0x7f /* 7 bit counter */ 540#define DFIFO_00_BO_MASK 0x3f /* 6 bit counter */ 541 542/* 543 * Interrupt status rw 544 * Note that this is the only register which can be read while SCSI 545 * SCRIPTS are being executed. 546 */ 547#define ISTAT_REG_700 0x21 548#define ISTAT_REG_800 0x14 549#define ISTAT_ABRT 0x80 /* Software abort, write 550 *1 to abort, wait for interrupt. */ 551/* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */ 552#define ISTAT_10_SRST 0x40 /* software reset */ 553#define ISTAT_10_SIGP 0x20 /* signal script */ 554/* 0x10 is reserved on NCR53c700 series chips */ 555#define ISTAT_800_SEM 0x10 /* semaphore */ 556#define ISTAT_CON 0x08 /* 1 when connected */ 557#define ISTAT_800_INTF 0x04 /* Interrupt on the fly */ 558#define ISTAT_700_PRE 0x04 /* Pointer register empty. 559 * Set to 1 when DSPS and DSP 560 * registers are empty in pipeline 561 * mode, always set otherwise. 562 */ 563#define ISTAT_SIP 0x02 /* SCSI interrupt pending from 564 * SCSI portion of SIOP see 565 * SSTAT0 566 */ 567#define ISTAT_DIP 0x01 /* DMA interrupt pending 568 * see DSTAT 569 */ 570 571/* NCR53c700-66 and NCR53c710 only */ 572#define CTEST8_REG 0x22 /* Chip test 8 rw */ 573#define CTEST8_0066_EAS 0x80 /* Enable alternate SCSI clock, 574 * ie read from SCLK/ rather than CLK/ 575 */ 576#define CTEST8_0066_EFM 0x40 /* Enable fetch and master outputs */ 577#define CTEST8_0066_GRP 0x20 /* Generate Receive Parity for 578 * pass through. This insures that 579 * bad parity won't reach the host 580 * bus. 581 */ 582#define CTEST8_0066_TE 0x10 /* TolerANT enable. Enable 583 * active negation, should only 584 * be used for slow SCSI 585 * non-differential. 586 */ 587#define CTEST8_0066_HSC 0x08 /* Halt SCSI clock */ 588#define CTEST8_0066_SRA 0x04 /* Shorten REQ/ACK filtering, 589 * must be set for fast SCSI-II 590 * speeds. 591 */ 592#define CTEST8_0066_DAS 0x02 /* Disable automatic target/initiator 593 * switching. 594 */ 595#define CTEST8_0066_LDE 0x01 /* Last disconnect enable. 596 * The status of pending 597 * disconnect is maintained by 598 * the core, eliminating 599 * the possibility of missing a 600 * selection or reselection 601 * while waiting to fetch a 602 * WAIT DISCONNECT opcode. 603 */ 604 605#define CTEST8_10_V3 0x80 /* Chip revision */ 606#define CTEST8_10_V2 0x40 607#define CTEST8_10_V1 0x20 608#define CTEST8_10_V0 0x10 609#define CTEST8_10_V_MASK 0xf0 610#define CTEST8_10_FLF 0x08 /* Flush FIFOs */ 611#define CTEST8_10_CLF 0x04 /* Clear FIFOs */ 612#define CTEST8_10_FM 0x02 /* Fetch pin mode */ 613#define CTEST8_10_SM 0x01 /* Snoop pin mode */ 614 615 616/* 617 * The CTEST9 register may be used to differentiate between a 618 * NCR53c700 and a NCR53c710. 619 * 620 * Write 0xff to this register. 621 * Read it. 622 * If the contents are 0xff, it is a NCR53c700 623 * If the contents are 0x00, it is a NCR53c700-66 first revision 624 * If the contents are some other value, it is some other NCR53c700-66 625 */ 626#define CTEST9_REG_00 0x23 /* Chip test 9 ro */ 627#define LCRC_REG_10 0x23 628 629/* 630 * 0x24 through 0x27 are the DMA byte counter register. Instructions 631 * write their high 8 bits into the DCMD register, the low 24 bits into 632 * the DBC register. 633 * 634 * Function is dependent on the command type being executed. 635 */ 636 637 638#define DBC_REG 0x24 639/* 640 * For Block Move Instructions, DBC is a 24 bit quantity representing 641 * the number of bytes to transfer. 642 * For Transfer Control Instructions, DBC is bit fielded as follows : 643 */ 644/* Bits 20 - 23 should be clear */ 645#define DBC_TCI_TRUE (1 << 19) /* Jump when true */ 646#define DBC_TCI_COMPARE_DATA (1 << 18) /* Compare data */ 647#define DBC_TCI_COMPARE_PHASE (1 << 17) /* Compare phase with DCMD field */ 648#define DBC_TCI_WAIT_FOR_VALID (1 << 16) /* Wait for REQ */ 649/* Bits 8 - 15 are reserved on some implementations ? */ 650#define DBC_TCI_MASK_MASK 0xff00 /* Mask for data compare */ 651#define DBC_TCI_MASK_SHIFT 8 652#define DBC_TCI_DATA_MASK 0xff /* Data to be compared */ 653#define DBC_TCI_DATA_SHIFT 0 654 655#define DBC_RWRI_IMMEDIATE_MASK 0xff00 /* Immediate data */ 656#define DBC_RWRI_IMMEDIATE_SHIFT 8 /* Amount to shift */ 657#define DBC_RWRI_ADDRESS_MASK 0x3f0000 /* Register address */ 658#define DBC_RWRI_ADDRESS_SHIFT 16 659 660 661/* 662 * DMA command r/w 663 */ 664#define DCMD_REG 0x27 665#define DCMD_TYPE_MASK 0xc0 /* Masks off type */ 666#define DCMD_TYPE_BMI 0x00 /* Indicates a Block Move instruction */ 667#define DCMD_BMI_IO 0x01 /* I/O, CD, and MSG bits selecting */ 668#define DCMD_BMI_CD 0x02 /* the phase for the block MOVE */ 669#define DCMD_BMI_MSG 0x04 /* instruction */ 670 671#define DCMD_BMI_OP_MASK 0x18 /* mask for opcode */ 672#define DCMD_BMI_OP_MOVE_T 0x00 /* MOVE */ 673#define DCMD_BMI_OP_MOVE_I 0x08 /* MOVE Initiator */ 674 675#define DCMD_BMI_INDIRECT 0x20 /* Indirect addressing */ 676 677#define DCMD_TYPE_TCI 0x80 /* Indicates a Transfer Control 678 instruction */ 679#define DCMD_TCI_IO 0x01 /* I/O, CD, and MSG bits selecting */ 680#define DCMD_TCI_CD 0x02 /* the phase for the block MOVE */ 681#define DCMD_TCI_MSG 0x04 /* instruction */ 682#define DCMD_TCI_OP_MASK 0x38 /* mask for opcode */ 683#define DCMD_TCI_OP_JUMP 0x00 /* JUMP */ 684#define DCMD_TCI_OP_CALL 0x08 /* CALL */ 685#define DCMD_TCI_OP_RETURN 0x10 /* RETURN */ 686#define DCMD_TCI_OP_INT 0x18 /* INT */ 687 688#define DCMD_TYPE_RWRI 0x40 /* Indicates I/O or register Read/Write 689 instruction */ 690#define DCMD_RWRI_OPC_MASK 0x38 /* Opcode mask */ 691#define DCMD_RWRI_OPC_WRITE 0x28 /* Write SFBR to register */ 692#define DCMD_RWRI_OPC_READ 0x30 /* Read register to SFBR */ 693#define DCMD_RWRI_OPC_MODIFY 0x38 /* Modify in place */ 694 695#define DCMD_RWRI_OP_MASK 0x07 696#define DCMD_RWRI_OP_MOVE 0x00 697#define DCMD_RWRI_OP_SHL 0x01 698#define DCMD_RWRI_OP_OR 0x02 699#define DCMD_RWRI_OP_XOR 0x03 700#define DCMD_RWRI_OP_AND 0x04 701#define DCMD_RWRI_OP_SHR 0x05 702#define DCMD_RWRI_OP_ADD 0x06 703#define DCMD_RWRI_OP_ADDC 0x07 704 705#define DCMD_TYPE_MMI 0xc0 /* Indicates a Memory Move instruction 706 (three words) */ 707 708 709#define DNAD_REG 0x28 /* through 0x2b DMA next address for 710 data */ 711#define DSP_REG 0x2c /* through 0x2f DMA SCRIPTS pointer rw */ 712#define DSPS_REG 0x30 /* through 0x33 DMA SCRIPTS pointer 713 save rw */ 714#define DMODE_REG_00 0x34 /* DMA mode rw */ 715#define DMODE_00_BL1 0x80 /* Burst length bits */ 716#define DMODE_00_BL0 0x40 717#define DMODE_BL_MASK 0xc0 718/* Burst lengths (800) */ 719#define DMODE_BL_2 0x00 /* 2 transfer */ 720#define DMODE_BL_4 0x40 /* 4 transfers */ 721#define DMODE_BL_8 0x80 /* 8 transfers */ 722#define DMODE_BL_16 0xc0 /* 16 transfers */ 723 724#define DMODE_10_BL_1 0x00 /* 1 transfer */ 725#define DMODE_10_BL_2 0x40 /* 2 transfers */ 726#define DMODE_10_BL_4 0x80 /* 4 transfers */ 727#define DMODE_10_BL_8 0xc0 /* 8 transfers */ 728#define DMODE_10_FC2 0x20 /* Driven to FC2 pin */ 729#define DMODE_10_FC1 0x10 /* Driven to FC1 pin */ 730#define DMODE_710_PD 0x08 /* Program/data on FC0 pin */ 731#define DMODE_710_UO 0x02 /* User prog. output */ 732 733#define DMODE_700_BW16 0x20 /* Host buswidth = 16 */ 734#define DMODE_700_286 0x10 /* 286 mode */ 735#define DMODE_700_IOM 0x08 /* Transfer to IO port */ 736#define DMODE_700_FAM 0x04 /* Fixed address mode */ 737#define DMODE_700_PIPE 0x02 /* Pipeline mode disables 738 * automatic fetch / exec 739 */ 740#define DMODE_MAN 0x01 /* Manual start mode, 741 * requires a 1 to be written 742 * to the start DMA bit in the DCNTL 743 * register to run scripts 744 */ 745 746#define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 ) 747 748/* NCR53c800 series only */ 749#define SCRATCHA_REG_800 0x34 /* through 0x37 Scratch A rw */ 750/* NCR53c710 only */ 751#define SCRATCHB_REG_10 0x34 /* through 0x37 scratch B rw */ 752 753#define DMODE_REG_10 0x38 /* DMA mode rw, NCR53c710 and newer */ 754#define DMODE_800_SIOM 0x20 /* Source IO = 1 */ 755#define DMODE_800_DIOM 0x10 /* Destination IO = 1 */ 756#define DMODE_800_ERL 0x08 /* Enable Read Line */ 757 758/* 35-38 are reserved on 700 and 700-66 series chips */ 759#define DIEN_REG 0x39 /* DMA interrupt enable rw */ 760/* 0x80, 0x40, and 0x20 are reserved on 700-series chips */ 761#define DIEN_800_MDPE 0x40 /* Master data parity error */ 762#define DIEN_800_BF 0x20 /* BUS fault */ 763#define DIEN_700_BF 0x20 /* BUS fault */ 764#define DIEN_ABRT 0x10 /* Enable aborted interrupt */ 765#define DIEN_SSI 0x08 /* Enable single step interrupt */ 766#define DIEN_SIR 0x04 /* Enable SCRIPTS INT command 767 * interrupt 768 */ 769/* 0x02 is reserved on 800 series chips */ 770#define DIEN_700_WTD 0x02 /* Enable watchdog timeout interrupt */ 771#define DIEN_700_OPC 0x01 /* Enable illegal instruction 772 * interrupt 773 */ 774#define DIEN_800_IID 0x01 /* Same meaning, different name */ 775 776/* 777 * DMA watchdog timer rw 778 * set in 16 CLK input periods. 779 */ 780#define DWT_REG 0x3a 781 782/* DMA control rw */ 783#define DCNTL_REG 0x3b 784#define DCNTL_700_CF1 0x80 /* Clock divisor bits */ 785#define DCNTL_700_CF0 0x40 786#define DCNTL_700_CF_MASK 0xc0 787/* Clock divisors Divisor SCLK range (MHZ) */ 788#define DCNTL_700_CF_2 0x00 /* 2.0 37.51-50.00 */ 789#define DCNTL_700_CF_1_5 0x40 /* 1.5 25.01-37.50 */ 790#define DCNTL_700_CF_1 0x80 /* 1.0 16.67-25.00 */ 791#define DCNTL_700_CF_3 0xc0 /* 3.0 50.01-66.67 (53c700-66) */ 792 793#define DCNTL_700_S16 0x20 /* Load scripts 16 bits at a time */ 794#define DCNTL_SSM 0x10 /* Single step mode */ 795#define DCNTL_700_LLM 0x08 /* Low level mode, can only be set 796 * after selection */ 797#define DCNTL_800_IRQM 0x08 /* Totem pole IRQ pin */ 798#define DCNTL_STD 0x04 /* Start DMA / SCRIPTS */ 799/* 0x02 is reserved */ 800#define DCNTL_00_RST 0x01 /* Software reset, resets everything 801 * but 286 mode bit in DMODE. On the 802 * NCR53c710, this bit moved to CTEST8 803 */ 804#define DCNTL_10_COM 0x01 /* 700 software compatibility mode */ 805#define DCNTL_10_EA 0x20 /* Enable Ack - needed for MVME16x */ 806 807#define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16) 808 809 810/* NCR53c700-66 only */ 811#define SCRATCHB_REG_00 0x3c /* through 0x3f scratch b rw */ 812#define SCRATCHB_REG_800 0x5c /* through 0x5f scratch b rw */ 813/* NCR53c710 only */ 814#define ADDER_REG_10 0x3c /* Adder, NCR53c710 only */ 815 816#define SIEN1_REG_800 0x41 817#define SIEN1_800_STO 0x04 /* selection/reselection timeout */ 818#define SIEN1_800_GEN 0x02 /* general purpose timer */ 819#define SIEN1_800_HTH 0x01 /* handshake to handshake */ 820 821#define SIST1_REG_800 0x43 822#define SIST1_800_STO 0x04 /* selection/reselection timeout */ 823#define SIST1_800_GEN 0x02 /* general purpose timer */ 824#define SIST1_800_HTH 0x01 /* handshake to handshake */ 825 826#define SLPAR_REG_800 0x44 /* Parity */ 827 828#define MACNTL_REG_800 0x46 /* Memory access control */ 829#define MACNTL_800_TYP3 0x80 830#define MACNTL_800_TYP2 0x40 831#define MACNTL_800_TYP1 0x20 832#define MACNTL_800_TYP0 0x10 833#define MACNTL_800_DWR 0x08 834#define MACNTL_800_DRD 0x04 835#define MACNTL_800_PSCPT 0x02 836#define MACNTL_800_SCPTS 0x01 837 838#define GPCNTL_REG_800 0x47 /* General Purpose Pin Control */ 839 840/* Timeouts are expressed such that 0=off, 1=100us, doubling after that */ 841#define STIME0_REG_800 0x48 /* SCSI Timer Register 0 */ 842#define STIME0_800_HTH_MASK 0xf0 /* Handshake to Handshake timeout */ 843#define STIME0_800_HTH_SHIFT 4 844#define STIME0_800_SEL_MASK 0x0f /* Selection timeout */ 845#define STIME0_800_SEL_SHIFT 0 846 847#define STIME1_REG_800 0x49 848#define STIME1_800_GEN_MASK 0x0f /* General purpose timer */ 849 850#define RESPID_REG_800 0x4a /* Response ID, bit fielded. 8 851 bits on narrow chips, 16 on WIDE */ 852 853#define STEST0_REG_800 0x4c 854#define STEST0_800_SLT 0x08 /* Selection response logic test */ 855#define STEST0_800_ART 0x04 /* Arbitration priority encoder test */ 856#define STEST0_800_SOZ 0x02 /* Synchronous offset zero */ 857#define STEST0_800_SOM 0x01 /* Synchronous offset maximum */ 858 859#define STEST1_REG_800 0x4d 860#define STEST1_800_SCLK 0x80 /* Disable SCSI clock */ 861 862#define STEST2_REG_800 0x4e 863#define STEST2_800_SCE 0x80 /* Enable SOCL/SODL */ 864#define STEST2_800_ROF 0x40 /* Reset SCSI sync offset */ 865#define STEST2_800_SLB 0x10 /* Enable SCSI loopback mode */ 866#define STEST2_800_SZM 0x08 /* SCSI high impedance mode */ 867#define STEST2_800_EXT 0x02 /* Extend REQ/ACK filter 30 to 60ns */ 868#define STEST2_800_LOW 0x01 /* SCSI low level mode */ 869 870#define STEST3_REG_800 0x4f 871#define STEST3_800_TE 0x80 /* Enable active negation */ 872#define STEST3_800_STR 0x40 /* SCSI FIFO test read */ 873#define STEST3_800_HSC 0x20 /* Halt SCSI clock */ 874#define STEST3_800_DSI 0x10 /* Disable single initiator response */ 875#define STEST3_800_TTM 0x04 /* Time test mode */ 876#define STEST3_800_CSF 0x02 /* Clear SCSI FIFO */ 877#define STEST3_800_STW 0x01 /* SCSI FIFO test write */ 878 879#define OPTION_PARITY 0x1 /* Enable parity checking */ 880#define OPTION_TAGGED_QUEUE 0x2 /* Enable SCSI-II tagged queuing */ 881#define OPTION_700 0x8 /* Always run NCR53c700 scripts */ 882#define OPTION_INTFLY 0x10 /* Use INTFLY interrupts */ 883#define OPTION_DEBUG_INTR 0x20 /* Debug interrupts */ 884#define OPTION_DEBUG_INIT_ONLY 0x40 /* Run initialization code and 885 simple test code, return 886 DID_NO_CONNECT if any SCSI 887 commands are attempted. */ 888#define OPTION_DEBUG_READ_ONLY 0x80 /* Return DID_ERROR if any 889 SCSI write is attempted */ 890#define OPTION_DEBUG_TRACE 0x100 /* Animated trace mode, print 891 each address and instruction 892 executed to debug buffer. */ 893#define OPTION_DEBUG_SINGLE 0x200 /* stop after executing one 894 instruction */ 895#define OPTION_SYNCHRONOUS 0x400 /* Enable sync SCSI. */ 896#define OPTION_MEMORY_MAPPED 0x800 /* NCR registers have valid 897 memory mapping */ 898#define OPTION_IO_MAPPED 0x1000 /* NCR registers have valid 899 I/O mapping */ 900#define OPTION_DEBUG_PROBE_ONLY 0x2000 /* Probe only, don't even init */ 901#define OPTION_DEBUG_TESTS_ONLY 0x4000 /* Probe, init, run selected tests */ 902#define OPTION_DEBUG_TEST0 0x08000 /* Run test 0 */ 903#define OPTION_DEBUG_TEST1 0x10000 /* Run test 1 */ 904#define OPTION_DEBUG_TEST2 0x20000 /* Run test 2 */ 905#define OPTION_DEBUG_DUMP 0x40000 /* Dump commands */ 906#define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */ 907#define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */ 908#define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */ 909#define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */ 910#define OPTION_DEBUG_DSA 0x800000 911#define OPTION_DEBUG_CORRUPTION 0x1000000 /* Detect script corruption */ 912#define OPTION_DEBUG_SDTR 0x2000000 /* Debug SDTR problem */ 913#define OPTION_DEBUG_MISMATCH 0x4000000 /* Debug phase mismatches */ 914#define OPTION_DISCONNECT 0x8000000 /* Allow disconnect */ 915#define OPTION_DEBUG_DISCONNECT 0x10000000 916#define OPTION_ALWAYS_SYNCHRONOUS 0x20000000 /* Negotiate sync. transfers 917 on power up */ 918#define OPTION_DEBUG_QUEUES 0x80000000 919#define OPTION_DEBUG_ALLOCATION 0x100000000LL 920#define OPTION_DEBUG_SYNCHRONOUS 0x200000000LL /* Sanity check SXFER and 921 SCNTL3 registers */ 922#define OPTION_NO_ASYNC 0x400000000LL /* Don't automagically send 923 SDTR for async transfers when 924 we haven't been told to do 925 a synchronous transfer. */ 926#define OPTION_NO_PRINT_RACE 0x800000000LL /* Don't print message when 927 the reselect/WAIT DISCONNECT 928 race condition hits */ 929#if !defined(PERM_OPTIONS) 930#define PERM_OPTIONS 0 931#endif 932 933/* 934 * Some data which is accessed by the NCR chip must be 4-byte aligned. 935 * For some hosts the default is less than that (eg. 68K uses 2-byte). 936 * Alignment has only been forced where it is important; also if one 937 * 32 bit structure field is aligned then it is assumed that following 938 * 32 bit fields are also aligned. Take care when adding fields 939 * which are other than 32 bit. 940 */ 941 942struct NCR53c7x0_synchronous { 943 u32 select_indirect /* Value used for indirect selection */ 944 __attribute__ ((aligned (4))); 945 u32 sscf_710; /* Used to set SSCF bits for 710 */ 946 u32 script[8]; /* Size ?? Script used when target is 947 reselected */ 948 unsigned char synchronous_want[5]; /* Per target desired SDTR */ 949/* 950 * Set_synchronous programs these, select_indirect and current settings after 951 * int_debug_should show a match. 952 */ 953 unsigned char sxfer_sanity, scntl3_sanity; 954}; 955 956#define CMD_FLAG_SDTR 1 /* Initiating synchronous 957 transfer negotiation */ 958#define CMD_FLAG_WDTR 2 /* Initiating wide transfer 959 negotiation */ 960#define CMD_FLAG_DID_SDTR 4 /* did SDTR */ 961#define CMD_FLAG_DID_WDTR 8 /* did WDTR */ 962 963struct NCR53c7x0_table_indirect { 964 u32 count; 965 void *address; 966}; 967 968enum ncr_event { 969 EVENT_NONE = 0, 970/* 971 * Order is IMPORTANT, since these must correspond to the event interrupts 972 * in 53c7,8xx.scr 973 */ 974 975 EVENT_ISSUE_QUEUE = 0x5000000, /* 0 Command was added to issue queue */ 976 EVENT_START_QUEUE, /* 1 Command moved to start queue */ 977 EVENT_SELECT, /* 2 Command completed selection */ 978 EVENT_DISCONNECT, /* 3 Command disconnected */ 979 EVENT_RESELECT, /* 4 Command reselected */ 980 EVENT_COMPLETE, /* 5 Command completed */ 981 EVENT_IDLE, /* 6 */ 982 EVENT_SELECT_FAILED, /* 7 */ 983 EVENT_BEFORE_SELECT, /* 8 */ 984 EVENT_RESELECT_FAILED /* 9 */ 985}; 986 987struct NCR53c7x0_event { 988 enum ncr_event event; /* What type of event */ 989 unsigned char target; 990 unsigned char lun; 991 struct timeval time; 992 u32 *dsa; /* What's in the DSA register now (virt) */ 993/* 994 * A few things from that SCSI pid so we know what happened after 995 * the Scsi_Cmnd structure in question may have disappeared. 996 */ 997 unsigned long pid; /* The SCSI PID which caused this 998 event */ 999 unsigned char cmnd[12]; 1000}; 1001 1002/* 1003 * Things in the NCR53c7x0_cmd structure are split into two parts : 1004 * 1005 * 1. A fixed portion, for things which are not accessed directly by static NCR 1006 * code (ie, are referenced only by the Linux side of the driver, 1007 * or only by dynamically generated code). 1008 * 1009 * 2. The DSA portion, for things which are accessed directly by static NCR 1010 * code. 1011 * 1012 * This is a little ugly, but it 1013 * 1. Avoids conflicts between the NCR code's picture of the structure, and 1014 * Linux code's idea of what it looks like. 1015 * 1016 * 2. Minimizes the pain in the Linux side of the code needed 1017 * to calculate real dsa locations for things, etc. 1018 * 1019 */ 1020 1021struct NCR53c7x0_cmd { 1022 void *real; /* Real, unaligned address for 1023 free function */ 1024 void (* free)(void *, int); /* Command to deallocate; NULL 1025 for structures allocated with 1026 scsi_register, etc. */ 1027 Scsi_Cmnd *cmd; /* Associated Scsi_Cmnd 1028 structure, Scsi_Cmnd points 1029 at NCR53c7x0_cmd using 1030 host_scribble structure */ 1031 1032 int size; /* scsi_malloc'd size of this 1033 structure */ 1034 1035 int flags; /* CMD_* flags */ 1036 1037 unsigned char cmnd[12]; /* CDB, copied from Scsi_Cmnd */ 1038 int result; /* Copy to Scsi_Cmnd when done */ 1039 1040 struct { /* Private non-cached bounce buffer */ 1041 unsigned char buf[256]; 1042 u32 addr; 1043 u32 len; 1044 } bounce; 1045 1046/* 1047 * SDTR and WIDE messages are an either/or affair 1048 * in this message, since we will go into message out and send 1049 * _the whole mess_ without dropping out of message out to 1050 * let the target go into message in after sending the first 1051 * message. 1052 */ 1053 1054 unsigned char select[11]; /* Select message, includes 1055 IDENTIFY 1056 (optional) QUEUE TAG 1057 (optional) SDTR or WDTR 1058 */ 1059 1060 1061 volatile struct NCR53c7x0_cmd *next; /* Linux maintained lists (free, 1062 running, eventually finished */ 1063 1064 1065 u32 *data_transfer_start; /* Start of data transfer routines */ 1066 u32 *data_transfer_end; /* Address after end of data transfer o 1067 routines */ 1068/* 1069 * The following three fields were moved from the DSA proper to here 1070 * since only dynamically generated NCR code refers to them, meaning 1071 * we don't need dsa_* absolutes, and it is simpler to let the 1072 * host code refer to them directly. 1073 */ 1074 1075 u32 residual[6] __attribute__ ((aligned (4))); 1076 /* Residual data transfer which 1077 allows pointer code to work 1078 right. 1079 1080 [0-1] : Conditional call to 1081 appropriate other transfer 1082 routine. 1083 [2-3] : Residual block transfer 1084 instruction. 1085 [4-5] : Jump to instruction 1086 after splice. 1087 */ 1088 u32 saved_residual[6]; /* Copy of old residual, so we 1089 can get another partial 1090 transfer and still recover 1091 */ 1092 1093 u32 saved_data_pointer; /* Saved data pointer */ 1094 1095 u32 dsa_next_addr; /* _Address_ of dsa_next field 1096 in this dsa for RISCy 1097 style constant. */ 1098 1099 u32 dsa_addr; /* Address of dsa; RISCy style 1100 constant */ 1101 1102 u32 dsa[0]; /* Variable length (depending 1103 on host type, number of scatter / 1104 gather buffers, etc). */ 1105}; 1106 1107struct NCR53c7x0_break { 1108 u32 *address, old_instruction[2]; 1109 struct NCR53c7x0_break *next; 1110 unsigned char old_size; /* Size of old instruction */ 1111}; 1112 1113/* Indicates that the NCR is not executing code */ 1114#define STATE_HALTED 0 1115/* 1116 * Indicates that the NCR is executing the wait for select / reselect 1117 * script. Only used when running NCR53c700 compatible scripts, only 1118 * state during which an ABORT is _not_ considered an error condition. 1119 */ 1120#define STATE_WAITING 1 1121/* Indicates that the NCR is executing other code. */ 1122#define STATE_RUNNING 2 1123/* 1124 * Indicates that the NCR was being aborted. 1125 */ 1126#define STATE_ABORTING 3 1127/* Indicates that the NCR was successfully aborted. */ 1128#define STATE_ABORTED 4 1129/* Indicates that the NCR has been disabled due to a fatal error */ 1130#define STATE_DISABLED 5 1131 1132/* 1133 * Where knowledge of SCSI SCRIPT(tm) specified values are needed 1134 * in an interrupt handler, an interrupt handler exists for each 1135 * different SCSI script so we don't have name space problems. 1136 * 1137 * Return values of these handlers are as follows : 1138 */ 1139#define SPECIFIC_INT_NOTHING 0 /* don't even restart */ 1140#define SPECIFIC_INT_RESTART 1 /* restart at the next instruction */ 1141#define SPECIFIC_INT_ABORT 2 /* recoverable error, abort cmd */ 1142#define SPECIFIC_INT_PANIC 3 /* unrecoverable error, panic */ 1143#define SPECIFIC_INT_DONE 4 /* normal command completion */ 1144#define SPECIFIC_INT_BREAK 5 /* break point encountered */ 1145 1146struct NCR53c7x0_hostdata { 1147 int size; /* Size of entire Scsi_Host 1148 structure */ 1149 int board; /* set to board type, useful if 1150 we have host specific things, 1151 ie, a general purpose I/O 1152 bit is being used to enable 1153 termination, etc. */ 1154 1155 int chip; /* set to chip type; 700-66 is 1156 700-66, rest are last three 1157 digits of part number */ 1158 1159 char valid_ids[8]; /* Valid SCSI ID's for adapter */ 1160 1161 u32 *dsp; /* dsp to restart with after 1162 all stacked interrupts are 1163 handled. */ 1164 1165 unsigned dsp_changed:1; /* Has dsp changed within this 1166 set of stacked interrupts ? */ 1167 1168 unsigned char dstat; /* Most recent value of dstat */ 1169 unsigned dstat_valid:1; 1170 1171 unsigned expecting_iid:1; /* Expect IID interrupt */ 1172 unsigned expecting_sto:1; /* Expect STO interrupt */ 1173 1174 /* 1175 * The code stays cleaner if we use variables with function 1176 * pointers and offsets that are unique for the different 1177 * scripts rather than having a slew of switch(hostdata->chip) 1178 * statements. 1179 * 1180 * It also means that the #defines from the SCSI SCRIPTS(tm) 1181 * don't have to be visible outside of the script-specific 1182 * instructions, preventing name space pollution. 1183 */ 1184 1185 void (* init_fixup)(struct Scsi_Host *host); 1186 void (* init_save_regs)(struct Scsi_Host *host); 1187 void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd); 1188 void (* soft_reset)(struct Scsi_Host *host); 1189 int (* run_tests)(struct Scsi_Host *host); 1190 1191 /* 1192 * Called when DSTAT_SIR is set, indicating an interrupt generated 1193 * by the INT instruction, where values are unique for each SCSI 1194 * script. Should return one of the SPEC_* values. 1195 */ 1196 1197 int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd); 1198 1199 int dsa_len; /* Size of DSA structure */ 1200 1201 /* 1202 * Location of DSA fields for the SCSI SCRIPT corresponding to this 1203 * chip. 1204 */ 1205 1206 s32 dsa_start; 1207 s32 dsa_end; 1208 s32 dsa_next; 1209 s32 dsa_prev; 1210 s32 dsa_cmnd; 1211 s32 dsa_select; 1212 s32 dsa_msgout; 1213 s32 dsa_cmdout; 1214 s32 dsa_dataout; 1215 s32 dsa_datain; 1216 s32 dsa_msgin; 1217 s32 dsa_msgout_other; 1218 s32 dsa_write_sync; 1219 s32 dsa_write_resume; 1220 s32 dsa_check_reselect; 1221 s32 dsa_status; 1222 s32 dsa_saved_pointer; 1223 s32 dsa_jump_dest; 1224 1225 /* 1226 * Important entry points that generic fixup code needs 1227 * to know about, fixed up. 1228 */ 1229 1230 s32 E_accept_message; 1231 s32 E_command_complete; 1232 s32 E_data_transfer; 1233 s32 E_dsa_code_template; 1234 s32 E_dsa_code_template_end; 1235 s32 E_end_data_transfer; 1236 s32 E_msg_in; 1237 s32 E_initiator_abort; 1238 s32 E_other_transfer; 1239 s32 E_other_in; 1240 s32 E_other_out; 1241 s32 E_target_abort; 1242 s32 E_debug_break; 1243 s32 E_reject_message; 1244 s32 E_respond_message; 1245 s32 E_select; 1246 s32 E_select_msgout; 1247 s32 E_test_0; 1248 s32 E_test_1; 1249 s32 E_test_2; 1250 s32 E_test_3; 1251 s32 E_dsa_zero; 1252 s32 E_cmdout_cmdout; 1253 s32 E_wait_reselect; 1254 s32 E_dsa_code_begin; 1255 1256 long long options; /* Bitfielded set of options enabled */ 1257 volatile u32 test_completed; /* Test completed */ 1258 int test_running; /* Test currently running */ 1259 s32 test_source 1260 __attribute__ ((aligned (4))); 1261 volatile s32 test_dest; 1262 1263 volatile int state; /* state of driver, only used for 1264 OPTION_700 */ 1265 1266 unsigned char dmode; /* 1267 * set to the address of the DMODE 1268 * register for this chip. 1269 */ 1270 unsigned char istat; /* 1271 * set to the address of the ISTAT 1272 * register for this chip. 1273 */ 1274 1275 int scsi_clock; /* 1276 * SCSI clock in HZ. 0 may be used 1277 * for unknown, although this will 1278 * disable synchronous negotiation. 1279 */ 1280 1281 volatile int intrs; /* Number of interrupts */ 1282 volatile int resets; /* Number of SCSI resets */ 1283 unsigned char saved_dmode; 1284 unsigned char saved_ctest4; 1285 unsigned char saved_ctest7; 1286 unsigned char saved_dcntl; 1287 unsigned char saved_scntl3; 1288 1289 unsigned char this_id_mask; 1290 1291 /* Debugger information */ 1292 struct NCR53c7x0_break *breakpoints, /* Linked list of all break points */ 1293 *breakpoint_current; /* Current breakpoint being stepped 1294 through, NULL if we are running 1295 normally. */ 1296#ifdef NCR_DEBUG 1297 int debug_size; /* Size of debug buffer */ 1298 volatile int debug_count; /* Current data count */ 1299 volatile char *debug_buf; /* Output ring buffer */ 1300 volatile char *debug_write; /* Current write pointer */ 1301 volatile char *debug_read; /* Current read pointer */ 1302#endif /* def NCR_DEBUG */ 1303 1304 int debug_print_limit; /* Number of commands to print 1305 out exhaustive debugging 1306 information for if 1307 OPTION_DEBUG_DUMP is set */ 1308 1309 unsigned char debug_lun_limit[16]; /* If OPTION_DEBUG_TARGET_LIMIT 1310 set, puke if commands are sent 1311 to other target/lun combinations */ 1312 1313 int debug_count_limit; /* Number of commands to execute 1314 before puking to limit debugging 1315 output */ 1316 1317 1318 volatile unsigned idle:1; /* set to 1 if idle */ 1319 1320 /* 1321 * Table of synchronous+wide transfer parameters set on a per-target 1322 * basis. 1323 */ 1324 1325 volatile struct NCR53c7x0_synchronous sync[16] 1326 __attribute__ ((aligned (4))); 1327 1328 volatile Scsi_Cmnd *issue_queue 1329 __attribute__ ((aligned (4))); 1330 /* waiting to be issued by 1331 Linux driver */ 1332 volatile struct NCR53c7x0_cmd *running_list; 1333 /* commands running, maintained 1334 by Linux driver */ 1335 1336 volatile struct NCR53c7x0_cmd *ncrcurrent; /* currently connected 1337 nexus, ONLY valid for 1338 NCR53c700/NCR53c700-66 1339 */ 1340 1341 volatile struct NCR53c7x0_cmd *spare; /* pointer to spare, 1342 allocated at probe time, 1343 which we can use for 1344 initialization */ 1345 volatile struct NCR53c7x0_cmd *free; 1346 int max_cmd_size; /* Maximum size of NCR53c7x0_cmd 1347 based on number of 1348 scatter/gather segments, etc. 1349 */ 1350 volatile int num_cmds; /* Number of commands 1351 allocated */ 1352 volatile int extra_allocate; 1353 volatile unsigned char cmd_allocated[16]; /* Have we allocated commands 1354 for this target yet? If not, 1355 do so ASAP */ 1356 volatile unsigned char busy[16][8]; /* number of commands 1357 executing on each target 1358 */ 1359 /* 1360 * Eventually, I'll switch to a coroutine for calling 1361 * cmd->done(cmd), etc. so that we can overlap interrupt 1362 * processing with this code for maximum performance. 1363 */ 1364 1365 volatile struct NCR53c7x0_cmd *finished_queue; 1366 1367 /* Shared variables between SCRIPT and host driver */ 1368 volatile u32 *schedule 1369 __attribute__ ((aligned (4))); /* Array of JUMPs to dsa_begin 1370 routines of various DSAs. 1371 When not in use, replace 1372 with jump to next slot */ 1373 1374 1375 volatile unsigned char msg_buf[16]; /* buffer for messages 1376 other than the command 1377 complete message */ 1378 1379 /* Per-target default synchronous and WIDE messages */ 1380 volatile unsigned char synchronous_want[16][5]; 1381 volatile unsigned char wide_want[16][4]; 1382 1383 /* Bit fielded set of targets we want to speak synchronously with */ 1384 volatile u16 initiate_sdtr; 1385 /* Bit fielded set of targets we want to speak wide with */ 1386 volatile u16 initiate_wdtr; 1387 /* Bit fielded list of targets we've talked to. */ 1388 volatile u16 talked_to; 1389 1390 /* Array of bit-fielded lun lists that we need to request_sense */ 1391 volatile unsigned char request_sense[16]; 1392 1393 u32 addr_reconnect_dsa_head 1394 __attribute__ ((aligned (4))); /* RISCy style constant, 1395 address of following */ 1396 volatile u32 reconnect_dsa_head; 1397 /* Data identifying nexus we are trying to match during reselection */ 1398 volatile unsigned char reselected_identify; /* IDENTIFY message */ 1399 volatile unsigned char reselected_tag; /* second byte of queue tag 1400 message or 0 */ 1401 1402 /* These were static variables before we moved them */ 1403 1404 s32 NCR53c7xx_zero 1405 __attribute__ ((aligned (4))); 1406 s32 NCR53c7xx_sink; 1407 u32 NOP_insn; 1408 char NCR53c7xx_msg_reject; 1409 char NCR53c7xx_msg_abort; 1410 char NCR53c7xx_msg_nop; 1411 1412 /* 1413 * Following item introduced by RGH to support NCRc710, which is 1414 * VERY brain-dead when it come to memory moves 1415 */ 1416 1417 /* DSA save area used only by the NCR chip */ 1418 volatile unsigned long saved2_dsa 1419 __attribute__ ((aligned (4))); 1420 1421 volatile unsigned long emulated_intfly 1422 __attribute__ ((aligned (4))); 1423 1424 volatile int event_size, event_index; 1425 volatile struct NCR53c7x0_event *events; 1426 1427 /* If we need to generate code to kill off the currently connected 1428 command, this is where we do it. Should have a BMI instruction 1429 to source or sink the current data, followed by a JUMP 1430 to abort_connected */ 1431 1432 u32 *abort_script; 1433 1434 int script_count; /* Size of script in words */ 1435 u32 script[0]; /* Relocated SCSI script */ 1436 1437}; 1438 1439#define IRQ_NONE 255 1440#define DMA_NONE 255 1441#define IRQ_AUTO 254 1442#define DMA_AUTO 254 1443 1444#define BOARD_GENERIC 0 1445 1446#define NCR53c7x0_insn_size(insn) \ 1447 (((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2) 1448 1449 1450#define NCR53c7x0_local_declare() \ 1451 volatile unsigned char *NCR53c7x0_address_memory; \ 1452 unsigned int NCR53c7x0_address_io; \ 1453 int NCR53c7x0_memory_mapped 1454 1455#define NCR53c7x0_local_setup(host) \ 1456 NCR53c7x0_address_memory = (void *) (host)->base; \ 1457 NCR53c7x0_address_io = (unsigned int) (host)->io_port; \ 1458 NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *) \ 1459 host->hostdata[0])-> options & OPTION_MEMORY_MAPPED 1460 1461#ifdef BIG_ENDIAN 1462/* These could be more efficient, given that we are always memory mapped, 1463 * but they don't give the same problems as the write macros, so leave 1464 * them. */ 1465#ifdef __mc68000__ 1466#define NCR53c7x0_read8(address) \ 1467 ((unsigned int)raw_inb((u32)NCR53c7x0_address_memory + ((u32)(address)^3)) ) 1468 1469#define NCR53c7x0_read16(address) \ 1470 ((unsigned int)raw_inw((u32)NCR53c7x0_address_memory + ((u32)(address)^2))) 1471#else 1472#define NCR53c7x0_read8(address) \ 1473 (NCR53c7x0_memory_mapped ? \ 1474 (unsigned int)readb((u32)NCR53c7x0_address_memory + ((u32)(address)^3)) : \ 1475 inb(NCR53c7x0_address_io + (address))) 1476 1477#define NCR53c7x0_read16(address) \ 1478 (NCR53c7x0_memory_mapped ? \ 1479 (unsigned int)readw((u32)NCR53c7x0_address_memory + ((u32)(address)^2)) : \ 1480 inw(NCR53c7x0_address_io + (address))) 1481#endif /* mc68000 */ 1482#else 1483#define NCR53c7x0_read8(address) \ 1484 (NCR53c7x0_memory_mapped ? \ 1485 (unsigned int)readb((u32)NCR53c7x0_address_memory + (u32)(address)) : \ 1486 inb(NCR53c7x0_address_io + (address))) 1487 1488#define NCR53c7x0_read16(address) \ 1489 (NCR53c7x0_memory_mapped ? \ 1490 (unsigned int)readw((u32)NCR53c7x0_address_memory + (u32)(address)) : \ 1491 inw(NCR53c7x0_address_io + (address))) 1492#endif 1493 1494#ifdef __mc68000__ 1495#define NCR53c7x0_read32(address) \ 1496 ((unsigned int) raw_inl((u32)NCR53c7x0_address_memory + (u32)(address))) 1497#else 1498#define NCR53c7x0_read32(address) \ 1499 (NCR53c7x0_memory_mapped ? \ 1500 (unsigned int) readl((u32)NCR53c7x0_address_memory + (u32)(address)) : \ 1501 inl(NCR53c7x0_address_io + (address))) 1502#endif /* mc68000*/ 1503 1504#ifdef BIG_ENDIAN 1505/* If we are big-endian, then we are not Intel, so probably don't have 1506 * an i/o map as well as a memory map. So, let's assume memory mapped. 1507 * Also, I am having terrible problems trying to persuade the compiler 1508 * not to lay down code which does a read after write for these macros. 1509 * If you remove 'volatile' from writeb() and friends it is ok.... 1510 */ 1511 1512#define NCR53c7x0_write8(address,value) \ 1513 *(volatile unsigned char *) \ 1514 ((u32)NCR53c7x0_address_memory + ((u32)(address)^3)) = (value) 1515 1516#define NCR53c7x0_write16(address,value) \ 1517 *(volatile unsigned short *) \ 1518 ((u32)NCR53c7x0_address_memory + ((u32)(address)^2)) = (value) 1519 1520#define NCR53c7x0_write32(address,value) \ 1521 *(volatile unsigned long *) \ 1522 ((u32)NCR53c7x0_address_memory + ((u32)(address))) = (value) 1523 1524#else 1525 1526#define NCR53c7x0_write8(address,value) \ 1527 (NCR53c7x0_memory_mapped ? \ 1528 ({writeb((value), (u32)NCR53c7x0_address_memory + (u32)(address)); mb();}) : \ 1529 outb((value), NCR53c7x0_address_io + (address))) 1530 1531#define NCR53c7x0_write16(address,value) \ 1532 (NCR53c7x0_memory_mapped ? \ 1533 ({writew((value), (u32)NCR53c7x0_address_memory + (u32)(address)); mb();}) : \ 1534 outw((value), NCR53c7x0_address_io + (address))) 1535 1536#define NCR53c7x0_write32(address,value) \ 1537 (NCR53c7x0_memory_mapped ? \ 1538 ({writel((value), (u32)NCR53c7x0_address_memory + (u32)(address)); mb();}) : \ 1539 outl((value), NCR53c7x0_address_io + (address))) 1540 1541#endif 1542 1543/* Patch arbitrary 32 bit words in the script */ 1544#define patch_abs_32(script, offset, symbol, value) \ 1545 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \ 1546 (u32)); ++i) { \ 1547 (script)[A_##symbol##_used[i] - (offset)] += (value); \ 1548 if (hostdata->options & OPTION_DEBUG_FIXUP) \ 1549 printk("scsi%d : %s reference %d at 0x%x in %s is now 0x%x\n",\ 1550 host->host_no, #symbol, i, A_##symbol##_used[i] - \ 1551 (int)(offset), #script, (script)[A_##symbol##_used[i] - \ 1552 (offset)]); \ 1553 } 1554 1555/* Patch read/write instruction immediate field */ 1556#define patch_abs_rwri_data(script, offset, symbol, value) \ 1557 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \ 1558 (u32)); ++i) \ 1559 (script)[A_##symbol##_used[i] - (offset)] = \ 1560 ((script)[A_##symbol##_used[i] - (offset)] & \ 1561 ~DBC_RWRI_IMMEDIATE_MASK) | \ 1562 (((value) << DBC_RWRI_IMMEDIATE_SHIFT) & \ 1563 DBC_RWRI_IMMEDIATE_MASK) 1564 1565/* Patch transfer control instruction data field */ 1566#define patch_abs_tci_data(script, offset, symbol, value) \ 1567 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \ 1568 (u32)); ++i) \ 1569 (script)[A_##symbol##_used[i] - (offset)] = \ 1570 ((script)[A_##symbol##_used[i] - (offset)] & \ 1571 ~DBC_TCI_DATA_MASK) | \ 1572 (((value) << DBC_TCI_DATA_SHIFT) & \ 1573 DBC_TCI_DATA_MASK) 1574 1575/* Patch field in dsa structure (assignment should be +=?) */ 1576#define patch_dsa_32(dsa, symbol, word, value) \ 1577 { \ 1578 (dsa)[(hostdata->##symbol - hostdata->dsa_start) / sizeof(u32) \ 1579 + (word)] = (value); \ 1580 if (hostdata->options & OPTION_DEBUG_DSA) \ 1581 printk("scsi : dsa %s symbol %s(%d) word %d now 0x%x\n", \ 1582 #dsa, #symbol, hostdata->##symbol, \ 1583 (word), (u32) (value)); \ 1584 } 1585 1586/* Paranoid people could use panic() here. */ 1587#define FATAL(host) shutdown((host)); 1588 1589#endif /* NCR53c710_C */ 1590#endif /* NCR53c710_H */ 1591