1/* $Id: amd7930.h,v 1.1.1.1 2008/10/15 03:26:47 james26_jang Exp $ 2 * drivers/sbus/audio/amd7930.h 3 * 4 * Copyright (C) 1996 Thomas K. Dyas (tdyas@noc.rutgers.edu) 5 * 6 * Definitions for the AMD79C30 Digital Subscriber Controller which is 7 * used as an audio chip in sun4c architecture machines. The 8 * information in this file is based on Advanced Micro Devices 9 * Publication 09893, Rev G, Amendment /0, Final (a.k.a. the data 10 * sheet). 11 */ 12 13#ifndef _AMD7930_H_ 14#define _AMD7930_H_ 15 16#include <linux/types.h> 17#include <linux/version.h> 18 19/* Register interface presented to the CPU by the amd7930. */ 20#define CR 0x00UL /* Command Register (W) */ 21#define IR CR /* Interrupt Register (R) */ 22#define DR 0x01UL /* Data Register (R/W) */ 23#define DSR1 0x02UL /* D-channel Status Register 1 (R) */ 24#define DER 0x03UL /* D-channel Error Register (R) */ 25#define DCTB 0x04UL /* D-channel Transmit Buffer (W) */ 26#define DCRB DCTB /* D-channel Receive Buffer (R) */ 27#define BBTB 0x05UL /* Bb-channel Transmit Buffer (W) */ 28#define BBRB BBTB /* Bb-channel Receive Buffer (R) */ 29#define BCTB 0x06UL /* Bc-channel Transmit Buffer (W) */ 30#define BCRB BCTB /* Bc-channel Receive Buffer (R) */ 31#define DSR2 0x07UL /* D-channel Status Register 2 (R) */ 32 33/* Indirect registers in the Main Audio Processor. */ 34struct amd7930_map { 35 __u16 x[8]; 36 __u16 r[8]; 37 __u16 gx; 38 __u16 gr; 39 __u16 ger; 40 __u16 stgr; 41 __u16 ftgr; 42 __u16 atgr; 43 __u8 mmr1; 44 __u8 mmr2; 45}; 46 47 48/* After an amd7930 interrupt, reading the Interrupt Register (ir) 49 * clears the interrupt and returns a bitmask indicated which 50 * interrupt source(s) require service 51 */ 52 53#define AMR_IR_DTTHRSH 0x01 /* D-channel xmit threshold */ 54#define AMR_IR_DRTHRSH 0x02 /* D-channel recv threshold */ 55#define AMR_IR_DSRI 0x04 /* D-channel packet status */ 56#define AMR_IR_DERI 0x08 /* D-channel error */ 57#define AMR_IR_BBUF 0x10 /* B-channel data xfer */ 58#define AMR_IR_LSRI 0x20 /* LIU status */ 59#define AMR_IR_DSR2I 0x40 /* D-channel buffer status */ 60#define AMR_IR_MLTFRMI 0x80 /* multiframe or PP */ 61 62/* The amd7930 has "indirect registers" which are accessed by writing 63 * the register number into the Command Register and then reading or 64 * writing values from the Data Register as appropriate. We define the 65 * AMR_* macros to be the indirect register numbers and AM_* macros to 66 * be bits in whatever register is referred to. 67 */ 68 69/* Initialization */ 70#define AMR_INIT 0x21 71#define AM_INIT_ACTIVE 0x01 72#define AM_INIT_DATAONLY 0x02 73#define AM_INIT_POWERDOWN 0x03 74#define AM_INIT_DISABLE_INTS 0x04 75#define AMR_INIT2 0x20 76#define AM_INIT2_ENABLE_POWERDOWN 0x20 77#define AM_INIT2_ENABLE_MULTIFRAME 0x10 78 79/* Line Interface Unit */ 80#define AMR_LIU_LSR 0xA1 81#define AM_LIU_LSR_STATE 0x07 82#define AM_LIU_LSR_F3 0x08 83#define AM_LIU_LSR_F7 0x10 84#define AM_LIU_LSR_F8 0x20 85#define AM_LIU_LSR_HSW 0x40 86#define AM_LIU_LSR_HSW_CHG 0x80 87#define AMR_LIU_LPR 0xA2 88#define AMR_LIU_LMR1 0xA3 89#define AM_LIU_LMR1_B1_ENABL 0x01 90#define AM_LIU_LMR1_B2_ENABL 0x02 91#define AM_LIU_LMR1_F_DISABL 0x04 92#define AM_LIU_LMR1_FA_DISABL 0x08 93#define AM_LIU_LMR1_REQ_ACTIV 0x10 94#define AM_LIU_LMR1_F8_F3 0x20 95#define AM_LIU_LMR1_LIU_ENABL 0x40 96#define AMR_LIU_LMR2 0xA4 97#define AM_LIU_LMR2_DECHO 0x01 98#define AM_LIU_LMR2_DLOOP 0x02 99#define AM_LIU_LMR2_DBACKOFF 0x04 100#define AM_LIU_LMR2_EN_F3_INT 0x08 101#define AM_LIU_LMR2_EN_F8_INT 0x10 102#define AM_LIU_LMR2_EN_HSW_INT 0x20 103#define AM_LIU_LMR2_EN_F7_INT 0x40 104#define AMR_LIU_2_4 0xA5 105#define AMR_LIU_MF 0xA6 106#define AMR_LIU_MFSB 0xA7 107#define AMR_LIU_MFQB 0xA8 108 109/* Multiplexor */ 110#define AMR_MUX_MCR1 0x41 111#define AMR_MUX_MCR2 0x42 112#define AMR_MUX_MCR3 0x43 113#define AM_MUX_CHANNEL_B1 0x01 114#define AM_MUX_CHANNEL_B2 0x02 115#define AM_MUX_CHANNEL_Ba 0x03 116#define AM_MUX_CHANNEL_Bb 0x04 117#define AM_MUX_CHANNEL_Bc 0x05 118#define AM_MUX_CHANNEL_Bd 0x06 119#define AM_MUX_CHANNEL_Be 0x07 120#define AM_MUX_CHANNEL_Bf 0x08 121#define AMR_MUX_MCR4 0x44 122#define AM_MUX_MCR4_ENABLE_INTS 0x08 123#define AM_MUX_MCR4_REVERSE_Bb 0x10 124#define AM_MUX_MCR4_REVERSE_Bc 0x20 125#define AMR_MUX_1_4 0x45 126 127/* Main Audio Processor */ 128#define AMR_MAP_X 0x61 129#define AMR_MAP_R 0x62 130#define AMR_MAP_GX 0x63 131#define AMR_MAP_GR 0x64 132#define AMR_MAP_GER 0x65 133#define AMR_MAP_STGR 0x66 134#define AMR_MAP_FTGR_1_2 0x67 135#define AMR_MAP_ATGR_1_2 0x68 136#define AMR_MAP_MMR1 0x69 137#define AM_MAP_MMR1_ALAW 0x01 138#define AM_MAP_MMR1_GX 0x02 139#define AM_MAP_MMR1_GR 0x04 140#define AM_MAP_MMR1_GER 0x08 141#define AM_MAP_MMR1_X 0x10 142#define AM_MAP_MMR1_R 0x20 143#define AM_MAP_MMR1_STG 0x40 144#define AM_MAP_MMR1_LOOPBACK 0x80 145#define AMR_MAP_MMR2 0x6A 146#define AM_MAP_MMR2_AINB 0x01 147#define AM_MAP_MMR2_LS 0x02 148#define AM_MAP_MMR2_ENABLE_DTMF 0x04 149#define AM_MAP_MMR2_ENABLE_TONEGEN 0x08 150#define AM_MAP_MMR2_ENABLE_TONERING 0x10 151#define AM_MAP_MMR2_DISABLE_HIGHPASS 0x20 152#define AM_MAP_MMR2_DISABLE_AUTOZERO 0x40 153#define AMR_MAP_1_10 0x6B 154#define AMR_MAP_MMR3 0x6C 155#define AMR_MAP_STRA 0x6D 156#define AMR_MAP_STRF 0x6E 157#define AMR_MAP_PEAKX 0x70 158#define AMR_MAP_PEAKR 0x71 159#define AMR_MAP_15_16 0x72 160 161/* Data Link Controller */ 162#define AMR_DLC_FRAR_1_2_3 0x81 163#define AMR_DLC_SRAR_1_2_3 0x82 164#define AMR_DLC_TAR 0x83 165#define AMR_DLC_DRLR 0x84 166#define AMR_DLC_DTCR 0x85 167#define AMR_DLC_DMR1 0x86 168#define AMR_DLC_DMR1_DTTHRSH_INT 0x01 169#define AMR_DLC_DMR1_DRTHRSH_INT 0x02 170#define AMR_DLC_DMR1_TAR_ENABL 0x04 171#define AMR_DLC_DMR1_EORP_INT 0x08 172#define AMR_DLC_DMR1_EN_ADDR1 0x10 173#define AMR_DLC_DMR1_EN_ADDR2 0x20 174#define AMR_DLC_DMR1_EN_ADDR3 0x40 175#define AMR_DLC_DMR1_EN_ADDR4 0x80 176#define AMR_DLC_DMR1_EN_ADDRS 0xf0 177#define AMR_DLC_DMR2 0x87 178#define AMR_DLC_DMR2_RABRT_INT 0x01 179#define AMR_DLC_DMR2_RESID_INT 0x02 180#define AMR_DLC_DMR2_COLL_INT 0x04 181#define AMR_DLC_DMR2_FCS_INT 0x08 182#define AMR_DLC_DMR2_OVFL_INT 0x10 183#define AMR_DLC_DMR2_UNFL_INT 0x20 184#define AMR_DLC_DMR2_OVRN_INT 0x40 185#define AMR_DLC_DMR2_UNRN_INT 0x80 186#define AMR_DLC_1_7 0x88 187#define AMR_DLC_DRCR 0x89 188#define AMR_DLC_RNGR1 0x8A 189#define AMR_DLC_RNGR2 0x8B 190#define AMR_DLC_FRAR4 0x8C 191#define AMR_DLC_SRAR4 0x8D 192#define AMR_DLC_DMR3 0x8E 193#define AMR_DLC_DMR3_VA_INT 0x01 194#define AMR_DLC_DMR3_EOTP_INT 0x02 195#define AMR_DLC_DMR3_LBRP_INT 0x04 196#define AMR_DLC_DMR3_RBA_INT 0x08 197#define AMR_DLC_DMR3_LBT_INT 0x10 198#define AMR_DLC_DMR3_TBE_INT 0x20 199#define AMR_DLC_DMR3_RPLOST_INT 0x40 200#define AMR_DLC_DMR3_KEEP_FCS 0x80 201#define AMR_DLC_DMR4 0x8F 202#define AMR_DLC_DMR4_RCV_1 0x00 203#define AMR_DLC_DMR4_RCV_2 0x01 204#define AMR_DLC_DMR4_RCV_4 0x02 205#define AMR_DLC_DMR4_RCV_8 0x03 206#define AMR_DLC_DMR4_RCV_16 0x01 207#define AMR_DLC_DMR4_RCV_24 0x02 208#define AMR_DLC_DMR4_RCV_30 0x03 209#define AMR_DLC_DMR4_XMT_1 0x00 210#define AMR_DLC_DMR4_XMT_2 0x04 211#define AMR_DLC_DMR4_XMT_4 0x08 212#define AMR_DLC_DMR4_XMT_8 0x0c 213#define AMR_DLC_DMR4_XMT_10 0x08 214#define AMR_DLC_DMR4_XMT_14 0x0c 215#define AMR_DLC_DMR4_IDLE_MARK 0x00 216#define AMR_DLC_DMR4_IDLE_FLAG 0x10 217#define AMR_DLC_DMR4_ADDR_BOTH 0x00 218#define AMR_DLC_DMR4_ADDR_1ST 0x20 219#define AMR_DLC_DMR4_ADDR_2ND 0xa0 220#define AMR_DLC_DMR4_CR_ENABLE 0x40 221#define AMR_DLC_12_15 0x90 222#define AMR_DLC_ASR 0x91 223#define AMR_DLC_EFCR 0x92 224#define AMR_DLC_EFCR_EXTEND_FIFO 0x01 225#define AMR_DLC_EFCR_SEC_PKT_INT 0x02 226 227#define AMR_DSR1_VADDR 0x01 228#define AMR_DSR1_EORP 0x02 229#define AMR_DSR1_PKT_IP 0x04 230#define AMR_DSR1_DECHO_ON 0x08 231#define AMR_DSR1_DLOOP_ON 0x10 232#define AMR_DSR1_DBACK_OFF 0x20 233#define AMR_DSR1_EOTP 0x40 234#define AMR_DSR1_CXMT_ABRT 0x80 235 236#define AMR_DSR2_LBRP 0x01 237#define AMR_DSR2_RBA 0x02 238#define AMR_DSR2_RPLOST 0x04 239#define AMR_DSR2_LAST_BYTE 0x08 240#define AMR_DSR2_TBE 0x10 241#define AMR_DSR2_MARK_IDLE 0x20 242#define AMR_DSR2_FLAG_IDLE 0x40 243#define AMR_DSR2_SECOND_PKT 0x80 244 245#define AMR_DER_RABRT 0x01 246#define AMR_DER_RFRAME 0x02 247#define AMR_DER_COLLISION 0x04 248#define AMR_DER_FCS 0x08 249#define AMR_DER_OVFL 0x10 250#define AMR_DER_UNFL 0x20 251#define AMR_DER_OVRN 0x40 252#define AMR_DER_UNRN 0x80 253 254/* Peripheral Port */ 255#define AMR_PP_PPCR1 0xC0 256#define AMR_PP_PPSR 0xC1 257#define AMR_PP_PPIER 0xC2 258#define AMR_PP_MTDR 0xC3 259#define AMR_PP_MRDR 0xC3 260#define AMR_PP_CITDR0 0xC4 261#define AMR_PP_CIRDR0 0xC4 262#define AMR_PP_CITDR1 0xC5 263#define AMR_PP_CIRDR1 0xC5 264#define AMR_PP_PPCR2 0xC8 265#define AMR_PP_PPCR3 0xC9 266 267/* Give this chip a "default" sample rate */ 268#define AMD7930_RATE (8000) 269 270#endif /* _AMD7930_H_ */ 271