1/* 2 * Regular lowlevel cardbus driver ("yenta") 3 * 4 * (C) Copyright 1999, 2000 Linus Torvalds 5 */ 6#include <linux/init.h> 7#include <linux/pci.h> 8#include <linux/sched.h> 9#include <linux/interrupt.h> 10#include <linux/delay.h> 11#include <linux/module.h> 12 13#include <pcmcia/version.h> 14#include <pcmcia/cs_types.h> 15#include <pcmcia/ss.h> 16#include <pcmcia/cs.h> 17 18#include <asm/io.h> 19 20#include "yenta.h" 21#include "i82365.h" 22 23#define DEBUG(x,args...) 24 25/* Don't ask.. */ 26#define to_cycles(ns) ((ns)/120) 27#define to_ns(cycles) ((cycles)*120) 28 29/* 30 * Generate easy-to-use ways of reading a cardbus sockets 31 * regular memory space ("cb_xxx"), configuration space 32 * ("config_xxx") and compatibility space ("exca_xxxx") 33 */ 34static inline u32 cb_readl(pci_socket_t *socket, unsigned reg) 35{ 36 u32 val = readl(socket->base + reg); 37 DEBUG("%p %04x %08x\n", socket, reg, val); 38 return val; 39} 40 41static inline void cb_writel(pci_socket_t *socket, unsigned reg, u32 val) 42{ 43 DEBUG("%p %04x %08x\n", socket, reg, val); 44 writel(val, socket->base + reg); 45} 46 47static inline u8 config_readb(pci_socket_t *socket, unsigned offset) 48{ 49 u8 val; 50 pci_read_config_byte(socket->dev, offset, &val); 51 DEBUG("%p %04x %02x\n", socket, offset, val); 52 return val; 53} 54 55static inline u16 config_readw(pci_socket_t *socket, unsigned offset) 56{ 57 u16 val; 58 pci_read_config_word(socket->dev, offset, &val); 59 DEBUG("%p %04x %04x\n", socket, offset, val); 60 return val; 61} 62 63static inline u32 config_readl(pci_socket_t *socket, unsigned offset) 64{ 65 u32 val; 66 pci_read_config_dword(socket->dev, offset, &val); 67 DEBUG("%p %04x %08x\n", socket, offset, val); 68 return val; 69} 70 71static inline void config_writeb(pci_socket_t *socket, unsigned offset, u8 val) 72{ 73 DEBUG("%p %04x %02x\n", socket, offset, val); 74 pci_write_config_byte(socket->dev, offset, val); 75} 76 77static inline void config_writew(pci_socket_t *socket, unsigned offset, u16 val) 78{ 79 DEBUG("%p %04x %04x\n", socket, offset, val); 80 pci_write_config_word(socket->dev, offset, val); 81} 82 83static inline void config_writel(pci_socket_t *socket, unsigned offset, u32 val) 84{ 85 DEBUG("%p %04x %08x\n", socket, offset, val); 86 pci_write_config_dword(socket->dev, offset, val); 87} 88 89static inline u8 exca_readb(pci_socket_t *socket, unsigned reg) 90{ 91 u8 val = readb(socket->base + 0x800 + reg); 92 DEBUG("%p %04x %02x\n", socket, reg, val); 93 return val; 94} 95 96static inline u8 exca_readw(pci_socket_t *socket, unsigned reg) 97{ 98 u16 val; 99 val = readb(socket->base + 0x800 + reg); 100 val |= readb(socket->base + 0x800 + reg + 1) << 8; 101 DEBUG("%p %04x %04x\n", socket, reg, val); 102 return val; 103} 104 105static inline void exca_writeb(pci_socket_t *socket, unsigned reg, u8 val) 106{ 107 DEBUG("%p %04x %02x\n", socket, reg, val); 108 writeb(val, socket->base + 0x800 + reg); 109} 110 111static void exca_writew(pci_socket_t *socket, unsigned reg, u16 val) 112{ 113 DEBUG("%p %04x %04x\n", socket, reg, val); 114 writeb(val, socket->base + 0x800 + reg); 115 writeb(val >> 8, socket->base + 0x800 + reg + 1); 116} 117 118/* 119 * Ugh, mixed-mode cardbus and 16-bit pccard state: things depend 120 * on what kind of card is inserted.. 121 */ 122static int yenta_get_status(pci_socket_t *socket, unsigned int *value) 123{ 124 unsigned int val; 125 u32 state = cb_readl(socket, CB_SOCKET_STATE); 126 127 val = (state & CB_3VCARD) ? SS_3VCARD : 0; 128 val |= (state & CB_XVCARD) ? SS_XVCARD : 0; 129 val |= (state & (CB_CDETECT1 | CB_CDETECT2 | CB_5VCARD | CB_3VCARD 130 | CB_XVCARD | CB_YVCARD)) ? 0 : SS_PENDING; 131 132 if (state & CB_CBCARD) { 133 val |= SS_CARDBUS; 134 val |= (state & CB_CARDSTS) ? SS_STSCHG : 0; 135 val |= (state & (CB_CDETECT1 | CB_CDETECT2)) ? 0 : SS_DETECT; 136 val |= (state & CB_PWRCYCLE) ? SS_POWERON | SS_READY : 0; 137 } else { 138 u8 status = exca_readb(socket, I365_STATUS); 139 val |= ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0; 140 if (exca_readb(socket, I365_INTCTL) & I365_PC_IOCARD) { 141 val |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG; 142 } else { 143 val |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD; 144 val |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN; 145 } 146 val |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0; 147 val |= (status & I365_CS_READY) ? SS_READY : 0; 148 val |= (status & I365_CS_POWERON) ? SS_POWERON : 0; 149 } 150 151 *value = val; 152 return 0; 153} 154 155static int yenta_Vcc_power(u32 control) 156{ 157 switch (control & CB_SC_VCC_MASK) { 158 case CB_SC_VCC_5V: return 50; 159 case CB_SC_VCC_3V: return 33; 160 default: return 0; 161 } 162} 163 164static int yenta_Vpp_power(u32 control) 165{ 166 switch (control & CB_SC_VPP_MASK) { 167 case CB_SC_VPP_12V: return 120; 168 case CB_SC_VPP_5V: return 50; 169 case CB_SC_VPP_3V: return 33; 170 default: return 0; 171 } 172} 173 174static int yenta_get_socket(pci_socket_t *socket, socket_state_t *state) 175{ 176 u8 reg; 177 u32 control; 178 179 control = cb_readl(socket, CB_SOCKET_CONTROL); 180 181 state->Vcc = yenta_Vcc_power(control); 182 state->Vpp = yenta_Vpp_power(control); 183 state->io_irq = socket->io_irq; 184 185 if (cb_readl(socket, CB_SOCKET_STATE) & CB_CBCARD) { 186 u16 bridge = config_readw(socket, CB_BRIDGE_CONTROL); 187 if (bridge & CB_BRIDGE_CRST) 188 state->flags |= SS_RESET; 189 return 0; 190 } 191 192 /* 16-bit card state.. */ 193 reg = exca_readb(socket, I365_POWER); 194 state->flags = (reg & I365_PWR_AUTO) ? SS_PWR_AUTO : 0; 195 state->flags |= (reg & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0; 196 197 reg = exca_readb(socket, I365_INTCTL); 198 state->flags |= (reg & I365_PC_RESET) ? 0 : SS_RESET; 199 state->flags |= (reg & I365_PC_IOCARD) ? SS_IOCARD : 0; 200 201 reg = exca_readb(socket, I365_CSCINT); 202 state->csc_mask = (reg & I365_CSC_DETECT) ? SS_DETECT : 0; 203 if (state->flags & SS_IOCARD) { 204 state->csc_mask |= (reg & I365_CSC_STSCHG) ? SS_STSCHG : 0; 205 } else { 206 state->csc_mask |= (reg & I365_CSC_BVD1) ? SS_BATDEAD : 0; 207 state->csc_mask |= (reg & I365_CSC_BVD2) ? SS_BATWARN : 0; 208 state->csc_mask |= (reg & I365_CSC_READY) ? SS_READY : 0; 209 } 210 211 return 0; 212} 213 214static void yenta_set_power(pci_socket_t *socket, socket_state_t *state) 215{ 216 u32 reg = 0; /* CB_SC_STPCLK? */ 217 switch (state->Vcc) { 218 case 33: reg = CB_SC_VCC_3V; break; 219 case 50: reg = CB_SC_VCC_5V; break; 220 default: reg = 0; break; 221 } 222 switch (state->Vpp) { 223 case 33: reg |= CB_SC_VPP_3V; break; 224 case 50: reg |= CB_SC_VPP_5V; break; 225 case 120: reg |= CB_SC_VPP_12V; break; 226 } 227 if (reg != cb_readl(socket, CB_SOCKET_CONTROL)) 228 cb_writel(socket, CB_SOCKET_CONTROL, reg); 229} 230 231static int yenta_set_socket(pci_socket_t *socket, socket_state_t *state) 232{ 233 u16 bridge; 234 235 if (state->flags & SS_DEBOUNCED) { 236 /* The insertion debounce period has ended. Clear any pending insertion events */ 237 socket->events &= ~SS_DETECT; 238 state->flags &= ~SS_DEBOUNCED; /* SS_DEBOUNCED is oneshot */ 239 } 240 yenta_set_power(socket, state); 241 socket->io_irq = state->io_irq; 242 bridge = config_readw(socket, CB_BRIDGE_CONTROL) & ~(CB_BRIDGE_CRST | CB_BRIDGE_INTR); 243 if (cb_readl(socket, CB_SOCKET_STATE) & CB_CBCARD) { 244 u8 intr; 245 bridge |= (state->flags & SS_RESET) ? CB_BRIDGE_CRST : 0; 246 247 /* ISA interrupt control? */ 248 intr = exca_readb(socket, I365_INTCTL); 249 intr = (intr & ~0xf); 250 if (!socket->cb_irq) { 251 intr |= state->io_irq; 252 bridge |= CB_BRIDGE_INTR; 253 } 254 exca_writeb(socket, I365_INTCTL, intr); 255 } else { 256 u8 reg; 257 258 reg = exca_readb(socket, I365_INTCTL) & (I365_RING_ENA | I365_INTR_ENA); 259 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET; 260 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0; 261 if (state->io_irq != socket->cb_irq) { 262 reg |= state->io_irq; 263 bridge |= CB_BRIDGE_INTR; 264 } 265 exca_writeb(socket, I365_INTCTL, reg); 266 267 reg = exca_readb(socket, I365_POWER) & (I365_VCC_MASK|I365_VPP1_MASK); 268 reg |= I365_PWR_NORESET; 269 if (state->flags & SS_PWR_AUTO) reg |= I365_PWR_AUTO; 270 if (state->flags & SS_OUTPUT_ENA) reg |= I365_PWR_OUT; 271 if (exca_readb(socket, I365_POWER) != reg) 272 exca_writeb(socket, I365_POWER, reg); 273 274 /* CSC interrupt: no ISA irq for CSC */ 275 reg = I365_CSC_DETECT; 276 if (state->flags & SS_IOCARD) { 277 if (state->csc_mask & SS_STSCHG) reg |= I365_CSC_STSCHG; 278 } else { 279 if (state->csc_mask & SS_BATDEAD) reg |= I365_CSC_BVD1; 280 if (state->csc_mask & SS_BATWARN) reg |= I365_CSC_BVD2; 281 if (state->csc_mask & SS_READY) reg |= I365_CSC_READY; 282 } 283 exca_writeb(socket, I365_CSCINT, reg); 284 exca_readb(socket, I365_CSC); 285 286 if(socket->zoom_video) 287 socket->zoom_video(socket, state->flags & SS_ZVCARD); 288 } 289 config_writew(socket, CB_BRIDGE_CONTROL, bridge); 290 /* Socket event mask: get card insert/remove events.. */ 291 cb_writel(socket, CB_SOCKET_EVENT, -1); 292 cb_writel(socket, CB_SOCKET_MASK, CB_CDMASK); 293 return 0; 294} 295 296static int yenta_get_io_map(pci_socket_t *socket, struct pccard_io_map *io) 297{ 298 int map; 299 unsigned char ioctl, addr; 300 301 map = io->map; 302 if (map > 1) 303 return -EINVAL; 304 305 io->start = exca_readw(socket, I365_IO(map)+I365_W_START); 306 io->stop = exca_readw(socket, I365_IO(map)+I365_W_STOP); 307 308 ioctl = exca_readb(socket, I365_IOCTL); 309 addr = exca_readb(socket, I365_ADDRWIN); 310 io->speed = to_ns(ioctl & I365_IOCTL_WAIT(map)) ? 1 : 0; 311 io->flags = (addr & I365_ENA_IO(map)) ? MAP_ACTIVE : 0; 312 io->flags |= (ioctl & I365_IOCTL_0WS(map)) ? MAP_0WS : 0; 313 io->flags |= (ioctl & I365_IOCTL_16BIT(map)) ? MAP_16BIT : 0; 314 io->flags |= (ioctl & I365_IOCTL_IOCS16(map)) ? MAP_AUTOSZ : 0; 315 316 return 0; 317} 318 319static int yenta_set_io_map(pci_socket_t *socket, struct pccard_io_map *io) 320{ 321 int map; 322 unsigned char ioctl, addr, enable; 323 324 map = io->map; 325 326 if (map > 1) 327 return -EINVAL; 328 329 enable = I365_ENA_IO(map); 330 addr = exca_readb(socket, I365_ADDRWIN); 331 332 /* Disable the window before changing it.. */ 333 if (addr & enable) { 334 addr &= ~enable; 335 exca_writeb(socket, I365_ADDRWIN, addr); 336 } 337 338 exca_writew(socket, I365_IO(map)+I365_W_START, io->start); 339 exca_writew(socket, I365_IO(map)+I365_W_STOP, io->stop); 340 341 ioctl = exca_readb(socket, I365_IOCTL) & ~I365_IOCTL_MASK(map); 342 if (io->flags & MAP_0WS) ioctl |= I365_IOCTL_0WS(map); 343 if (io->flags & MAP_16BIT) ioctl |= I365_IOCTL_16BIT(map); 344 if (io->flags & MAP_AUTOSZ) ioctl |= I365_IOCTL_IOCS16(map); 345 exca_writeb(socket, I365_IOCTL, ioctl); 346 347 if (io->flags & MAP_ACTIVE) 348 exca_writeb(socket, I365_ADDRWIN, addr | enable); 349 return 0; 350} 351 352static int yenta_get_mem_map(pci_socket_t *socket, struct pccard_mem_map *mem) 353{ 354 int map; 355 unsigned char addr; 356 unsigned int start, stop, page, offset; 357 358 map = mem->map; 359 if (map > 4) 360 return -EINVAL; 361 362 addr = exca_readb(socket, I365_ADDRWIN); 363 mem->flags = (addr & I365_ENA_MEM(map)) ? MAP_ACTIVE : 0; 364 365 start = exca_readw(socket, I365_MEM(map) + I365_W_START); 366 mem->flags |= (start & I365_MEM_16BIT) ? MAP_16BIT : 0; 367 mem->flags |= (start & I365_MEM_0WS) ? MAP_0WS : 0; 368 start = (start & 0x0fff) << 12; 369 370 stop = exca_readw(socket, I365_MEM(map) + I365_W_STOP); 371 mem->speed = to_ns(stop >> 14); 372 stop = ((stop & 0x0fff) << 12) + 0x0fff; 373 374 offset = exca_readw(socket, I365_MEM(map) + I365_W_OFF); 375 mem->flags |= (offset & I365_MEM_WRPROT) ? MAP_WRPROT : 0; 376 mem->flags |= (offset & I365_MEM_REG) ? MAP_ATTRIB : 0; 377 offset = ((offset & 0x3fff) << 12) + start; 378 mem->card_start = offset & 0x3ffffff; 379 380 page = exca_readb(socket, CB_MEM_PAGE(map)) << 24; 381 mem->sys_start = start + page; 382 mem->sys_stop = start + page; 383 384 return 0; 385} 386 387static int yenta_set_mem_map(pci_socket_t *socket, struct pccard_mem_map *mem) 388{ 389 int map; 390 unsigned char addr, enable; 391 unsigned int start, stop, card_start; 392 unsigned short word; 393 394 map = mem->map; 395 start = mem->sys_start; 396 stop = mem->sys_stop; 397 card_start = mem->card_start; 398 399 if (map > 4 || start > stop || ((start ^ stop) >> 24) || 400 (card_start >> 26) || mem->speed > 1000) 401 return -EINVAL; 402 403 enable = I365_ENA_MEM(map); 404 addr = exca_readb(socket, I365_ADDRWIN); 405 if (addr & enable) { 406 addr &= ~enable; 407 exca_writeb(socket, I365_ADDRWIN, addr); 408 } 409 410 exca_writeb(socket, CB_MEM_PAGE(map), start >> 24); 411 412 word = (start >> 12) & 0x0fff; 413 if (mem->flags & MAP_16BIT) 414 word |= I365_MEM_16BIT; 415 if (mem->flags & MAP_0WS) 416 word |= I365_MEM_0WS; 417 exca_writew(socket, I365_MEM(map) + I365_W_START, word); 418 419 word = (stop >> 12) & 0x0fff; 420 switch (to_cycles(mem->speed)) { 421 case 0: break; 422 case 1: word |= I365_MEM_WS0; break; 423 case 2: word |= I365_MEM_WS1; break; 424 default: word |= I365_MEM_WS1 | I365_MEM_WS0; break; 425 } 426 exca_writew(socket, I365_MEM(map) + I365_W_STOP, word); 427 428 word = ((card_start - start) >> 12) & 0x3fff; 429 if (mem->flags & MAP_WRPROT) 430 word |= I365_MEM_WRPROT; 431 if (mem->flags & MAP_ATTRIB) 432 word |= I365_MEM_REG; 433 exca_writew(socket, I365_MEM(map) + I365_W_OFF, word); 434 435 if (mem->flags & MAP_ACTIVE) 436 exca_writeb(socket, I365_ADDRWIN, addr | enable); 437 return 0; 438} 439 440static void yenta_proc_setup(pci_socket_t *socket, struct proc_dir_entry *base) 441{ 442 /* Not done yet */ 443} 444 445static unsigned int yenta_events(pci_socket_t *socket) 446{ 447 u8 csc; 448 u32 cb_event; 449 unsigned int events; 450 451 /* Clear interrupt status for the event */ 452 cb_event = cb_readl(socket, CB_SOCKET_EVENT); 453 cb_writel(socket, CB_SOCKET_EVENT, cb_event); 454 455 csc = exca_readb(socket, I365_CSC); 456 457 events = (cb_event & (CB_CD1EVENT | CB_CD2EVENT)) ? SS_DETECT : 0 ; 458 events |= (csc & I365_CSC_DETECT) ? SS_DETECT : 0; 459 if (exca_readb(socket, I365_INTCTL) & I365_PC_IOCARD) { 460 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; 461 } else { 462 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0; 463 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0; 464 events |= (csc & I365_CSC_READY) ? SS_READY : 0; 465 } 466 return events; 467} 468 469 470static void yenta_bh(void *data) 471{ 472 pci_socket_t *socket = data; 473 unsigned int events; 474 475 spin_lock_irq(&socket->event_lock); 476 events = socket->events; 477 socket->events = 0; 478 spin_unlock_irq(&socket->event_lock); 479 if (socket->handler) 480 socket->handler(socket->info, events); 481} 482 483static void yenta_interrupt(int irq, void *dev_id, struct pt_regs *regs) 484{ 485 unsigned int events; 486 pci_socket_t *socket = (pci_socket_t *) dev_id; 487 488 events = yenta_events(socket); 489 if (events) { 490 spin_lock(&socket->event_lock); 491 socket->events |= events; 492 spin_unlock(&socket->event_lock); 493 schedule_task(&socket->tq_task); 494 } 495} 496 497static void yenta_interrupt_wrapper(unsigned long data) 498{ 499 pci_socket_t *socket = (pci_socket_t *) data; 500 501 yenta_interrupt(0, (void *)socket, NULL); 502 socket->poll_timer.expires = jiffies + HZ; 503 add_timer(&socket->poll_timer); 504} 505 506/* 507 * Only probe "regular" interrupts, don't 508 * touch dangerous spots like the mouse irq, 509 * because there are mice that apparently 510 * get really confused if they get fondled 511 * too intimately. 512 * 513 * Default to 11, 10, 9, 7, 6, 5, 4, 3. 514 */ 515static u32 isa_interrupts = 0x0ef8; 516 517static unsigned int yenta_probe_irq(pci_socket_t *socket, u32 isa_irq_mask) 518{ 519 int i; 520 unsigned long val; 521 u16 bridge_ctrl; 522 u32 mask; 523 524 /* Set up ISA irq routing to probe the ISA irqs.. */ 525 bridge_ctrl = config_readw(socket, CB_BRIDGE_CONTROL); 526 if (!(bridge_ctrl & CB_BRIDGE_INTR)) { 527 bridge_ctrl |= CB_BRIDGE_INTR; 528 config_writew(socket, CB_BRIDGE_CONTROL, bridge_ctrl); 529 } 530 531 /* 532 * Probe for usable interrupts using the force 533 * register to generate bogus card status events. 534 */ 535 cb_writel(socket, CB_SOCKET_EVENT, -1); 536 cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK); 537 exca_writeb(socket, I365_CSCINT, 0); 538 val = probe_irq_on() & isa_irq_mask; 539 for (i = 1; i < 16; i++) { 540 if (!((val >> i) & 1)) 541 continue; 542 exca_writeb(socket, I365_CSCINT, I365_CSC_STSCHG | (i << 4)); 543 cb_writel(socket, CB_SOCKET_FORCE, CB_FCARDSTS); 544 udelay(100); 545 cb_writel(socket, CB_SOCKET_EVENT, -1); 546 } 547 cb_writel(socket, CB_SOCKET_MASK, 0); 548 exca_writeb(socket, I365_CSCINT, 0); 549 550 mask = probe_irq_mask(val) & 0xffff; 551 552 bridge_ctrl &= ~CB_BRIDGE_INTR; 553 config_writew(socket, CB_BRIDGE_CONTROL, bridge_ctrl); 554 555 return mask; 556} 557 558/* 559 * Set static data that doesn't need re-initializing.. 560 */ 561static void yenta_get_socket_capabilities(pci_socket_t *socket, u32 isa_irq_mask) 562{ 563 socket->cap.features |= SS_CAP_PAGE_REGS | SS_CAP_PCCARD | SS_CAP_CARDBUS; 564 socket->cap.map_size = 0x1000; 565 socket->cap.pci_irq = socket->cb_irq; 566 socket->cap.irq_mask = yenta_probe_irq(socket, isa_irq_mask); 567 socket->cap.cb_dev = socket->dev; 568 socket->cap.bus = NULL; 569 570 printk("Yenta IRQ list %04x, PCI irq%d\n", socket->cap.irq_mask, socket->cb_irq); 571} 572 573extern void cardbus_register(pci_socket_t *socket); 574 575/* 576 * 'Bottom half' for the yenta_open routine. Allocate the interrupt line 577 * and register the socket with the upper layers. 578 */ 579static void yenta_open_bh(void * data) 580{ 581 pci_socket_t * socket = (pci_socket_t *) data; 582 583 /* It's OK to overwrite this now */ 584 socket->tq_task.routine = yenta_bh; 585 586 if (!socket->cb_irq || request_irq(socket->cb_irq, yenta_interrupt, SA_SHIRQ, socket->dev->name, socket)) { 587 /* No IRQ or request_irq failed. Poll */ 588 socket->cb_irq = 0; /* But zero is a valid IRQ number. */ 589 socket->poll_timer.function = yenta_interrupt_wrapper; 590 socket->poll_timer.data = (unsigned long)socket; 591 socket->poll_timer.expires = jiffies + HZ; 592 add_timer(&socket->poll_timer); 593 } 594 595 /* Figure out what the dang thing can do for the PCMCIA layer... */ 596 yenta_get_socket_capabilities(socket, isa_interrupts); 597 printk("Socket status: %08x\n", cb_readl(socket, CB_SOCKET_STATE)); 598 599 /* Register it with the pcmcia layer.. */ 600 cardbus_register(socket); 601 602 MOD_DEC_USE_COUNT; 603} 604 605static void yenta_clear_maps(pci_socket_t *socket) 606{ 607 int i; 608 pccard_io_map io = { 0, 0, 0, 0, 1 }; 609 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 }; 610 611 mem.sys_stop = 0x0fff; 612 yenta_set_socket(socket, &dead_socket); 613 for (i = 0; i < 2; i++) { 614 io.map = i; 615 yenta_set_io_map(socket, &io); 616 } 617 for (i = 0; i < 5; i++) { 618 mem.map = i; 619 yenta_set_mem_map(socket, &mem); 620 } 621} 622 623/* 624 * Initialize the standard cardbus registers 625 */ 626static void yenta_config_init(pci_socket_t *socket) 627{ 628 u16 bridge; 629 struct pci_dev *dev = socket->dev; 630 631 pci_set_power_state(socket->dev, 0); 632 633 config_writel(socket, CB_LEGACY_MODE_BASE, 0); 634 config_writel(socket, PCI_BASE_ADDRESS_0, dev->resource[0].start); 635 config_writew(socket, PCI_COMMAND, 636 PCI_COMMAND_IO | 637 PCI_COMMAND_MEMORY | 638 PCI_COMMAND_MASTER | 639 PCI_COMMAND_WAIT); 640 641 config_writeb(socket, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES / 4); 642 config_writeb(socket, PCI_LATENCY_TIMER, 168); 643 config_writel(socket, PCI_PRIMARY_BUS, 644 (176 << 24) | /* sec. latency timer */ 645 (dev->subordinate->subordinate << 16) | /* subordinate bus */ 646 (dev->subordinate->secondary << 8) | /* secondary bus */ 647 dev->subordinate->primary); /* primary bus */ 648 649 /* 650 * Set up the bridging state: 651 * - enable write posting. 652 * - memory window 0 prefetchable, window 1 non-prefetchable 653 * - PCI interrupts enabled if a PCI interrupt exists.. 654 */ 655 bridge = config_readw(socket, CB_BRIDGE_CONTROL); 656 bridge &= ~(CB_BRIDGE_CRST | CB_BRIDGE_PREFETCH1 | CB_BRIDGE_INTR | CB_BRIDGE_ISAEN | CB_BRIDGE_VGAEN); 657 bridge |= CB_BRIDGE_PREFETCH0 | CB_BRIDGE_POSTEN; 658 if (!socket->cb_irq) 659 bridge |= CB_BRIDGE_INTR; 660 config_writew(socket, CB_BRIDGE_CONTROL, bridge); 661 662 exca_writeb(socket, I365_GBLCTL, 0x00); 663 exca_writeb(socket, I365_GENCTL, 0x00); 664 665 /* Redo card voltage interrogation */ 666 cb_writel(socket, CB_SOCKET_FORCE, CB_CVSTEST); 667} 668 669/* Called at resume and initialization events */ 670static int yenta_init(pci_socket_t *socket) 671{ 672 yenta_config_init(socket); 673 yenta_clear_maps(socket); 674 675 /* Re-enable interrupts */ 676 cb_writel(socket, CB_SOCKET_MASK, CB_CDMASK); 677 return 0; 678} 679 680static int yenta_suspend(pci_socket_t *socket) 681{ 682 yenta_set_socket(socket, &dead_socket); 683 684 /* Disable interrupts */ 685 cb_writel(socket, CB_SOCKET_MASK, 0x0); 686 687 /* 688 * This does not work currently. The controller 689 * loses too much information during D3 to come up 690 * cleanly. We should probably fix yenta_init() 691 * to update all the critical registers, notably 692 * the IO and MEM bridging region data.. That is 693 * something that pci_set_power_state() should 694 * probably know about bridges anyway. 695 * 696 pci_set_power_state(socket->dev, 3); 697 */ 698 699 return 0; 700} 701 702static void yenta_allocate_res(pci_socket_t *socket, int nr, unsigned type) 703{ 704 struct pci_bus *bus; 705 struct resource *root, *res; 706 u32 start, end; 707 u32 align, size, min, max; 708 unsigned offset; 709 unsigned mask; 710 711 /* The granularity of the memory limit is 4kB, on IO it's 4 bytes */ 712 mask = ~0xfff; 713 if (type & IORESOURCE_IO) 714 mask = ~3; 715 716 offset = 0x1c + 8*nr; 717 bus = socket->dev->subordinate; 718 res = socket->dev->resource + PCI_BRIDGE_RESOURCES + nr; 719 res->name = bus->name; 720 res->flags = type; 721 res->start = 0; 722 res->end = 0; 723 root = pci_find_parent_resource(socket->dev, res); 724 725 if (!root) 726 return; 727 728 start = config_readl(socket, offset) & mask; 729 end = config_readl(socket, offset+4) | ~mask; 730 if (start && end > start) { 731 res->start = start; 732 res->end = end; 733 request_resource(root, res); 734 return; 735 } 736 737 align = size = 4*1024*1024; 738 min = PCIBIOS_MIN_MEM; max = ~0U; 739 if (type & IORESOURCE_IO) { 740 align = 1024; 741 size = 256; 742 min = 0x4000; 743 max = 0xffff; 744 } 745 746 if (allocate_resource(root, res, size, min, max, align, NULL, NULL) < 0) 747 return; 748 749 config_writel(socket, offset, res->start); 750 config_writel(socket, offset+4, res->end); 751} 752 753/* 754 * Allocate the bridge mappings for the device.. 755 */ 756static void yenta_allocate_resources(pci_socket_t *socket) 757{ 758 yenta_allocate_res(socket, 0, IORESOURCE_MEM|IORESOURCE_PREFETCH); 759 yenta_allocate_res(socket, 1, IORESOURCE_MEM); 760 yenta_allocate_res(socket, 2, IORESOURCE_IO); 761 yenta_allocate_res(socket, 3, IORESOURCE_IO); /* PCI isn't clever enough to use this one yet */ 762} 763 764/* 765 * Close it down - release our resources and go home.. 766 */ 767static void yenta_close(pci_socket_t *sock) 768{ 769 /* Disable all events so we don't die in an IRQ storm */ 770 cb_writel(sock, CB_SOCKET_MASK, 0x0); 771 exca_writeb(sock, I365_CSCINT, 0); 772 773 if (sock->cb_irq) 774 free_irq(sock->cb_irq, sock); 775 else 776 del_timer_sync(&sock->poll_timer); 777 778 if (sock->base) 779 iounmap(sock->base); 780} 781 782#include "ti113x.h" 783#include "ricoh.h" 784 785/* 786 * Different cardbus controllers have slightly different 787 * initialization sequences etc details. List them here.. 788 */ 789#define PD(x,y) PCI_VENDOR_ID_##x, PCI_DEVICE_ID_##x##_##y 790static struct cardbus_override_struct { 791 unsigned short vendor; 792 unsigned short device; 793 struct pci_socket_ops *op; 794} cardbus_override[] = { 795 { PD(TI,1130), &ti113x_ops }, 796 { PD(TI,1031), &ti_ops }, 797 { PD(TI,1131), &ti113x_ops }, 798 { PD(TI,1250), &ti1250_ops }, 799 { PD(TI,1220), &ti_ops }, 800 { PD(TI,1221), &ti_ops }, 801 { PD(TI,1210), &ti_ops }, 802 { PD(TI,1450), &ti_ops }, 803 { PD(TI,1225), &ti_ops }, 804 { PD(TI,1251A), &ti_ops }, 805 { PD(TI,1211), &ti_ops }, 806 { PD(TI,1251B), &ti_ops }, 807 { PD(TI,1410), &ti_ops }, 808 { PD(TI,1420), &ti_ops }, 809 { PD(TI,4410), &ti_ops }, 810 { PD(TI,4451), &ti_ops }, 811 812 { PD(RICOH,RL5C465), &ricoh_ops }, 813 { PD(RICOH,RL5C466), &ricoh_ops }, 814 { PD(RICOH,RL5C475), &ricoh_ops }, 815 { PD(RICOH,RL5C476), &ricoh_ops }, 816 { PD(RICOH,RL5C478), &ricoh_ops } 817}; 818 819#define NR_OVERRIDES (sizeof(cardbus_override)/sizeof(struct cardbus_override_struct)) 820 821/* 822 * Initialize a cardbus controller. Make sure we have a usable 823 * interrupt, and that we can map the cardbus area. Fill in the 824 * socket information structure.. 825 */ 826static int yenta_open(pci_socket_t *socket) 827{ 828 int i; 829 struct pci_dev *dev = socket->dev; 830 831 /* 832 * Do some basic sanity checking.. 833 */ 834 if (pci_enable_device(dev)) 835 return -1; 836 if (!pci_resource_start(dev, 0)) { 837 printk("No cardbus resource!\n"); 838 return -1; 839 } 840 841 /* 842 * Ok, start setup.. Map the cardbus registers, 843 * and request the IRQ. 844 */ 845 socket->base = ioremap(pci_resource_start(dev, 0), 0x1000); 846 if (!socket->base) 847 return -1; 848 849 yenta_config_init(socket); 850 851 /* Disable all events */ 852 cb_writel(socket, CB_SOCKET_MASK, 0x0); 853 854 /* Set up the bridge regions.. */ 855 yenta_allocate_resources(socket); 856 857 socket->cb_irq = dev->irq; 858 859 /* Do we have special options for the device? */ 860 for (i = 0; i < NR_OVERRIDES; i++) { 861 struct cardbus_override_struct *d = cardbus_override+i; 862 if (dev->vendor == d->vendor && dev->device == d->device) { 863 socket->op = d->op; 864 if (d->op->open) { 865 int retval = d->op->open(socket); 866 if (retval < 0) 867 return retval; 868 } 869 } 870 } 871 872 /* Get the PCMCIA kernel thread to complete the 873 initialisation later. We can't do this here, 874 because, er, because Linus says so :) 875 */ 876 socket->tq_task.routine = yenta_open_bh; 877 socket->tq_task.data = socket; 878 879 MOD_INC_USE_COUNT; 880 schedule_task(&socket->tq_task); 881 882 return 0; 883} 884 885/* 886 * Standard plain cardbus - no frills, no extensions 887 */ 888struct pci_socket_ops yenta_operations = { 889 yenta_open, 890 yenta_close, 891 yenta_init, 892 yenta_suspend, 893 yenta_get_status, 894 yenta_get_socket, 895 yenta_set_socket, 896 yenta_get_io_map, 897 yenta_set_io_map, 898 yenta_get_mem_map, 899 yenta_set_mem_map, 900 yenta_proc_setup 901}; 902EXPORT_SYMBOL(yenta_operations); 903MODULE_LICENSE("GPL"); 904