1/* 2 * SDL Inc. RISCom/N2 synchronous serial card driver for Linux 3 * 4 * Copyright (C) 1998-2000 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * For information see http://hq.pm.waw.pl/hdlc/ 12 * 13 * Note: integrated CSU/DSU/DDS are not supported by this driver 14 * 15 * Sources of information: 16 * Hitachi HD64570 SCA User's Manual 17 * SDL Inc. PPP/HDLC/CISCO driver 18 */ 19 20#include <linux/module.h> 21#include <linux/kernel.h> 22#include <linux/slab.h> 23#include <linux/sched.h> 24#include <linux/types.h> 25#include <linux/fcntl.h> 26#include <linux/in.h> 27#include <linux/string.h> 28#include <linux/errno.h> 29#include <linux/init.h> 30#include <linux/ioport.h> 31#include <linux/netdevice.h> 32#include <linux/hdlc.h> 33#include <asm/io.h> 34#include "hd64570.h" 35 36#define DEBUG_RINGS 37/* #define DEBUG_PKT */ 38 39static const char* version = "SDL RISCom/N2 driver revision: 1.02 for Linux 2.4"; 40static const char* devname = "RISCom/N2"; 41 42#define USE_WINDOWSIZE 16384 43#define USE_BUS16BITS 1 44#define CLOCK_BASE 9830400 /* 9.8304 MHz */ 45 46#define N2_IOPORTS 0x10 47 48static char *hw = NULL; 49 50/* RISCom/N2 Board Registers */ 51 52/* PC Control Register */ 53#define N2_PCR 0 54#define PCR_RUNSCA 1 /* Run 64570 */ 55#define PCR_VPM 2 /* Enable VPM - needed if using RAM above 1 MB */ 56#define PCR_ENWIN 4 /* Open window */ 57#define PCR_BUS16 8 /* 16-bit bus */ 58 59 60/* Memory Base Address Register */ 61#define N2_BAR 2 62 63 64/* Page Scan Register */ 65#define N2_PSR 4 66#define WIN16K 0x00 67#define WIN32K 0x20 68#define WIN64K 0x40 69#define PSR_WINBITS 0x60 70#define PSR_DMAEN 0x80 71#define PSR_PAGEBITS 0x0F 72 73 74/* Modem Control Reg */ 75#define N2_MCR 6 76#define CLOCK_OUT_PORT1 0x80 77#define CLOCK_OUT_PORT0 0x40 78#define TX422_PORT1 0x20 79#define TX422_PORT0 0x10 80#define DSR_PORT1 0x08 81#define DSR_PORT0 0x04 82#define DTR_PORT1 0x02 83#define DTR_PORT0 0x01 84 85 86typedef struct port_s { 87 hdlc_device hdlc; /* HDLC device struct - must be first */ 88 struct card_s *card; 89 spinlock_t lock; /* TX lock */ 90 int clkmode; /* clock mode */ 91 int clkrate; /* clock rate */ 92 int line; /* loopback only */ 93 u8 rxs, txs, tmc; /* SCA registers */ 94 u8 valid; /* port enabled */ 95 u8 phy_node; /* physical port # - 0 or 1 */ 96 u8 log_node; /* logical port # */ 97 u8 rxin; /* rx ring buffer 'in' pointer */ 98 u8 txin; /* tx ring buffer 'in' and 'last' pointers */ 99 u8 txlast; 100 u8 rxpart; /* partial frame received, next frame invalid*/ 101}port_t; 102 103 104 105typedef struct card_s { 106 u8 *winbase; /* ISA window base address */ 107 u32 phy_winbase; /* ISA physical base address */ 108 u32 ram_size; /* number of bytes */ 109 u16 io; /* IO Base address */ 110 u16 buff_offset; /* offset of first buffer of first channel */ 111 u8 irq; /* IRQ (3-15) */ 112 u8 ring_buffers; /* number of buffers in a ring */ 113 114 port_t ports[2]; 115 struct card_s *next_card; 116}card_t; 117 118 119 120#define sca_reg(reg, card) (0x8000 | (card)->io | \ 121 ((reg) & 0x0F) | (((reg) & 0xF0) << 6)) 122#define sca_in(reg, card) inb(sca_reg(reg, card)) 123#define sca_out(value, reg, card) outb(value, sca_reg(reg, card)) 124#define sca_inw(reg, card) inw(sca_reg(reg, card)) 125#define sca_outw(value, reg, card) outw(value, sca_reg(reg, card)) 126 127#define port_to_card(port) ((port)->card) 128#define log_node(port) ((port)->log_node) 129#define phy_node(port) ((port)->phy_node) 130#define winsize(card) (USE_WINDOWSIZE) 131#define winbase(card) ((card)->winbase) 132#define get_port(card, port) ((card)->ports[port].valid ? \ 133 &(card)->ports[port] : NULL) 134 135 136 137static __inline__ u8 sca_get_page(card_t *card) 138{ 139 return inb(card->io + N2_PSR) & PSR_PAGEBITS; 140} 141 142 143static __inline__ void openwin(card_t *card, u8 page) 144{ 145 u8 psr = inb(card->io + N2_PSR); 146 outb((psr & ~PSR_PAGEBITS) | page, card->io + N2_PSR); 147} 148 149 150static __inline__ void close_windows(card_t *card) 151{ 152 outb(inb(card->io + N2_PCR) & ~PCR_ENWIN, card->io + N2_PCR); 153} 154 155 156#include "hd6457x.c" 157 158 159 160static int n2_set_clock(port_t *port, int value) 161{ 162 card_t *card = port->card; 163 int io = card->io; 164 u8 mcr = inb(io + N2_MCR); 165 u8 msci = get_msci(port); 166 u8 rxs = port->rxs & CLK_BRG_MASK; 167 u8 txs = port->txs & CLK_BRG_MASK; 168 169 switch(value) { 170 case CLOCK_EXT: 171 mcr &= port->phy_node ? ~CLOCK_OUT_PORT1 : ~CLOCK_OUT_PORT0; 172 rxs |= CLK_LINE_RX; /* RXC input */ 173 txs |= CLK_LINE_TX; /* TXC input */ 174 break; 175 176 case CLOCK_INT: 177 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; 178 rxs |= CLK_BRG_RX; /* BRG output */ 179 txs |= CLK_RXCLK_TX; /* RX clock */ 180 break; 181 182 case CLOCK_TXINT: 183 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; 184 rxs |= CLK_LINE_RX; /* RXC input */ 185 txs |= CLK_BRG_TX; /* BRG output */ 186 break; 187 188 case CLOCK_TXFROMRX: 189 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; 190 rxs |= CLK_LINE_RX; /* RXC input */ 191 txs |= CLK_RXCLK_TX; /* RX clock */ 192 break; 193 194 default: 195 return -EINVAL; 196 } 197 198 outb(mcr, io + N2_MCR); 199 port->rxs = rxs; 200 port->txs = txs; 201 sca_out(rxs, msci + RXS, card); 202 sca_out(txs, msci + TXS, card); 203 port->clkmode = value; 204 return 0; 205} 206 207 208 209static int n2_open(hdlc_device *hdlc) 210{ 211 port_t *port = hdlc_to_port(hdlc); 212 int io = port->card->io; 213 u8 mcr = inb(io + N2_MCR) | (port->phy_node ? TX422_PORT1 : TX422_PORT0); 214 215 MOD_INC_USE_COUNT; 216 mcr &= port->phy_node ? ~DTR_PORT1 : ~DTR_PORT0; /* set DTR ON */ 217 outb(mcr, io + N2_MCR); 218 219 outb(inb(io + N2_PCR) | PCR_ENWIN, io + N2_PCR); /* open window */ 220 outb(inb(io + N2_PSR) | PSR_DMAEN, io + N2_PSR); /* enable dma */ 221 sca_open(hdlc); 222 n2_set_clock(port, port->clkmode); 223 return 0; 224} 225 226 227 228static void n2_close(hdlc_device *hdlc) 229{ 230 port_t *port = hdlc_to_port(hdlc); 231 int io = port->card->io; 232 u8 mcr = inb(io+N2_MCR) | (port->phy_node ? TX422_PORT1 : TX422_PORT0); 233 234 sca_close(hdlc); 235 mcr |= port->phy_node ? DTR_PORT1 : DTR_PORT0; /* set DTR OFF */ 236 outb(mcr, io + N2_MCR); 237 MOD_DEC_USE_COUNT; 238} 239 240 241 242static int n2_ioctl(hdlc_device *hdlc, struct ifreq *ifr, int cmd) 243{ 244 int value = ifr->ifr_ifru.ifru_ivalue; 245 int result = 0; 246 port_t *port = hdlc_to_port(hdlc); 247 248 if(!capable(CAP_NET_ADMIN)) 249 return -EPERM; 250 251 switch(cmd) { 252 case HDLCSCLOCK: 253 result = n2_set_clock(port, value); 254 case HDLCGCLOCK: 255 value = port->clkmode; 256 break; 257 258 case HDLCSCLOCKRATE: 259 port->clkrate = value; 260 sca_set_clock(port); 261 case HDLCGCLOCKRATE: 262 value = port->clkrate; 263 break; 264 265 case HDLCSLINE: 266 result = sca_set_loopback(port, value); 267 case HDLCGLINE: 268 value = port->line; 269 break; 270 271#ifdef DEBUG_RINGS 272 case HDLCRUN: 273 sca_dump_rings(hdlc); 274 return 0; 275#endif /* DEBUG_RINGS */ 276 277 default: 278 return -EINVAL; 279 } 280 281 ifr->ifr_ifru.ifru_ivalue = value; 282 return result; 283} 284 285 286 287static u8 n2_count_page(card_t *card) 288{ 289 u8 page; 290 int i, bcount = USE_WINDOWSIZE, wcount = USE_WINDOWSIZE/2; 291 u16 *dp = (u16*)card->winbase; 292 u8 *bp = (u8*)card->winbase; 293 u8 psr = inb(card->io + N2_PSR) & PSR_WINBITS; 294 295 296 for (page = 0; page < 16; page++) { 297 outb(psr | page, card->io + N2_PSR); /* select a page */ 298 writeb(page, dp); 299 if (readb(dp) != page) 300 break; /* If can't read back, no good memory */ 301 302 outb(psr, card->io + N2_PSR); /* goto page 0 */ 303 if (readb(dp)) 304 break; /* If page 0 changed, then wrapped around */ 305 306 outb(psr | page, card->io + N2_PSR); /* select page again */ 307 308 /* first do byte tests */ 309 for (i = 0; i < bcount; i++) 310 writeb(i, bp + i); 311 for (i = 0; i < bcount; i++) 312 if (readb(bp + i) != (i & 0xff)) 313 return 0; 314 315 for (i = 0; i < bcount; i++) 316 writeb(~i, bp + i); 317 for (i = 0; i < bcount; i++) 318 if (readb(bp + i) != (~i & 0xff)) 319 return 0; 320 321 /* next do 16-bit tests */ 322 for (i = 0; i < wcount; i++) 323 writew(0x55AA, dp + i); 324 for (i = 0; i < wcount; i++) 325 if (readw(dp + i) != 0x55AA) 326 return 0; 327 328 for (i = 0; i < wcount; i++) 329 writew(0xAA55, dp + i); 330 for (i = 0; i < wcount; i++) 331 if (readw(dp + i) != 0xAA55) 332 return 0; 333 334 for (i = 0; i < wcount; i++) 335 writew(page, dp + i); 336 } 337 338 return page; 339} 340 341 342 343static void n2_destroy_card(card_t *card) 344{ 345 int cnt; 346 347 for (cnt = 0; cnt < 2; cnt++) 348 if (card->ports[cnt].card) 349 unregister_hdlc_device(&card->ports[cnt].hdlc); 350 351 if (card->irq) 352 free_irq(card->irq, card); 353 354 if (card->winbase) { 355 iounmap(card->winbase); 356 release_mem_region(card->phy_winbase, USE_WINDOWSIZE); 357 } 358 359 if (card->io) 360 release_region(card->io, N2_IOPORTS); 361 kfree(card); 362} 363 364 365 366static int n2_run(unsigned long io, unsigned long irq, unsigned long winbase, 367 long valid0, long valid1) 368{ 369 card_t *card; 370 u8 cnt, pcr; 371 372 if (io < 0x200 || io > 0x3FF || (io % N2_IOPORTS) != 0) { 373 printk(KERN_ERR "n2: invalid I/O port value\n"); 374 return -ENODEV; 375 } 376 377 if (irq < 3 || irq > 15 || irq == 6) { 378 printk(KERN_ERR "n2: invalid IRQ value\n"); 379 return -ENODEV; 380 } 381 382 if (winbase < 0xA0000 || winbase > 0xFFFFF || (winbase & 0xFFF) != 0) { 383 printk(KERN_ERR "n2: invalid RAM value\n"); 384 return -ENODEV; 385 } 386 387 card = kmalloc(sizeof(card_t), GFP_KERNEL); 388 if (card == NULL) { 389 printk(KERN_ERR "n2: unable to allocate memory\n"); 390 return -ENOBUFS; 391 } 392 memset(card, 0, sizeof(card_t)); 393 394 if (!request_region(io, N2_IOPORTS, devname)) { 395 printk(KERN_ERR "n2: I/O port region in use\n"); 396 n2_destroy_card(card); 397 return -EBUSY; 398 } 399 card->io = io; 400 401 if (request_irq(irq, &sca_intr, 0, devname, card)) { 402 printk(KERN_ERR "n2: could not allocate IRQ\n"); 403 n2_destroy_card(card); 404 return(-EBUSY); 405 } 406 card->irq = irq; 407 408 if (!request_mem_region(winbase, USE_WINDOWSIZE, devname)) { 409 printk(KERN_ERR "n2: could not request RAM window\n"); 410 n2_destroy_card(card); 411 return(-EBUSY); 412 } 413 card->phy_winbase = winbase; 414 card->winbase = ioremap(winbase, USE_WINDOWSIZE); 415 416 outb(0, io + N2_PCR); 417 outb(winbase >> 12, io + N2_BAR); 418 419 switch (USE_WINDOWSIZE) { 420 case 16384: 421 outb(WIN16K, io + N2_PSR); 422 break; 423 424 case 32768: 425 outb(WIN32K, io + N2_PSR); 426 break; 427 428 case 65536: 429 outb(WIN64K, io + N2_PSR); 430 break; 431 432 default: 433 printk(KERN_ERR "n2: invalid window size\n"); 434 n2_destroy_card(card); 435 return -ENODEV; 436 } 437 438 pcr = PCR_ENWIN | PCR_VPM | (USE_BUS16BITS ? PCR_BUS16 : 0); 439 outb(pcr, io + N2_PCR); 440 441 cnt = n2_count_page(card); 442 if (!cnt) { 443 printk(KERN_ERR "n2: memory test failed.\n"); 444 n2_destroy_card(card); 445 return -EIO; 446 } 447 448 card->ram_size = cnt * USE_WINDOWSIZE; 449 450 /* 4 rings required for 2 ports, 2 rings for one port */ 451 card->ring_buffers = card->ram_size / 452 ((valid0 + valid1) * 2 * (sizeof(pkt_desc) + HDLC_MAX_MRU)); 453 454 card->buff_offset = (valid0 + valid1) * 2 * (sizeof(pkt_desc)) 455 * card->ring_buffers; 456 457 printk(KERN_DEBUG "n2: RISCom/N2 %u KB RAM, IRQ%u, " 458 "using %u packets rings\n", card->ram_size / 1024, card->irq, 459 card->ring_buffers); 460 461 pcr |= PCR_RUNSCA; /* run SCA */ 462 outb(pcr, io + N2_PCR); 463 outb(0, io + N2_MCR); 464 465 sca_init(card, 0); 466 for (cnt = 0; cnt < 2; cnt++) { 467 port_t *port = &card->ports[cnt]; 468 469 if ((cnt == 0 && !valid0) || (cnt == 1 && !valid1)) 470 continue; 471 472 port->phy_node = cnt; 473 port->valid = 1; 474 475 if ((cnt == 1) && valid0) 476 port->log_node = 1; 477 478 spin_lock_init(&port->lock); 479 hdlc_to_dev(&port->hdlc)->irq = irq; 480 hdlc_to_dev(&port->hdlc)->mem_start = winbase; 481 hdlc_to_dev(&port->hdlc)->mem_end = winbase + USE_WINDOWSIZE-1; 482 hdlc_to_dev(&port->hdlc)->tx_queue_len = 50; 483 port->hdlc.ioctl = n2_ioctl; 484 port->hdlc.open = n2_open; 485 port->hdlc.close = n2_close; 486 port->hdlc.xmit = sca_xmit; 487 488 if (register_hdlc_device(&port->hdlc)) { 489 printk(KERN_WARNING "n2: unable to register hdlc " 490 "device\n"); 491 n2_destroy_card(card); 492 return -ENOBUFS; 493 } 494 port->card = card; 495 sca_init_sync_port(port); /* Set up SCA memory */ 496 497 printk(KERN_INFO "%s: RISCom/N2 node %d\n", 498 hdlc_to_name(&port->hdlc), port->phy_node); 499 } 500 501 *new_card = card; 502 new_card = &card->next_card; 503 504 return 0; 505} 506 507 508 509static int __init n2_init(void) 510{ 511 if (hw==NULL) { 512#ifdef MODULE 513 printk(KERN_INFO "n2: no card initialized\n"); 514#endif 515 return -ENOSYS; /* no parameters specified, abort */ 516 } 517 518 printk(KERN_INFO "%s\n", version); 519 520 do { 521 unsigned long io, irq, ram; 522 long valid[2] = { 0, 0 }; /* Default = both ports disabled */ 523 524 io = simple_strtoul(hw, &hw, 0); 525 526 if (*hw++ != ',') 527 break; 528 irq = simple_strtoul(hw, &hw, 0); 529 530 if (*hw++ != ',') 531 break; 532 ram = simple_strtoul(hw, &hw, 0); 533 534 if (*hw++ != ',') 535 break; 536 while(1) { 537 if (*hw == '0' && !valid[0]) 538 valid[0] = 1; /* Port 0 enabled */ 539 else if (*hw == '1' && !valid[1]) 540 valid[1] = 1; /* Port 1 enabled */ 541 else 542 break; 543 hw++; 544 } 545 546 if (!valid[0] && !valid[1]) 547 break; /* at least one port must be used */ 548 549 if (*hw == ':' || *hw == '\x0') 550 n2_run(io, irq, ram, valid[0], valid[1]); 551 552 if (*hw == '\x0') 553 return 0; 554 }while(*hw++ == ':'); 555 556 printk(KERN_ERR "n2: invalid hardware parameters\n"); 557 return first_card ? 0 : -ENOSYS; 558} 559 560 561#ifndef MODULE 562static int __init n2_setup(char *str) 563{ 564 hw = str; 565 return 1; 566} 567 568__setup("n2=", n2_setup); 569#endif 570 571 572static void __exit n2_cleanup(void) 573{ 574 card_t *card = first_card; 575 576 while (card) { 577 card_t *ptr = card; 578 card = card->next_card; 579 n2_destroy_card(ptr); 580 } 581} 582 583 584module_init(n2_init); 585module_exit(n2_cleanup); 586 587MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); 588MODULE_DESCRIPTION("RISCom/N2 serial port driver"); 589MODULE_LICENSE("GPL"); 590MODULE_PARM(hw, "s"); /* hw=io,irq,ram,ports:io,irq,... */ 591EXPORT_NO_SYMBOLS; 592