1/* 2 * Hitachi SCA HD64570 and HD64572 common driver for Linux 3 * 4 * Copyright (C) 1998-2000 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * Sources of information: 12 * Hitachi HD64570 SCA User's Manual 13 * Hitachi HD64572 SCA-II User's Manual 14 */ 15 16#include <linux/module.h> 17#include <linux/kernel.h> 18#include <linux/slab.h> 19#include <linux/sched.h> 20#include <linux/types.h> 21#include <linux/fcntl.h> 22#include <linux/interrupt.h> 23#include <linux/in.h> 24#include <linux/string.h> 25#include <linux/timer.h> 26#include <linux/errno.h> 27#include <linux/init.h> 28#include <linux/ioport.h> 29 30#include <asm/system.h> 31#include <asm/bitops.h> 32#include <asm/uaccess.h> 33#include <asm/io.h> 34 35#include <linux/netdevice.h> 36#include <linux/skbuff.h> 37 38#include <linux/hdlc.h> 39 40#if (!defined(__HD64570_H) && !defined(__HD64572_H)) || \ 41 (defined (__HD64570_H) && defined (__HD64572_H)) 42#error Either hd64570.h or hd64572.h must be included 43#endif 44 45 46static card_t *first_card; 47static card_t **new_card = &first_card; 48 49 50/* Maximum events to handle at each interrupt - should I increase it? */ 51#define INTR_WORK 4 52 53#define get_msci(port) (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) 54#define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET) 55#define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET) 56 57#define SCA_INTR_MSCI(node) (node ? 0x10 : 0x01) 58#define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02) 59#define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04) 60 61#ifdef __HD64570_H /* HD64570 */ 62#define sca_outa(value, reg, card) sca_outw(value, reg, card) 63#define sca_ina(reg, card) sca_inw(reg, card) 64#define writea(value, ptr) writew(value, ptr) 65 66static inline int sca_intr_status(card_t *card) 67{ 68 u8 isr0 = sca_in(ISR0, card); 69 u8 isr1 = sca_in(ISR1, card); 70 u8 result = 0; 71 72 if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0); 73 if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0); 74 if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1); 75 if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1); 76 if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0); 77 if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1); 78 79 return result; 80} 81 82#else /* HD64572 */ 83#define sca_outa(value, reg, card) sca_outl(value, reg, card) 84#define sca_ina(reg, card) sca_inl(reg, card) 85#define writea(value, ptr) writel(value, ptr) 86 87 88static inline int sca_intr_status(card_t *card) 89{ 90 u32 isr0 = sca_inl(ISR0, card); 91 u8 result = 0; 92 93 if (isr0 & 0x0000000F) result |= SCA_INTR_DMAC_RX(0); 94 if (isr0 & 0x000000F0) result |= SCA_INTR_DMAC_TX(0); 95 if (isr0 & 0x00000F00) result |= SCA_INTR_DMAC_RX(1); 96 if (isr0 & 0x0000F000) result |= SCA_INTR_DMAC_TX(1); 97 if (isr0 & 0x003E0000) result |= SCA_INTR_MSCI(0); 98 if (isr0 & 0x3E000000) result |= SCA_INTR_MSCI(1); 99 100 return result; 101} 102 103#endif /* HD64570 vs HD64572 */ 104 105 106 107 108static inline port_t* hdlc_to_port(hdlc_device *hdlc) 109{ 110 return (port_t*)hdlc; 111} 112 113 114 115static inline port_t* dev_to_port(struct net_device *dev) 116{ 117 return hdlc_to_port(dev_to_hdlc(dev)); 118} 119 120 121 122static inline u8 next_desc(port_t *port, u8 desc) 123{ 124 return (desc + 1) % port_to_card(port)->ring_buffers; 125} 126 127 128 129static inline u16 desc_offset(port_t *port, u8 desc, u8 transmit) 130{ 131 /* Descriptor offset always fits in 16 bytes */ 132 u8 buffs = port_to_card(port)->ring_buffers; 133 return ((log_node(port) * 2 + transmit) * buffs + (desc % buffs)) * 134 sizeof(pkt_desc); 135} 136 137 138 139static inline pkt_desc* desc_address(port_t *port, u8 desc, u8 transmit) 140{ 141#ifdef PAGE0_ALWAYS_MAPPED 142 return (pkt_desc*)(win0base(port_to_card(port)) 143 + desc_offset(port, desc, transmit)); 144#else 145 return (pkt_desc*)(winbase(port_to_card(port)) 146 + desc_offset(port, desc, transmit)); 147#endif 148} 149 150 151 152static inline u32 buffer_offset(port_t *port, u8 desc, u8 transmit) 153{ 154 u8 buffs = port_to_card(port)->ring_buffers; 155 return port_to_card(port)->buff_offset + 156 ((log_node(port) * 2 + transmit) * buffs + (desc % buffs)) * 157 (u32)HDLC_MAX_MRU; 158} 159 160 161 162static void sca_init_sync_port(port_t *port) 163{ 164 card_t *card = port_to_card(port); 165 u8 transmit, i; 166 u16 dmac, buffs = card->ring_buffers; 167 168 port->rxin = 0; 169 port->txin = 0; 170 port->txlast = 0; 171 172#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED) 173 openwin(card, 0); 174#endif 175 176 for (transmit = 0; transmit < 2; transmit++) { 177 for (i = 0; i < buffs; i++) { 178 pkt_desc* desc = desc_address(port, i, transmit); 179 u16 chain_off = desc_offset(port, i + 1, transmit); 180 u32 buff_off = buffer_offset(port, i, transmit); 181 182 writea(chain_off, &desc->cp); 183 writel(buff_off, &desc->bp); 184 writew(0, &desc->len); 185 writeb(0, &desc->stat); 186 } 187 188 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port); 189 /* DMA disable - to halt state */ 190 sca_out(0, transmit ? DSR_TX(phy_node(port)) : 191 DSR_RX(phy_node(port)), card); 192 /* software ABORT - to initial state */ 193 sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) : 194 DCR_RX(phy_node(port)), card); 195 196#ifdef __HD64570_H 197 sca_out(0, dmac + CPB, card); /* pointer base */ 198#endif 199 /* current desc addr */ 200 sca_outa(desc_offset(port, 0, transmit), dmac + CDAL, card); 201 if (!transmit) 202 sca_outa(desc_offset(port, buffs - 1, transmit), 203 dmac + EDAL, card); 204 else 205 sca_outa(desc_offset(port, 0, transmit), dmac + EDAL, 206 card); 207 208 /* clear frame end interrupt counter */ 209 sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) : 210 DCR_RX(phy_node(port)), card); 211 212 if (!transmit) { /* Receive */ 213 /* set buffer length */ 214 sca_outw(HDLC_MAX_MRU, dmac + BFLL, card); 215 /* Chain mode, Multi-frame */ 216 sca_out(0x14, DMR_RX(phy_node(port)), card); 217 sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)), 218 card); 219 /* DMA enable */ 220 sca_out(DSR_DE, DSR_RX(phy_node(port)), card); 221 } else { /* Transmit */ 222 /* Chain mode, Multi-frame */ 223 sca_out(0x14, DMR_TX(phy_node(port)), card); 224 /* enable underflow interrupts */ 225 sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card); 226 } 227 } 228} 229 230 231 232/* MSCI interrupt service */ 233static inline void sca_msci_intr(port_t *port) 234{ 235 u16 msci = get_msci(port); 236 card_t* card = port_to_card(port); 237 u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */ 238 239 /* printk(KERN_DEBUG "MSCI INT: ST1=%02X ILAR=%02X\n", 240 stat, sca_in(ILAR, card)); */ 241 242 /* Reset MSCI TX underrun status bit */ 243 sca_out(stat & ST1_UDRN, msci + ST1, card); 244 245 if (stat & ST1_UDRN) { 246 port->hdlc.stats.tx_errors++; /* TX Underrun error detected */ 247 port->hdlc.stats.tx_fifo_errors++; 248 } 249} 250 251 252 253static inline void sca_rx(card_t *card, port_t *port, pkt_desc *desc, 254 u8 rxin) 255{ 256 struct sk_buff *skb; 257 u16 len; 258 u32 buff; 259#ifndef ALL_PAGES_ALWAYS_MAPPED 260 u32 maxlen; 261 u8 page; 262#endif 263 264 len = readw(&desc->len); 265 skb = dev_alloc_skb(len); 266 if (!skb) { 267 port->hdlc.stats.rx_dropped++; 268 return; 269 } 270 271 buff = buffer_offset(port, rxin, 0); 272#ifndef ALL_PAGES_ALWAYS_MAPPED 273 page = buff / winsize(card); 274 buff = buff % winsize(card); 275 maxlen = winsize(card) - buff; 276 277 openwin(card, page); 278 279 if (len > maxlen) { 280 memcpy_fromio(skb->data, winbase(card) + buff, maxlen); 281 openwin(card, page + 1); 282 memcpy_fromio(skb->data + maxlen, winbase(card), len - maxlen); 283 } else 284#endif 285 memcpy_fromio(skb->data, winbase(card) + buff, len); 286 287#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED) 288 /* select pkt_desc table page back */ 289 openwin(card, 0); 290#endif 291 skb_put(skb, len); 292#ifdef DEBUG_PKT 293 printk(KERN_DEBUG "%s RX(%i):", hdlc_to_name(&port->hdlc), skb->len); 294 debug_frame(skb); 295#endif 296 port->hdlc.stats.rx_packets++; 297 port->hdlc.stats.rx_bytes += skb->len; 298 hdlc_netif_rx(&port->hdlc, skb); 299} 300 301 302 303/* Receive DMA interrupt service */ 304static inline void sca_rx_intr(port_t *port) 305{ 306 u16 dmac = get_dmac_rx(port); 307 card_t *card = port_to_card(port); 308 u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */ 309 struct net_device_stats *stats = &port->hdlc.stats; 310 311 /* Reset DSR status bits */ 312 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 313 DSR_RX(phy_node(port)), card); 314 315 if (stat & DSR_BOF) 316 stats->rx_over_errors++; /* Dropped one or more frames */ 317 318 while (1) { 319 u32 desc_off = desc_offset(port, port->rxin, 0); 320 pkt_desc *desc; 321 u32 cda = sca_ina(dmac + CDAL, card); 322 323 if (cda == desc_off) 324 break; /* No frame received */ 325 326#ifdef __HD64572_H 327 if (cda == desc_off + 8) 328 break; /* SCA-II updates CDA in 2 steps */ 329#endif 330 331 desc = desc_address(port, port->rxin, 0); 332 stat = readb(&desc->stat); 333 if (!(stat & ST_RX_EOM)) 334 port->rxpart = 1; /* partial frame received */ 335 else if ((stat & ST_ERROR_MASK) || port->rxpart) { 336 stats->rx_errors++; 337 if (stat & ST_RX_OVERRUN) stats->rx_fifo_errors++; 338 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | 339 ST_RX_RESBIT)) || port->rxpart) 340 stats->rx_frame_errors++; 341 else if (stat & ST_RX_CRC) stats->rx_crc_errors++; 342 if (stat & ST_RX_EOM) 343 port->rxpart = 0; /* received last fragment */ 344 } else 345 sca_rx(card, port, desc, port->rxin); 346 347 /* Set new error descriptor address */ 348 sca_outa(desc_off, dmac + EDAL, card); 349 port->rxin = next_desc(port, port->rxin); 350 } 351 352 /* make sure RX DMA is enabled */ 353 sca_out(DSR_DE, DSR_RX(phy_node(port)), card); 354} 355 356 357 358/* Transmit DMA interrupt service */ 359static inline void sca_tx_intr(port_t *port) 360{ 361 u16 dmac = get_dmac_tx(port); 362 card_t* card = port_to_card(port); 363 u8 stat; 364 365 spin_lock(&port->lock); 366 367 stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */ 368 369 /* Reset DSR status bits */ 370 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 371 DSR_TX(phy_node(port)), card); 372 373 while (1) { 374 u32 desc_off = desc_offset(port, port->txlast, 1); 375 pkt_desc *desc; 376 u16 len; 377 378 if (sca_ina(dmac + CDAL, card) == desc_off) 379 break; /* Transmitter is/will_be sending this frame */ 380 381 desc = desc_address(port, port->txlast, 1); 382 len = readw(&desc->len); 383 384 port->hdlc.stats.tx_packets++; 385 port->hdlc.stats.tx_bytes += len; 386 writeb(0, &desc->stat); /* Free descriptor */ 387 388 port->txlast = (port->txlast + 1) % 389 port_to_card(port)->ring_buffers; 390 } 391 392 netif_wake_queue(hdlc_to_dev(&port->hdlc)); 393 spin_unlock(&port->lock); 394} 395 396 397 398static void sca_intr(int irq, void* dev_id, struct pt_regs *regs) 399{ 400 card_t *card = dev_id; 401 int boguscnt = INTR_WORK; 402 int i; 403 u8 stat; 404 405#ifndef ALL_PAGES_ALWAYS_MAPPED 406 u8 page = sca_get_page(card); 407#endif 408 409 while((stat = sca_intr_status(card)) != 0) { 410 for (i = 0; i < 2; i++) { 411 port_t *port = get_port(card, i); 412 if (port) { 413 if (stat & SCA_INTR_MSCI(i)) 414 sca_msci_intr(port); 415 416 if (stat & SCA_INTR_DMAC_RX(i)) 417 sca_rx_intr(port); 418 419 if (stat & SCA_INTR_DMAC_TX(i)) 420 sca_tx_intr(port); 421 } 422 423 if (--boguscnt < 0) { 424 printk(KERN_ERR "%s: too much work at " 425 "interrupt\n", 426 hdlc_to_name(&port->hdlc)); 427 goto exit; 428 } 429 } 430 } 431 432 exit: 433#ifndef ALL_PAGES_ALWAYS_MAPPED 434 openwin(card, page); /* Restore original page */ 435#endif 436} 437 438 439 440static inline int sca_set_loopback(port_t *port, int line) 441{ 442 card_t* card = port_to_card(port); 443 u8 msci = get_msci(port); 444 u8 md2 = sca_in(msci + MD2, card); 445 446 switch(line) { 447 case LINE_DEFAULT: 448 md2 &= ~MD2_LOOPBACK; 449 port->line &= ~LINE_LOOPBACK; 450 break; 451 452 case LINE_LOOPBACK: 453 md2 |= MD2_LOOPBACK; 454 port->line |= LINE_LOOPBACK; 455 break; 456 457 default: 458 return -EINVAL; 459 } 460 461 sca_out(md2, msci + MD2, card); 462 return 0; 463} 464 465 466 467static void sca_set_clock(port_t *port) 468{ 469 card_t *card = port_to_card(port); 470 u8 msci = get_msci(port); 471 unsigned int tmc, br = 10, brv = 1024; 472 473 if (port->clkrate > 0) { 474 /* Try lower br for better accuracy*/ 475 do { 476 br--; 477 brv >>= 1; /* brv = 2^9 = 512 max in specs */ 478 479 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */ 480 tmc = CLOCK_BASE / (brv * port->clkrate); 481 }while(br > 1 && tmc <= 128); 482 483 if (tmc < 1) { 484 tmc = 1; 485 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */ 486 brv = 1; 487 } else if (tmc > 255) 488 tmc = 256; /* tmc=0 means 256 - low baud rates */ 489 490 port->clkrate = CLOCK_BASE / (brv * tmc); 491 } else { 492 br = 9; /* Minimum clock rate */ 493 tmc = 256; /* 8bit = 0 */ 494 port->clkrate = CLOCK_BASE / (256 * 512); 495 } 496 497 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br; 498 port->txs = (port->txs & ~CLK_BRG_MASK) | br; 499 port->tmc = tmc; 500 501 /* baud divisor - time constant*/ 502#ifdef __HD64570_H 503 sca_out(port->tmc, msci + TMC, card); 504#else 505 sca_out(port->tmc, msci + TMCR, card); 506 sca_out(port->tmc, msci + TMCT, card); 507#endif 508 509 /* Set BRG bits */ 510 sca_out(port->rxs, msci + RXS, card); 511 sca_out(port->txs, msci + TXS, card); 512} 513 514 515 516static void sca_set_hdlc_mode(port_t *port, u8 idle, u8 crc, u8 nrzi) 517{ 518 card_t* card = port_to_card(port); 519 u8 msci = get_msci(port); 520 u8 md2 = (nrzi ? MD2_NRZI : 0) | 521 ((port->line & LINE_LOOPBACK) ? MD2_LOOPBACK : 0); 522 u8 ctl = (idle ? CTL_IDLE : 0); 523#ifdef __HD64572_H 524 ctl |= CTL_URCT | CTL_URSKP; /* Skip the rest of underrun frame */ 525#endif 526 527 sca_out(CMD_RESET, msci + CMD, card); 528 sca_out(MD0_HDLC | crc, msci + MD0, card); 529 sca_out(0x00, msci + MD1, card); /* no address field check */ 530 sca_out(md2, msci + MD2, card); 531 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */ 532 sca_out(ctl, msci + CTL, card); 533 534#ifdef __HD64570_H 535 /* Allow at least 8 bytes before requesting RX DMA operation */ 536 /* TX with higher priority and possibly with shorter transfers */ 537 sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/ 538 sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/ 539 sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */ 540#else 541 sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */ 542 /* Setting than to larger value may cause Illegal Access */ 543 sca_out(0x20, msci + TNR0, card); /* =TX DMA activation condition */ 544 sca_out(0x30, msci + TNR1, card); /* +1=TX DMA deactivation condition*/ 545 sca_out(0x04, msci + TCR, card); /* =Critical TX DMA activ condition */ 546#endif 547 548 549#ifdef __HD64570_H 550 /* MSCI TX INT IRQ enable */ 551 sca_out(IE0_TXINT, msci + IE0, card); 552 sca_out(IE1_UDRN, msci + IE1, card); /* TX underrun IRQ */ 553 sca_out(sca_in(IER0, card) | (phy_node(port) ? 0x80 : 0x08), 554 IER0, card); 555 /* DMA IRQ enable */ 556 sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F), 557 IER1, card); 558#else 559 /* MSCI TX INT and underrrun IRQ enable */ 560 sca_outl(IE0_TXINT | IE0_UDRN, msci + IE0, card); 561 /* DMA & MSCI IRQ enable */ 562 sca_outl(sca_in(IER0, card) | 563 (phy_node(port) ? 0x02006600 : 0x00020066), IER0, card); 564#endif 565 566#ifdef __HD64570_H 567 sca_out(port->tmc, msci + TMC, card); /* Restore registers */ 568#else 569 sca_out(port->tmc, msci + TMCR, card); 570 sca_out(port->tmc, msci + TMCT, card); 571#endif 572 sca_out(port->rxs, msci + RXS, card); 573 sca_out(port->txs, msci + TXS, card); 574 sca_out(CMD_TX_ENABLE, msci + CMD, card); 575 sca_out(CMD_RX_ENABLE, msci + CMD, card); 576} 577 578 579 580#ifdef DEBUG_RINGS 581static void sca_dump_rings(hdlc_device *hdlc) 582{ 583 port_t *port = hdlc_to_port(hdlc); 584 card_t *card = port_to_card(port); 585 u16 cnt; 586#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED) 587 u8 page; 588#endif 589 590#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED) 591 page = sca_get_page(card); 592 openwin(card, 0); 593#endif 594 595 printk(KERN_ERR "RX ring: CDA=%u EDA=%u DSR=%02X in=%u " 596 "%sactive", 597 sca_ina(get_dmac_rx(port) + CDAL, card), 598 sca_ina(get_dmac_rx(port) + EDAL, card), 599 sca_in(DSR_RX(phy_node(port)), card), 600 port->rxin, 601 sca_in(DSR_RX(phy_node(port)), card) & DSR_DE?"":"in"); 602 for (cnt = 0; cnt<port_to_card(port)->ring_buffers; cnt++) 603 printk(" %02X", 604 readb(&(desc_address(port, cnt, 0)->stat))); 605 606 printk("\n" KERN_ERR "TX ring: CDA=%u EDA=%u DSR=%02X in=%u " 607 "last=%u %sactive", 608 sca_ina(get_dmac_tx(port) + CDAL, card), 609 sca_ina(get_dmac_tx(port) + EDAL, card), 610 sca_in(DSR_TX(phy_node(port)), card), port->txin, 611 port->txlast, 612 sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in"); 613 614 for (cnt = 0; cnt<port_to_card(port)->ring_buffers; cnt++) 615 printk(" %02X", 616 readb(&(desc_address(port, cnt, 1)->stat))); 617 printk("\n"); 618 619 printk(KERN_ERR "MSCI: MD: %02x %02x %02x, " 620 "ST: %02x %02x %02x %02x" 621#ifdef __HD64572_H 622 " %02x" 623#endif 624 ", FST: %02x CST: %02x %02x\n", 625 sca_in(get_msci(port) + MD0, card), 626 sca_in(get_msci(port) + MD1, card), 627 sca_in(get_msci(port) + MD2, card), 628 sca_in(get_msci(port) + ST0, card), 629 sca_in(get_msci(port) + ST1, card), 630 sca_in(get_msci(port) + ST2, card), 631 sca_in(get_msci(port) + ST3, card), 632#ifdef __HD64572_H 633 sca_in(get_msci(port) + ST4, card), 634#endif 635 sca_in(get_msci(port) + FST, card), 636 sca_in(get_msci(port) + CST0, card), 637 sca_in(get_msci(port) + CST1, card)); 638 639#ifdef __HD64572_H 640 printk(KERN_ERR "ILAR: %02x\n", sca_in(ILAR, card)); 641#endif 642 643#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED) 644 openwin(card, page); /* Restore original page */ 645#endif 646} 647#endif /* DEBUG_RINGS */ 648 649 650 651static void sca_open(hdlc_device *hdlc) 652{ 653 port_t *port = hdlc_to_port(hdlc); 654 655 sca_set_hdlc_mode(port, 1, MD0_CRC_ITU, 0); 656 netif_start_queue(hdlc_to_dev(hdlc)); 657} 658 659 660static void sca_close(hdlc_device *hdlc) 661{ 662 port_t *port = hdlc_to_port(hdlc); 663 664 /* reset channel */ 665 netif_stop_queue(hdlc_to_dev(hdlc)); 666 sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port)); 667} 668 669 670 671static int sca_xmit(hdlc_device *hdlc, struct sk_buff *skb) 672{ 673 port_t *port = hdlc_to_port(hdlc); 674 struct net_device *dev = hdlc_to_dev(hdlc); 675 card_t *card = port_to_card(port); 676 pkt_desc *desc; 677 u32 buff, len; 678#ifndef ALL_PAGES_ALWAYS_MAPPED 679 u8 page; 680 u32 maxlen; 681#endif 682 683 spin_lock_irq(&port->lock); 684 685 desc = desc_address(port, port->txin + 1, 1); 686 if (readb(&desc->stat)) { /* allow 1 packet gap */ 687 /* should never happen - previous xmit should stop queue */ 688#ifdef DEBUG_PKT 689 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name); 690#endif 691 netif_stop_queue(dev); 692 spin_unlock_irq(&port->lock); 693 return 1; /* request packet to be queued */ 694 } 695 696#ifdef DEBUG_PKT 697 printk(KERN_DEBUG "%s TX(%i):", hdlc_to_name(hdlc), skb->len); 698 debug_frame(skb); 699#endif 700 701 desc = desc_address(port, port->txin, 1); 702 buff = buffer_offset(port, port->txin, 1); 703 len = skb->len; 704#ifndef ALL_PAGES_ALWAYS_MAPPED 705 page = buff / winsize(card); 706 buff = buff % winsize(card); 707 maxlen = winsize(card) - buff; 708 709 openwin(card, page); 710 if (len > maxlen) { 711 memcpy_toio(winbase(card) + buff, skb->data, maxlen); 712 openwin(card, page + 1); 713 memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen); 714 } 715 else 716#endif 717 memcpy_toio(winbase(card) + buff, skb->data, len); 718 719#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED) 720 openwin(card, 0); /* select pkt_desc table page back */ 721#endif 722 writew(len, &desc->len); 723 writeb(ST_TX_EOM, &desc->stat); 724 dev->trans_start = jiffies; 725 726 port->txin = next_desc(port, port->txin); 727 sca_outa(desc_offset(port, port->txin, 1), 728 get_dmac_tx(port) + EDAL, card); 729 730 sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */ 731 732 desc = desc_address(port, port->txin + 1, 1); 733 if (readb(&desc->stat)) /* allow 1 packet gap */ 734 netif_stop_queue(hdlc_to_dev(&port->hdlc)); 735 736 spin_unlock_irq(&port->lock); 737 738 dev_kfree_skb(skb); 739 return 0; 740} 741 742 743static void sca_init(card_t *card, int wait_states) 744{ 745 sca_out(wait_states, WCRL, card); /* Wait Control */ 746 sca_out(wait_states, WCRM, card); 747 sca_out(wait_states, WCRH, card); 748 749 sca_out(0, DMER, card); /* DMA Master disable */ 750 sca_out(0x03, PCR, card); /* DMA priority */ 751 sca_out(0, IER1, card); /* DMA interrupt disable */ 752 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */ 753 sca_out(0, DSR_TX(0), card); 754 sca_out(0, DSR_RX(1), card); 755 sca_out(0, DSR_TX(1), card); 756 sca_out(DMER_DME, DMER, card); /* DMA Master enable */ 757} 758