1/****************************************************************************** 2 * 3 * Name: xmac_ii.h 4 * Project: GEnesis, PCI Gigabit Ethernet Adapter 5 * Version: $Revision: 1.1.1.1 $ 6 * Date: $Date: 2008/10/15 03:26:44 $ 7 * Purpose: Defines and Macros for XaQti's Gigabit Ethernet Controller 8 * 9 ******************************************************************************/ 10 11/****************************************************************************** 12 * 13 * (C)Copyright 1998-2000 SysKonnect GmbH. 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * The information in this file is provided "AS IS" without warranty. 21 * 22 ******************************************************************************/ 23 24/****************************************************************************** 25 * 26 * History: 27 * 28 * $Log: xmac_ii.h,v $ 29 * Revision 1.1.1.1 2008/10/15 03:26:44 james26_jang 30 * Initial. 31 * 32 * Revision 1.1.1.1 2008/07/21 09:15:07 james26_jang 33 * New UI, New QoS, New wireless driver(4.151.10.29), ipmonitor. 34 * 35 * Revision 1.1 2008/07/17 12:43:35 james26_jang 36 * *** empty log message *** 37 * 38 * Revision 1.1.1.1 2007/02/15 12:11:35 jiahao 39 * initial update 40 * 41 * Revision 1.1.1.1 2007/01/25 12:51:56 jiahao_jhou 42 * 43 * 44 * Revision 1.1.1.1 2003/02/03 22:37:48 mhuang 45 * LINUX_2_4 branch snapshot from linux-mips.org CVS 46 * 47 * Revision 1.28 2000/11/09 12:32:49 rassmann 48 * Renamed variables. 49 * 50 * Revision 1.27 2000/05/17 11:00:46 malthoff 51 * Add bit for enable/disable power management in BCOM chip. 52 * 53 * Revision 1.26 1999/11/22 14:03:00 cgoos 54 * Changed license header to GPL. 55 * 56 * Revision 1.25 1999/08/12 19:19:38 malthoff 57 * Add PHY_B_AC_TX_TST bit according to BCOM A1 errata sheet. 58 * 59 * Revision 1.24 1999/07/30 11:27:21 cgoos 60 * Fixed a missing end-of-comment. 61 * 62 * Revision 1.23 1999/07/30 07:03:31 malthoff 63 * Cut some long comments. 64 * Correct the XMAC PHY ID definitions. 65 * 66 * Revision 1.22 1999/05/19 07:33:18 cgoos 67 * Changes for 1000Base-T. 68 * 69 * Revision 1.21 1999/03/25 07:46:11 malthoff 70 * Add XM_HW_CFG, XM_TS_READ, and XM_TS_LOAD registers. 71 * 72 * Revision 1.20 1999/03/12 13:36:09 malthoff 73 * Remove __STDC__. 74 * 75 * Revision 1.19 1998/12/10 12:22:54 gklug 76 * fix: RX_PAGE must be in interrupt mask 77 * 78 * Revision 1.18 1998/12/10 10:36:36 gklug 79 * fix: swap of pause bits 80 * 81 * Revision 1.17 1998/11/18 13:21:45 gklug 82 * fix: Default interrupt mask 83 * 84 * Revision 1.16 1998/10/29 15:53:21 gklug 85 * fix: Default mask uses ASS (GP0) signal 86 * 87 * Revision 1.15 1998/10/28 13:52:52 malthoff 88 * Add new bits in RX_CMD register. 89 * 90 * Revision 1.14 1998/10/19 15:34:53 gklug 91 * fix: typos 92 * 93 * Revision 1.13 1998/10/14 07:19:03 malthoff 94 * bug fix: Every define which describes bit 31 95 * must be declared as unsigned long 'UL'. 96 * fix bit definitions of PHY_AN_RFB and PHY_AN_PAUSE. 97 * Remove ANP defines. Rework the RFB defines. 98 * 99 * Revision 1.12 1998/10/14 06:22:44 cgoos 100 * Changed shifted constant to ULONG. 101 * 102 * Revision 1.11 1998/10/14 05:43:26 gklug 103 * add: shift pause codeing 104 * fix: PAUSE bits definition 105 * 106 * Revision 1.10 1998/10/13 09:19:21 malthoff 107 * Again change XMR_FS_ANY_ERR because of new info from XaQti. 108 * 109 * Revision 1.9 1998/10/09 07:58:30 malthoff 110 * Add XMR_FS_FCS_ERR to XMR_FS_ANY_ERR. 111 * 112 * Revision 1.8 1998/10/09 07:18:17 malthoff 113 * bug fix of a bug fix: XM_PAUSE_MODE and XM_DEF_MODE 114 * are not inverted! Bug XM_DEF_MSK is inverted. 115 * 116 * Revision 1.7 1998/10/05 08:04:32 malthoff 117 * bug fix: XM_PAUSE_MODE and XM_DEF_MODE 118 * must be inverted declarations. 119 * 120 * Revision 1.6 1998/09/28 13:38:18 malthoff 121 * Add default modes and masks XM_DEF_MSK, 122 * XM_PAUSE_MODE and XM_DEF_MODE 123 * 124 * Revision 1.5 1998/09/16 14:42:04 malthoff 125 * Bug Fix: XM_GP_PORT is a 32 bit (not a 16 bit) register. 126 * 127 * Revision 1.4 1998/08/20 14:59:47 malthoff 128 * Rework this file after reading the XaQti data sheet 129 * "Differences between Rev. B2 & Rev. C XMAC II". 130 * This file is now 100% XMAC II Rev. C complained. 131 * 132 * Revision 1.3 1998/06/29 12:18:23 malthoff 133 * Correct XMR_FS_ANY_ERR definition. 134 * 135 * Revision 1.2 1998/06/29 12:10:56 malthoff 136 * Add define XMR_FS_ANY_ERR. 137 * 138 * Revision 1.1 1998/06/19 13:37:17 malthoff 139 * created. 140 * 141 * 142 ******************************************************************************/ 143 144#ifndef __INC_XMAC_H 145#define __INC_XMAC_H 146 147#ifdef __cplusplus 148extern "C" { 149#endif /* __cplusplus */ 150 151/* defines ********************************************************************/ 152 153/* 154 * XMAC II registers 155 * 156 * The XMAC registers are 16 or 32 bits wide. The XMACs host processor 157 * interface is set to 16 bit mode, therefore ALL registers will be 158 * addressed with 16 bit accesses. 159 * 160 * The following macros are provided to access the XMAC registers 161 * XM_IN16(), XM_OUT16, XM_IN32(), MX_OUT32(), XM_INADR(), XM_OUTADR(), 162 * XM_INHASH(), and XM_OUTHASH(). 163 * The macros are defined in SkGeHw.h. 164 * 165 * Note: NA reg = Network Address e.g DA, SA etc. 166 * 167 */ 168#define XM_MMU_CMD 0x0000 /* 16 bit r/w MMU Command Register */ 169 /* 0x0004: reserved */ 170#define XM_POFF 0x0008 /* 32 bit r/w Packet Offset Register */ 171#define XM_BURST 0x000c /* 32 bit r/w Burst Register for half duplex*/ 172#define XM_1L_VLAN_TAG 0x0010 /* 16 bit r/w One Level VLAN Tag ID */ 173#define XM_2L_VLAN_TAG 0x0014 /* 16 bit r/w Two Level VLAN Tag ID */ 174 /* 0x0018 - 0x001e: reserved */ 175#define XM_TX_CMD 0x0020 /* 16 bit r/w Transmit Command Register */ 176#define XM_TX_RT_LIM 0x0024 /* 16 bit r/w Transmit Retry Limit Register */ 177#define XM_TX_STIME 0x0028 /* 16 bit r/w Transmit Slottime Register */ 178#define XM_TX_IPG 0x002c /* 16 bit r/w Transmit Inter Packet Gap */ 179#define XM_RX_CMD 0x0030 /* 16 bit r/w Receive Command Register */ 180#define XM_PHY_ADDR 0x0034 /* 16 bit r/w PHY Address Register */ 181#define XM_PHY_DATA 0x0038 /* 16 bit r/w PHY Data Register */ 182 /* 0x003c: reserved */ 183#define XM_GP_PORT 0x0040 /* 32 bit r/w General Purpose Port Register */ 184#define XM_IMSK 0x0044 /* 16 bit r/w Interrupt Mask Register */ 185#define XM_ISRC 0x0048 /* 16 bit ro Interrupt Status Register */ 186#define XM_HW_CFG 0x004c /* 16 bit r/w Hardware Config Register */ 187 /* 0x0050 - 0x005e: reserved */ 188#define XM_TX_LO_WM 0x0060 /* 16 bit r/w Tx FIFO Low Water Mark */ 189#define XM_TX_HI_WM 0x0062 /* 16 bit r/w Tx FIFO High Water Mark */ 190#define XM_TX_THR 0x0064 /* 16 bit r/w Tx Request Threshold */ 191#define XM_HT_THR 0x0066 /* 16 bit r/w Host Request Threshold */ 192#define XM_PAUSE_DA 0x0068 /* NA reg r/w Pause Destination Address */ 193 /* 0x006e: reserved */ 194#define XM_CTL_PARA 0x0070 /* 32 bit r/w Control Parameter Register */ 195#define XM_MAC_OPCODE 0x0074 /* 16 bit r/w Opcode for MAC control frames */ 196#define XM_MAC_PTIME 0x0076 /* 16 bit r/w Pause time for MAC ctrl frames*/ 197#define XM_TX_STAT 0x0078 /* 32 bit ro Tx Status LIFO Register */ 198 199 /* 0x0080 - 0x00fc: 16 NA reg r/w Exakt Match Address Registers */ 200 /* use the XM_EMX() macro to address */ 201#define XM_EXM_START 0x0080 /* r/w Start Address of the EXM Regs */ 202 203 /* 204 * XM_EXM(Reg) 205 * 206 * returns the XMAC address offset off specified Exakt Match Addr Reg 207 * 208 * para: Reg EXM register to addr (0 .. 15) 209 * 210 * usage: XM_INADDR(XMAC_1,pAC,XM_EXM(i),&val[i]) ; 211 */ 212#define XM_EXM(Reg) (XM_EXM_START + ((Reg) << 3)) 213 214#define XM_SRC_CHK 0x0100 /* NA reg r/w Source Check Address Register */ 215#define XM_SA 0x0108 /* NA reg r/w Station Address Register */ 216#define XM_HSM 0x0110 /* 64 bit r/w Hash Match Address Registers */ 217#define XM_RX_LO_WM 0x0118 /* 16 bit r/w Receive Low Water Mark */ 218#define XM_RX_HI_WM 0x011a /* 16 bit r/w Receive High Water Mark */ 219#define XM_RX_THR 0x011c /* 32 bit r/w Receive Request Threshold */ 220#define XM_DEV_ID 0x0120 /* 32 bit ro Device ID Register */ 221#define XM_MODE 0x0124 /* 32 bit r/w Mode Register */ 222#define XM_LSA 0x0128 /* NA reg ro Last Source Register */ 223 /* 0x012e: reserved */ 224#define XM_TS_READ 0x0130 /* 32 bit ro TimeStamp Read Regeister */ 225#define XM_TS_LOAD 0x0134 /* 32 bit ro TimeStamp Load Value */ 226 /* 0x0138 - 0x01fe: reserved */ 227#define XM_STAT_CMD 0x0200 /* 16 bit r/w Statistics Command Register */ 228#define XM_RX_CNT_EV 0x0204 /* 32 bit ro Rx Counter Event Register */ 229#define XM_TX_CNT_EV 0x0208 /* 32 bit ro Tx Counter Event Register */ 230#define XM_RX_EV_MSK 0x020c /* 32 bit r/w Rx Counter Event Mask */ 231#define XM_TX_EV_MSK 0x0210 /* 32 bit r/w Tx Counter Event Mask */ 232 /* 0x0204 - 0x027e: reserved */ 233#define XM_TXF_OK 0x0280 /* 32 bit ro Frames Transmitted OK Conuter */ 234#define XM_TXO_OK_HI 0x0284 /* 32 bit ro Octets Transmitted OK High Cnt*/ 235#define XM_TXO_OK_LO 0x0288 /* 32 bit ro Octets Transmitted OK Low Cnt */ 236#define XM_TXF_BC_OK 0x028c /* 32 bit ro Broadcast Frames Xmitted OK */ 237#define XM_TXF_MC_OK 0x0290 /* 32 bit ro Multicast Frames Xmitted OK */ 238#define XM_TXF_UC_OK 0x0294 /* 32 bit ro Unicast Frames Xmitted OK */ 239#define XM_TXF_LONG 0x0298 /* 32 bit ro Tx Long Frame Counter */ 240#define XM_TXE_BURST 0x029c /* 32 bit ro Tx Burst Event Counter */ 241#define XM_TXF_MPAUSE 0x02a0 /* 32 bit ro Tx Pause MAC Ctrl Frame Cnt */ 242#define XM_TXF_MCTRL 0x02a4 /* 32 bit ro Tx MAC Ctrl Frame Counter */ 243#define XM_TXF_SNG_COL 0x02a8 /* 32 bit ro Tx Single Colliosion Counter */ 244#define XM_TXF_MUL_COL 0x02ac /* 32 bit ro Tx Multiple Collision Counter */ 245#define XM_TXF_ABO_COL 0x02b0 /* 32 bit ro Tx aborted due to Exessive Col*/ 246#define XM_TXF_LAT_COL 0x02b4 /* 32 bit ro Tx Late Collision Counter */ 247#define XM_TXF_DEF 0x02b8 /* 32 bit ro Tx Deferred Frame Counter */ 248#define XM_TXF_EX_DEF 0x02bc /* 32 bit ro Tx Excessive Deferall Counter */ 249#define XM_TXE_FIFO_UR 0x02c0 /* 32 bit ro Tx FIFO Underrun Event Cnt */ 250#define XM_TXE_CS_ERR 0x02c4 /* 32 bit ro Tx Carrier Sence Error Cnt */ 251#define XM_TXP_UTIL 0x02c8 /* 32 bit ro Tx Utilization in % */ 252 /* 0x02cc - 0x02ce: reserved */ 253#define XM_TXF_64B 0x02d0 /* 32 bit ro 64 Byte Tx Frame Counter */ 254#define XM_TXF_127B 0x02d4 /* 32 bit ro 65-127 Byte Tx Frame Counter */ 255#define XM_TXF_255B 0x02d8 /* 32 bit ro 128-255 Byte Tx Frame Counter */ 256#define XM_TXF_511B 0x02dc /* 32 bit ro 256-511 Byte Tx Frame Counter */ 257#define XM_TXF_1023B 0x02e0 /* 32 bit ro 512-1023 Byte Tx Frame Counter*/ 258#define XM_TXF_MAX_SZ 0x02e4 /* 32 bit ro 1024-MaxSize Byte Tx Frame Cnt*/ 259 /* 0x02e8 - 0x02fe: reserved */ 260#define XM_RXF_OK 0x0300 /* 32 bit ro Frames Received OK */ 261#define XM_RXO_OK_HI 0x0304 /* 32 bit ro Octets Received OK High Cnt */ 262#define XM_RXO_OK_LO 0x0308 /* 32 bit ro Octets Received OK Low Counter*/ 263#define XM_RXF_BC_OK 0x030c /* 32 bit ro Broadcast Frames Received OK */ 264#define XM_RXF_MC_OK 0x0310 /* 32 bit ro Multicast Frames Received OK */ 265#define XM_RXF_UC_OK 0x0314 /* 32 bit ro Unicast Frames Received OK */ 266#define XM_RXF_MPAUSE 0x0318 /* 32 bit ro Rx Pause MAC Ctrl Frame Cnt */ 267#define XM_RXF_MCTRL 0x031c /* 32 bit ro Rx MAC Ctrl Frame Counter */ 268#define XM_RXF_INV_MP 0x0320 /* 32 bit ro Rx invalid Pause Frame Cnt */ 269#define XM_RXF_INV_MOC 0x0324 /* 32 bit ro Rx Frames with inv. MAC Opcode*/ 270#define XM_RXE_BURST 0x0328 /* 32 bit ro Rx Burst Event Counter */ 271#define XM_RXE_FMISS 0x032c /* 32 bit ro Rx Missed Frames Event Cnt */ 272#define XM_RXF_FRA_ERR 0x0330 /* 32 bit ro Rx Framing Error Counter */ 273#define XM_RXE_FIFO_OV 0x0334 /* 32 bit ro Rx FIFO overflow Event Cnt */ 274#define XM_RXF_JAB_PKT 0x0338 /* 32 bit ro Rx Jabber Packet Frame Cnt */ 275#define XM_RXE_CAR_ERR 0x033c /* 32 bit ro Rx Carrier Event Error Cnt */ 276#define XM_RXF_LEN_ERR 0x0340 /* 32 bit ro Rx in Range Length Error */ 277#define XM_RXE_SYM_ERR 0x0344 /* 32 bit ro Rx Symbol Error Counter */ 278#define XM_RXE_SHT_ERR 0x0348 /* 32 bit ro Rx Short Event Error Cnt */ 279#define XM_RXE_RUNT 0x034c /* 32 bit ro Rx Runt Event Counter */ 280#define XM_RXF_LNG_ERR 0x0350 /* 32 bit ro Rx Frame too Long Error Cnt */ 281#define XM_RXF_FCS_ERR 0x0354 /* 32 bit ro Rx Frame Check Seq. Error Cnt */ 282 /* 0x0358 - 0x035a: reserved */ 283#define XM_RXF_CEX_ERR 0x035c /* 32 bit ro Rx Carrier Ext Error Frame Cnt*/ 284#define XM_RXP_UTIL 0x0360 /* 32 bit ro Rx Utilization in % */ 285 /* 0x0364 - 0x0366: reserved */ 286#define XM_RXF_64B 0x0368 /* 32 bit ro 64 Byte Rx Frame Counter */ 287#define XM_RXF_127B 0x036c /* 32 bit ro 65-127 Byte Rx Frame Counter */ 288#define XM_RXF_255B 0x0370 /* 32 bit ro 128-255 Byte Rx Frame Counter */ 289#define XM_RXF_511B 0x0374 /* 32 bit ro 256-511 Byte Rx Frame Counter */ 290#define XM_RXF_1023B 0x0378 /* 32 bit ro 512-1023 Byte Rx Frame Counter*/ 291#define XM_RXF_MAX_SZ 0x037c /* 32 bit ro 1024-MaxSize Byte Rx Frame Cnt*/ 292 /* 0x02e8 - 0x02fe: reserved */ 293 294 295/*----------------------------------------------------------------------------*/ 296/* 297 * XMAC Bit Definitions 298 * 299 * If the bit access behaviour differs from the register access behaviour 300 * (r/w, ro) this is docomented after the bit number. The following bit 301 * access behaviours are used: 302 * (sc) self clearing 303 * (ro) read only 304 */ 305 306/* XM_MMU_CMD 16 bit r/w MMU Comamnd Register */ 307 /* Bit 15..13: reserved */ 308#define XM_MMU_PHY_RDY (1<<12) /* Bit 12: PHY Read Ready */ 309#define XM_MMU_PHY_BUSY (1<<11) /* Bit 11: PHY Busy */ 310#define XM_MMU_IGN_PF (1<<10) /* Bit 10: Ignore Pause Frame */ 311#define XM_MMU_MAC_LB (1<<9) /* Bit 9: Enable MAC Loopback */ 312 /* Bit 8: reserved */ 313#define XM_MMU_FRC_COL (1<<7) /* Bit 7: Force Collision */ 314#define XM_MMU_SIM_COL (1<<6) /* Bit 6: Simulate Collision */ 315#define XM_MMU_NO_PRE (1<<5) /* Bit 5: No MDIO Preamble */ 316#define XM_MMU_GMII_FD (1<<4) /* Bit 4: GMII uses Full Duplex */ 317#define XM_MMU_RAT_CTRL (1<<3) /* Bit 3: Enable Rate Control */ 318#define XM_MMU_GMII_LOOP (1<<2) /* Bit 2: PHY is in Lookback Mode */ 319#define XM_MMU_ENA_RX (1<<1) /* Bit 1: Enable Receiver */ 320#define XM_MMU_ENA_TX (1<<0) /* Bit 0: Enable Transmitter */ 321 322 323/* XM_TX_CMD 16 bit r/w Transmit Command Register */ 324 /* Bit 15..7: reserved */ 325#define XM_TX_BK2BK (1<<6) /* Bit 6: Ignor Carrier Sense (tx Bk2Bk)*/ 326#define XM_TX_ENC_BYP (1<<5) /* Bit 5: Set Encoder in Bypass Mode */ 327#define XM_TX_SAM_LINE (1<<4) /* Bit 4: (sc) Start utilization calculation */ 328#define XM_TX_NO_GIG_MD (1<<3) /* Bit 3: Disable Carrier Extension */ 329#define XM_TX_NO_PRE (1<<2) /* Bit 2: Disable Preamble Generation */ 330#define XM_TX_NO_CRC (1<<1) /* Bit 1: Disable CRC Generation */ 331#define XM_TX_AUTO_PAD (1<<0) /* Bit 0: Enable Automatic Padding */ 332 333 334/* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */ 335 /* Bit 15..5: reserved */ 336#define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */ 337 338 339/* XM_TX_STIME 16 bit r/w Transmit Slottime Register */ 340 /* Bit 15..7: reserved */ 341#define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */ 342 343 344/* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */ 345 /* Bit 15..8: reserved */ 346#define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */ 347 348 349/* XM_RX_CMD 16 bit r/w Receive Command Register */ 350 /* Bit 15..9: reserved */ 351#define XM_RX_LENERR_OK (1<<8) /* Bit 8 don't set Rx Err bit for */ 352 /* inrange error packets */ 353#define XM_RX_BIG_PK_OK (1<<7) /* Bit 7 don't set Rx Err bit for */ 354 /* jumbo packets */ 355#define XM_RX_IPG_CAP (1<<6) /* Bit 6 repl. type field with IPG */ 356#define XM_RX_TP_MD (1<<5) /* Bit 5: Enable transparent Mode */ 357#define XM_RX_STRIP_FCS (1<<4) /* Bit 4: Enable FCS Stripping */ 358#define XM_RX_SELF_RX (1<<3) /* Bit 3: Enable Rx of own packets */ 359#define XM_RX_SAM_LINE (1<<2) /* Bit 2: (sc) Start utilization calculation */ 360#define XM_RX_STRIP_PAD (1<<1) /* Bit 1: Strip pad bytes of rx frames */ 361#define XM_RX_DIS_CEXT (1<<0) /* Bit 0: Disable carrier ext. check */ 362 363 364/* XM_PHY_ADDR 16 bit r/w PHY Address Register */ 365 /* Bit 15..5: reserved */ 366#define XM_PHY_ADDR_SZ 0x1f /* Bit 4..0: PHY Address bits */ 367 368 369/* XM_GP_PORT 32 bit r/w General Purpose Port Register */ 370 /* Bit 31..7: reserved */ 371#define XM_GP_ANIP (1L<<6) /* Bit 6: (ro) Auto Negotiation in Progress */ 372#define XM_GP_FRC_INT (1L<<5) /* Bit 5: (sc) Force Interrupt */ 373 /* Bit 4: reserved */ 374#define XM_GP_RES_MAC (1L<<3) /* Bit 3: (sc) Reset MAC and FIFOs */ 375#define XM_GP_RES_STAT (1L<<2) /* Bit 2: (sc) Reset the statistics module */ 376 /* Bit 1: reserved */ 377#define XM_GP_INP_ASS (1L<<0) /* Bit 0: (ro) GP Input Pin asserted */ 378 379 380/* XM_IMSK 16 bit r/w Interrupt Mask Register */ 381/* XM_ISRC 16 bit ro Interrupt Status Register */ 382 /* Bit 15: reserved */ 383#define XM_IS_LNK_AE (1<<14) /* Bit 14: Link Asynchronous Event */ 384#define XM_IS_TX_ABORT (1<<13) /* Bit 13: Transmit Abort, late Col. etc */ 385#define XM_IS_FRC_INT (1<<12) /* Bit 12: Force INT bit set in GP */ 386#define XM_IS_INP_ASS (1<<11) /* Bit 11: Input Asserted, GP bit 0 set */ 387#define XM_IS_LIPA_RC (1<<10) /* Bit 10: Link Partner requests config */ 388#define XM_IS_RX_PAGE (1<<9) /* Bit 9: Page Received */ 389#define XM_IS_TX_PAGE (1<<8) /* Bit 8: Next Page Loaded for Transmit */ 390#define XM_IS_AND (1<<7) /* Bit 7: Auto Negotiation Done */ 391#define XM_IS_TSC_OV (1<<6) /* Bit 6: Time Stamp Counter Overflow */ 392#define XM_IS_RXC_OV (1<<5) /* Bit 5: Rx Counter Event Overflow */ 393#define XM_IS_TXC_OV (1<<4) /* Bit 4: Tx Counter Event Overflow */ 394#define XM_IS_RXF_OV (1<<3) /* Bit 3: Receive FIFO Overflow */ 395#define XM_IS_TXF_UR (1<<2) /* Bit 2: Transmit FIFO Underrun */ 396#define XM_IS_TX_COMP (1<<1) /* Bit 1: Frame Tx Complete */ 397#define XM_IS_RX_COMP (1<<0) /* Bit 0: Frame Rx Complete */ 398 399#define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE |\ 400 XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | XM_IS_TXF_UR)) 401 402 403/* XM_HW_CFG 16 bit r/w Hardware Config Register */ 404 /* Bit 15.. 4: reserved */ 405#define XM_HW_GEN_EOP (1<<3) /* Bit 3: generate End of Packet pulse */ 406#define XM_HW_COM4SIG (1<<2) /* Bit 2: use Comma Detect for Sig. Det.*/ 407 /* Bit 1: reserved */ 408#define XM_HW_GMII_MD (1<<0) /* Bit 0: GMII Interface selected */ 409 410 411/* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */ 412/* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */ 413 /* Bit 15..10 reserved */ 414#define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */ 415 416/* XM_TX_THR 16 bit r/w Tx Request Threshold */ 417/* XM_HT_THR 16 bit r/w Host Request Threshold */ 418/* XM_RX_THR 16 bit r/w Receive Request Threshold */ 419 /* Bit 15..11 reserved */ 420#define XM_THR_MSK 0x03ff /* Bit 10.. 0 Tx FIFO Watermark bits */ 421 422 423/* XM_TX_STAT 32 bit ro Tx Status LIFO Register */ 424#define XM_ST_VALID (1UL<<31) /* Bit 31: Status Valid */ 425#define XM_ST_BYTE_CNT (0x3fffL<<17) /* Bit 30..17: Tx frame Length */ 426#define XM_ST_RETRY_CNT (0x1fL<<12) /* Bit 16..12: Retry Count */ 427#define XM_ST_EX_COL (1L<<11) /* Bit 11: Excessive Collisions */ 428#define XM_ST_EX_DEF (1L<<10) /* Bit 10: Excessive Deferral */ 429#define XM_ST_BURST (1L<<9) /* Bit 9: p. xmitted in burst md*/ 430#define XM_ST_DEFER (1L<<8) /* Bit 8: packet was defered */ 431#define XM_ST_BC (1L<<7) /* Bit 7: Broadcast packet */ 432#define XM_ST_MC (1L<<6) /* Bit 6: Multicast packet */ 433#define XM_ST_UC (1L<<5) /* Bit 5: Unicast packet */ 434#define XM_ST_TX_UR (1L<<4) /* Bit 4: FIFO Underrun occured */ 435#define XM_ST_CS_ERR (1L<<3) /* Bit 3: Carrier Sense Error */ 436#define XM_ST_LAT_COL (1L<<2) /* Bit 2: Late Collision Error */ 437#define XM_ST_MUL_COL (1L<<1) /* Bit 1: Multiple Collisions */ 438#define XM_ST_SGN_COL (1L<<0) /* Bit 0: Single Collision */ 439 440/* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */ 441/* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */ 442 /* Bit 15..11: reserved */ 443#define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */ 444 445 446/* XM_DEV_ID 32 bit ro Device ID Register */ 447#define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */ 448#define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */ 449 450 451/* XM_MODE 32 bit r/w Mode Register */ 452 /* Bit 31..27: reserved */ 453#define XM_MD_ENA_REJ (1L<<26) /* Bit 26: Enable Frame Reject */ 454#define XM_MD_SPOE_E (1L<<25) /* Bit 25: Send Pause on Edge */ 455 /* extern generated */ 456#define XM_MD_TX_REP (1L<<24) /* Bit 24: Transmit Repeater Mode*/ 457#define XM_MD_SPOFF_I (1L<<23) /* Bit 23: Send Pause on FIFOfull*/ 458 /* intern generated */ 459#define XM_MD_LE_STW (1L<<22) /* Bit 22: Rx Stat Word in Lit En*/ 460#define XM_MD_TX_CONT (1L<<21) /* Bit 21: Send Continuous */ 461#define XM_MD_TX_PAUSE (1L<<20) /* Bit 20: (sc) Send Pause Frame */ 462#define XM_MD_ATS (1L<<19) /* Bit 19: Append Time Stamp */ 463#define XM_MD_SPOL_I (1L<<18) /* Bit 18: Send Pause on Low */ 464 /* intern generated */ 465#define XM_MD_SPOH_I (1L<<17) /* Bit 17: Send Pause on High */ 466 /* intern generated */ 467#define XM_MD_CAP (1L<<16) /* Bit 16: Check Address Pair */ 468#define XM_MD_ENA_HSH (1L<<15) /* Bit 15: Enable Hashing */ 469#define XM_MD_CSA (1L<<14) /* Bit 14: Check Station Address */ 470#define XM_MD_CAA (1L<<13) /* Bit 13: Check Address Array */ 471#define XM_MD_RX_MCTRL (1L<<12) /* Bit 12: Rx MAC Control Frames */ 472#define XM_MD_RX_RUNT (1L<<11) /* Bit 11: Rx Runt Frames */ 473#define XM_MD_RX_IRLE (1L<<10) /* Bit 10: Rx in Range Len Err F */ 474#define XM_MD_RX_LONG (1L<<9) /* Bit 9: Rx Long Frames */ 475#define XM_MD_RX_CRCE (1L<<8) /* Bit 8: Rx CRC Error Frames */ 476#define XM_MD_RX_ERR (1L<<7) /* Bit 7: Rx Error Frames */ 477#define XM_MD_DIS_UC (1L<<6) /* Bit 6: Disable Rx Unicast */ 478#define XM_MD_DIS_MC (1L<<5) /* Bit 5: Disable Rx Multicast */ 479#define XM_MD_DIS_BC (1L<<4) /* Bit 4: Disable Rx Boradcast */ 480#define XM_MD_ENA_PROM (1L<<3) /* Bit 3: Enable Promiscuous */ 481#define XM_MD_ENA_BE (1L<<2) /* Bit 2: Enable Big Endian */ 482#define XM_MD_FTF (1L<<1) /* Bit 1: (sc) Flush Tx FIFO */ 483#define XM_MD_FRF (1L<<0) /* Bit 0: (sc) Flush Rx FIFO */ 484 485#define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I) 486#define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\ 487 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA) 488 489/* XM_STAT_CMD 16 bit r/w Statistics Command Register */ 490 /* Bit 16..6: reserved */ 491#define XM_SC_SNP_RXC (1<<5) /* Bit 5: (sc) Snap Rx Counters */ 492#define XM_SC_SNP_TXC (1<<4) /* Bit 4: (sc) Snap Tx Counters */ 493#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */ 494#define XM_SC_CP_TXC (1<<2) /* Bit 2: Copy Tx Counters Continuously */ 495#define XM_SC_CLR_RXC (1<<1) /* Bit 1: (sc) Clear Rx Counters */ 496#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */ 497 498 499/* XM_RX_CNT_EV 32 bit ro Rx Counter Event Register */ 500/* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */ 501#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov*/ 502#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov*/ 503#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov*/ 504#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov*/ 505#define XMR_127B_OV (1L<<27) /* Bit 27: 65-127 Byte Rx Cnt Ov */ 506#define XMR_64B_OV (1L<<26) /* Bit 26: 64 Byte Rx Cnt Ov */ 507#define XMR_UTIL_OV (1L<<25) /* Bit 25: Rx Util Cnt Overflow */ 508#define XMR_UTIL_UR (1L<<24) /* Bit 24: Rx Util Cnt Underrun */ 509#define XMR_CEX_ERR_OV (1L<<23) /* Bit 23: CEXT Err Cnt Ov */ 510 /* Bit 22: reserved */ 511#define XMR_FCS_ERR_OV (1L<<21) /* Bit 21: Rx FCS Error Cnt Ov */ 512#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov*/ 513#define XMR_RUNT_OV (1L<<19) /* Bit 19: Runt Event Cnt Ov */ 514#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov*/ 515#define XMR_SYM_ERR_OV (1L<<17) /* Bit 17: Rx Sym Err Cnt Ov */ 516 /* Bit 16: reserved */ 517#define XMR_CAR_ERR_OV (1L<<15) /* Bit 15: Rx Carr Ev Err Cnt Ov */ 518#define XMR_JAB_PKT_OV (1L<<14) /* Bit 14: Rx Jabb Packet Cnt Ov */ 519#define XMR_FIFO_OV (1L<<13) /* Bit 13: Rx FIFO Ov Ev Cnt Ov */ 520#define XMR_FRA_ERR_OV (1L<<12) /* Bit 12: Rx Framing Err Cnt Ov */ 521#define XMR_FMISS_OV (1L<<11) /* Bit 11: Rx Missed Ev Cnt Ov */ 522#define XMR_BURST (1L<<10) /* Bit 10: Rx Burst Event Cnt Ov */ 523#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov*/ 524#define XMR_INV_MP (1L<<8) /* Bit 8: Rx inv Pause Frame Ov */ 525#define XMR_MCTRL_OV (1L<<7) /* Bit 7: Rx MAC Ctrl-F Cnt Ov */ 526#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov*/ 527#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame CntOv*/ 528#define XMR_MC_OK_OV (1L<<4) /* Bit 4: Rx Multicast Cnt Ov */ 529#define XMR_BC_OK_OV (1L<<3) /* Bit 3: Rx Broadcast Cnt Ov */ 530#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low CntOv*/ 531#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK Hi Cnt Ov*/ 532#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received Ok Ov */ 533 534#define XMR_DEF_MSK 0x00000006L /* all bits excepting 1 and 2 */ 535 536/* XM_TX_CNT_EV 32 bit ro Tx Counter Event Register */ 537/* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */ 538 /* Bit 31..26: reserved */ 539#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov*/ 540#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov*/ 541#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov*/ 542#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov*/ 543#define XMT_127B_OV (1L<<21) /* Bit 21: 65-127 Byte Tx Cnt Ov */ 544#define XMT_64B_OV (1L<<20) /* Bit 20: 64 Byte Tx Cnt Ov */ 545#define XMT_UTIL_OV (1L<<19) /* Bit 19: Tx Util Cnt Overflow */ 546#define XMT_UTIL_UR (1L<<18) /* Bit 18: Tx Util Cnt Underrun */ 547#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov*/ 548#define XMT_FIFO_UR_OV (1L<<16) /* Bit 16: Tx FIFO Ur Ev Cnt Ov */ 549#define XMT_EX_DEF_OV (1L<<15) /* Bit 15: Tx Ex Deferall Cnt Ov */ 550#define XMT_DEF (1L<<14) /* Bit 14: Tx Deferred Cnt Ov */ 551#define XMT_LAT_COL_OV (1L<<13) /* Bit 13: Tx Late Col Cnt Ov */ 552#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov*/ 553#define XMT_MUL_COL_OV (1L<<11) /* Bit 11: Tx Mult Col Cnt Ov */ 554#define XMT_SNG_COL (1L<<10) /* Bit 10: Tx Single Col Cnt Ov */ 555#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov*/ 556#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov*/ 557#define XMT_BURST (1L<<7) /* Bit 7: Tx Burst Event Cnt Ov */ 558#define XMT_LONG (1L<<6) /* Bit 6: Tx Long Frame Cnt Ov */ 559#define XMT_UC_OK_OV (1L<<5) /* Bit 5: Tx Unicast Cnt Ov */ 560#define XMT_MC_OK_OV (1L<<4) /* Bit 4: Tx Multicast Cnt Ov */ 561#define XMT_BC_OK_OV (1L<<3) /* Bit 3: Tx Broadcast Cnt Ov */ 562#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low CntOv*/ 563#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK Hi Cnt Ov*/ 564#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx Ok Ov */ 565 566#define XMT_DEF_MSK 0x00000006L /* all bits excepting 1 and 2 */ 567 568/* 569 * Receive Frame Status Encoding 570 */ 571#define XMR_FS_LEN (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */ 572#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: tagged wh 2Lev VLAN ID*/ 573#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: tagged wh 1Lev VLAN ID*/ 574#define XMR_FS_BC (1L<<15) /* Bit 15: Broadcast Frame */ 575#define XMR_FS_MC (1L<<14) /* Bit 14: Multicast Frame */ 576#define XMR_FS_UC (1L<<13) /* Bit 13: Unicast Frame */ 577 /* Bit 12: reserved */ 578#define XMR_FS_BURST (1L<<11) /* Bit 11: Burst Mode */ 579#define XMR_FS_CEX_ERR (1L<<10) /* Bit 10: Carrier Ext. Error */ 580#define XMR_FS_802_3 (1L<<9) /* Bit 9: 802.3 Frame */ 581#define XMR_FS_COL_ERR (1L<<8) /* Bit 8: Collision Error */ 582#define XMR_FS_CAR_ERR (1L<<7) /* Bit 7: Carrier Event Error */ 583#define XMR_FS_LEN_ERR (1L<<6) /* Bit 6: In-Range Length Error */ 584#define XMR_FS_FRA_ERR (1L<<5) /* Bit 5: Framing Error */ 585#define XMR_FS_RUNT (1L<<4) /* Bit 4: Runt Error */ 586#define XMR_FS_LNG_ERR (1L<<3) /* Bit 3: Gaint Error */ 587#define XMR_FS_FCS_ERR (1L<<2) /* Bit 2: Frame Check Sequ Err */ 588#define XMR_FS_ERR (1L<<1) /* Bit 1: Frame Error */ 589#define XMR_FS_MCTRL (1L<<0) /* Bit 0: MAC Control Packet */ 590 591/* 592 * XMR_FS_ERR will be set if 593 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT, 594 * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR 595 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue 596 * XMR_FS_ERR unless the corresponding bit in the Receive Command 597 * Register is set. 598 */ 599#define XMR_FS_ANY_ERR XMR_FS_ERR 600 601/*----------------------------------------------------------------------------*/ 602/* 603 * XMAC-PHY Registers, indirect addressed over the XMAC 604 */ 605#define PHY_XMAC_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 606#define PHY_XMAC_STAT 0x01 /* 16 bit r/w PHY Status Register */ 607#define PHY_XMAC_ID0 0x02 /* 16 bit ro PHY ID0 Register */ 608#define PHY_XMAC_ID1 0x03 /* 16 bit ro PHY ID1 Register */ 609#define PHY_XMAC_AUNE_ADV 0x04 /* 16 bit r/w Autoneg Advertisement */ 610#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit ro Link Partner Abi Reg */ 611#define PHY_XMAC_AUNE_EXP 0x06 /* 16 bit ro Autoneg Expansion Reg */ 612#define PHY_XMAC_NEPG 0x07 /* 16 bit r/w Next Page Register */ 613#define PHY_XMAC_NEPG_LP 0x08 /* 16 bit ro Next Page Link P Reg */ 614 /* 0x09 - 0x0e: reserved */ 615#define PHY_XMAC_EXT_STAT 0x0f /* 16 bit ro Ext Status Register */ 616#define PHY_XMAC_RES_ABI 0x10 /* 16 bit ro PHY Resolved Ability */ 617 618/*----------------------------------------------------------------------------*/ 619/* 620 * Broadcom-PHY Registers, indirect addressed over XMAC 621 */ 622#define PHY_BCOM_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 623#define PHY_BCOM_STAT 0x01 /* 16 bit ro PHY Status Register */ 624#define PHY_BCOM_ID0 0x02 /* 16 bit ro PHY ID0 Register */ 625#define PHY_BCOM_ID1 0x03 /* 16 bit ro PHY ID1 Register */ 626#define PHY_BCOM_AUNE_ADV 0x04 /* 16 bit r/w Autoneg Advertisement */ 627#define PHY_BCOM_AUNE_LP 0x05 /* 16 bit ro Link Part Ability Reg */ 628#define PHY_BCOM_AUNE_EXP 0x06 /* 16 bit ro Autoneg Expansion Reg */ 629#define PHY_BCOM_NEPG 0x07 /* 16 bit r/w Next Page Register */ 630#define PHY_BCOM_NEPG_LP 0x08 /* 16 bit ro Next Page Link P Reg */ 631 /* Broadcom-specific registers */ 632#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */ 633#define PHY_BCOM_1000T_STAT 0x0a /* 16 bit ro 1000Base-T Status Reg */ 634 /* 0x0b - 0x0e: reserved */ 635#define PHY_BCOM_EXT_STAT 0x0f /* 16 bit ro Extended Status Reg */ 636#define PHY_BCOM_P_EXT_CTRL 0x10 /* 16 bit r/w PHY Extended Ctrl Reg */ 637#define PHY_BCOM_P_EXT_STAT 0x11 /* 16 bit ro PHY Extended Stat Reg */ 638#define PHY_BCOM_RE_CTR 0x12 /* 16 bit r/w Receive Error Counter */ 639#define PHY_BCOM_FC_CTR 0x13 /* 16 bit r/w False Carr Sense Cnt */ 640#define PHY_BCOM_RNO_CTR 0x14 /* 16 bit r/w Receiver NOT_OK Cnt */ 641 /* 0x15 - 0x17: reserved */ 642#define PHY_BCOM_AUX_CTRL 0x18 /* 16 bit r/w Auxiliary Control Reg */ 643#define PHY_BCOM_AUX_STAT 0x19 /* 16 bit ro Auxiliary Stat Summary*/ 644#define PHY_BCOM_INT_STAT 0x1a /* 16 bit ro Interrupt Status Reg */ 645#define PHY_BCOM_INT_MASK 0x1b /* 16 bit r/w Interrupt Mask Reg */ 646 /* 0x1c: reserved */ 647 /* 0x1d - 0x1f: test registers */ 648 649/*----------------------------------------------------------------------------*/ 650/* 651 * Level One-PHY Registers, indirect addressed over XMAC 652 */ 653#define PHY_LONE_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 654#define PHY_LONE_STAT 0x01 /* 16 bit ro PHY Status Register */ 655#define PHY_LONE_ID0 0x02 /* 16 bit ro PHY ID0 Register */ 656#define PHY_LONE_ID1 0x03 /* 16 bit ro PHY ID1 Register */ 657#define PHY_LONE_AUNE_ADV 0x04 /* 16 bit r/w Autoneg Advertisement */ 658#define PHY_LONE_AUNE_LP 0x05 /* 16 bit ro Link Part Ability Reg */ 659#define PHY_LONE_AUNE_EXP 0x06 /* 16 bit ro Autoneg Expansion Reg */ 660#define PHY_LONE_NEPG 0x07 /* 16 bit r/w Next Page Register */ 661#define PHY_LONE_NEPG_LP 0x08 /* 16 bit ro Next Page Link Partner*/ 662 /* Level One-specific registers */ 663#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg*/ 664#define PHY_LONE_1000T_STAT 0x0a /* 16 bit ro 1000Base-T Status Reg */ 665 /* 0x0b -0x0e: reserved */ 666#define PHY_LONE_EXT_STAT 0x0f /* 16 bit ro Extended Status Reg */ 667#define PHY_LONE_PORT_CFG 0x10 /* 16 bit r/w Port Configuration Reg*/ 668#define PHY_LONE_Q_STAT 0x11 /* 16 bit ro Quick Status Reg */ 669#define PHY_LONE_INT_ENAB 0x12 /* 16 bit r/w Interrupt Enable Reg */ 670#define PHY_LONE_INT_STAT 0x13 /* 16 bit ro Interrupt Status Reg */ 671#define PHY_LONE_LED_CFG 0x14 /* 16 bit r/w LED Configuration Reg */ 672#define PHY_LONE_PORT_CTRL 0x15 /* 16 bit r/w Port Control Reg */ 673#define PHY_LONE_CIM 0x16 /* 16 bit ro CIM Reg */ 674 /* 0x17 -0x1c: reserved */ 675 676/*----------------------------------------------------------------------------*/ 677/* 678 * National-PHY Registers, indirect addressed over XMAC 679 */ 680#define PHY_NAT_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 681#define PHY_NAT_STAT 0x01 /* 16 bit r/w PHY Status Register */ 682#define PHY_NAT_ID0 0x02 /* 16 bit ro PHY ID0 Register */ 683#define PHY_NAT_ID1 0x03 /* 16 bit ro PHY ID1 Register */ 684#define PHY_NAT_AUNE_ADV 0x04 /* 16 bit r/w Autonegotiation Advertisement */ 685#define PHY_NAT_AUNE_LP 0x05 /* 16 bit ro Link Partner Ability Reg */ 686#define PHY_NAT_AUNE_EXP 0x06 /* 16 bit ro Autonegotiation Expansion Reg */ 687#define PHY_NAT_NEPG 0x07 /* 16 bit r/w Next Page Register */ 688#define PHY_NAT_NEPG_LP 0x08 /* 16 bit ro Next Page Link Partner Reg */ 689 /* National-specific registers */ 690#define PHY_NAT_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ 691#define PHY_NAT_1000T_STAT 0x0a /* 16 bit ro 1000Base-T Status Reg */ 692 /* 0x0b -0x0e: reserved */ 693#define PHY_NAT_EXT_STAT 0x0f /* 16 bit ro Extended Status Register */ 694#define PHY_NAT_EXT_CTRL1 0x10 /* 16 bit ro Extended Control Reg1 */ 695#define PHY_NAT_Q_STAT1 0x11 /* 16 bit ro Quick Status Reg1 */ 696#define PHY_NAT_10B_OP 0x12 /* 16 bit ro 10Base-T Operations Reg */ 697#define PHY_NAT_EXT_CTRL2 0x13 /* 16 bit ro Extended Control Reg1 */ 698#define PHY_NAT_Q_STAT2 0x14 /* 16 bit ro Quick Status Reg2 */ 699 /* 0x15 -0x18: reserved */ 700#define PHY_NAT_PHY_ADDR 0x19 /* 16 bit ro PHY Address Register */ 701 702 703/*----------------------------------------------------------------------------*/ 704 705/* 706 * PHY bit definitions 707 * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are 708 * Xmac/Broadcom/LevelOne/National-specific. 709 * All other are general. 710 */ 711 712/***** PHY_XMAC_CTRL 16 bit r/w PHY Control Register *****/ 713/***** PHY_BCOM_CTRL 16 bit r/w PHY Control Register *****/ 714/***** PHY_LONE_CTRL 16 bit r/w PHY Control Register *****/ 715#define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY releated regs */ 716#define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ 717#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */ 718#define PHY_CT_ANE (1<<12) /* Bit 12: Autonegotiation Enabled */ 719#define PHY_CT_PDOWN (1<<11) /* Bit 11: (BC,L1) Power Down Mode */ 720#define PHY_CT_ISOL (1<<10) /* Bit 10: (BC,L1) Isolate Mode */ 721#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Autonegotiation */ 722#define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ 723#define PHY_CT_COL_TST (1<<7) /* Bit 7: (BC,L1) Collsion Test enabled */ 724#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: (BC,L1) Speed select, upper bit */ 725 /* Bit 5..0: reserved */ 726 727#define PHY_B_CT_SP1000 (1<<6) /* Bit 6: enable speed of 1000 MBit/s */ 728#define PHY_B_CT_SP100 (1<<13) /* Bit 13: enable speed of 100 MBit/s */ 729#define PHY_B_CT_SP10 (0) /* Bit 6/13 not set, speed of 10 MBit/s */ 730 731#define PHY_L_CT_SP1000 (1<<6) /* Bit 6: enable speed of 1000 MBit/s */ 732#define PHY_L_CT_SP100 (1<<13) /* Bit 13: enable speed of 100 MBit/s */ 733#define PHY_L_CT_SP10 (0) /* Bit 6/13 not set, speed of 10 MBit/s */ 734 735 736/***** PHY_XMAC_STAT 16 bit r/w PHY Status Register *****/ 737/***** PHY_BCOM_STAT 16 bit r/w PHY Status Register *****/ 738/***** PHY_LONE_STAT 16 bit r/w PHY Status Register *****/ 739 /* Bit 15..9: reserved */ 740 /* (BC/L1) 100/10 MBit/s cap bits ignored*/ 741#define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ 742 /* Bit 7: reserved */ 743#define PHY_ST_PRE_SUB (1<<6) /* Bit 6: (BC/L1) preamble suppression */ 744#define PHY_ST_AN_OVER (1<<5) /* Bit 5: Autonegotiation Over */ 745#define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remode Fault Condition Occured*/ 746#define PHY_ST_AN_CAP (1<<3) /* Bit 3: Autonegotiation Capability */ 747#define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ 748#define PHY_ST_JAP_DET (1<<1) /* Bit 1: (BC/L1) Japper Detected */ 749#define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ 750 751 752/* PHY_XMAC_ID1 16 bit ro PHY ID1 Register */ 753/* PHY_BCOM_ID1 16 bit ro PHY ID1 Register */ 754/* PHY_LONE_ID1 16 bit ro PHY ID1 Register */ 755#define PHY_I1_OUI (0x3f<<10) /* Bit 15..10: Organiz. Unique ID */ 756#define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ 757#define PHY_I1_REV (0x0f<<0) /* Bit 3.. 0: Revision Number */ 758 759 760/***** PHY_XMAC_AUNE_ADV 16 bit r/w Autoneg Advertisement *****/ 761/***** PHY_XMAC_AUNE_LP 16 bit ro Link Partner Ability Reg *****/ 762#define PHY_AN_NXT_PG (1<<15) /* Bit 15: Request Next Page */ 763#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */ 764#define PHY_X_AN_RFB (3<<12) /* Bit 13..12: Remode Fault Bits */ 765 /* Bit 11.. 9: reserved */ 766#define PHY_X_AN_PAUSE (3<<7) /* Bit 8.. 7: Pause Bits */ 767#define PHY_X_AN_HD (1<<6) /* Bit 6: Half Duplex */ 768#define PHY_X_AN_FD (1<<5) /* Bit 5: Full Duplex */ 769 /* Bit 4.. 0: reserved */ 770 771/***** PHY_BCOM_AUNE_ADV 16 bit r/w Autoneg Advertisement *****/ 772/***** PHY_BCOM_AUNE_LP 16 bit ro Link Partner Ability Reg *****/ 773/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */ 774 /* Bit 14: reserved */ 775#define PHY_B_AN_RF (1<<13) /* Bit 13: Remote Fault */ 776 /* Bit 12: reserved */ 777#define PHY_B_AN_ASP (1<<11) /* Bit 11: Asymetric Pause */ 778#define PHY_B_AN_PC (1<<10) /* Bit 10: Pause Capable */ 779 /* Bit 9..5: 100/10 BT cap bits ingnored */ 780#define PHY_B_AN_SEL (0x1f<<0)/* Bit 4..0: Selector Field, 00001=Ethernet*/ 781 782/***** PHY_LONE_AUNE_ADV 16 bit r/w Autoneg Advertisement *****/ 783/***** PHY_LONE_AUNE_LP 16 bit ro Link Partner Ability Reg *****/ 784/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */ 785 /* Bit 14: reserved */ 786#define PHY_L_AN_RF (1<<13) /* Bit 13: Remote Fault */ 787 /* Bit 12: reserved */ 788#define PHY_L_AN_ASP (1<<11) /* Bit 11: Asymetric Pause */ 789#define PHY_L_AN_PC (1<<10) /* Bit 10: Pause Capable */ 790 /* Bit 9..5: 100/10 BT cap bits ingnored */ 791#define PHY_L_AN_SEL (0x1f<<0)/* Bit 4..0: Selector Field, 00001=Ethernet*/ 792 793/***** PHY_NAT_AUNE_ADV 16 bit r/w Autoneg Advertisement *****/ 794/***** PHY_NAT_AUNE_LP 16 bit ro Link Partner Ability Reg *****/ 795/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */ 796 /* Bit 14: reserved */ 797#define PHY_N_AN_RF (1<<13) /* Bit 13: Remote Fault */ 798 /* Bit 12: reserved */ 799#define PHY_N_AN_100F (1<<11) /* Bit 11: 100Base-T2 FD Support */ 800#define PHY_N_AN_100H (1<<10) /* Bit 10: 100Base-T2 HD Support */ 801 /* Bit 9..5: 100/10 BT cap bits ingnored */ 802#define PHY_N_AN_SEL (0x1f<<0)/* Bit 4..0: Selector Field, 00001=Ethernet*/ 803 804/* field type definition for PHY_x_AN_SEL */ 805#define PHY_SEL_TYPE 0x01 /* 00001 = Ethernet */ 806 807/***** PHY_XMAC_AUNE_EXP 16 bit ro Autoneg Expansion Reg *****/ 808 /* Bit 15..4: reserved */ 809#define PHY_AN_LP_NP (1<<3) /* Bit 3: Link Partner can Next Page */ 810#define PHY_AN_LOC_NP (1<<2) /* Bit 2: Local PHY can Next Page */ 811#define PHY_AN_RX_PG (1<<1) /* Bit 1: Page Received */ 812 /* Bit 0: reserved */ 813 814/***** PHY_BCOM_AUNE_EXP 16 bit ro Autoneg Expansion Reg *****/ 815 /* Bit 15..5: reserved */ 816#define PHY_B_AN_PDF (1<<4) /* Bit 4: Parallel Detection Fault */ 817/* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */ 818/* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */ 819/* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */ 820#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Autoneg Cap. */ 821 822/***** PHY_LONE_AUNE_EXP 16 bit ro Autoneg Expansion Reg *****/ 823#define PHY_L_AN_BP (1<<5) /* Bit 5: Base Page Indication */ 824#define PHY_L_AN_PDF (1<<4) /* Bit 4: Parallel Detection Fault */ 825/* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */ 826/* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */ 827/* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */ 828#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Autoneg Cap. */ 829 830 831/***** PHY_XMAC_NEPG 16 bit r/w Next Page Register *****/ 832/***** PHY_BCOM_NEPG 16 bit r/w Next Page Register *****/ 833/***** PHY_LONE_NEPG 16 bit r/w Next Page Register *****/ 834/***** PHY_XMAC_NEPG_LP 16 bit ro Next Page Link Partner *****/ 835/***** PHY_BCOM_NEPG_LP 16 bit ro Next Page Link Partner *****/ 836/***** PHY_LONE_NEPG_LP 16 bit ro Next Page Link Partner *****/ 837#define PHY_NP_MORE (1<<15) /* Bit 15: More, Next Pages to follow */ 838#define PHY_NP_ACK1 (1<<14) /* Bit 14: (ro) Ack 1, for receiving a message*/ 839#define PHY_NP_MSG_VAL (1<<13) /* Bit 13: Message Page valid */ 840#define PHY_NP_ACK2 (1<<12) /* Bit 12: Ack 2, comply with msg content*/ 841#define PHY_NP_TOG (1<<11) /* Bit 11: Toggle Bit, ensure sync */ 842#define PHY_NP_MSG 0x07ff /* Bit 10..0: Message from/to Link Partner */ 843 844/* 845 * XMAC-Specific 846 */ 847/***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/ 848#define PHY_X_EX_FD (1<<15) /* Bit 15: Device Supports Full Duplex */ 849#define PHY_X_EX_HD (1<<14) /* Bit 14: Device Supports Half Duplex */ 850 /* Bit 13..0: reserved */ 851 852/***** PHY_XMAC_RES_ABI 16 bit ro PHY Resolved Ability *****/ 853 /* Bit 15..9: reserved */ 854#define PHY_X_RS_PAUSE (3<<7) /* Bit 8..7: selected Pause Mode */ 855#define PHY_X_RS_HD (1<<6) /* Bit 6: Half Duplex Mode selected */ 856#define PHY_X_RS_FD (1<<5) /* Bit 5: Full Duplex Mode selected */ 857#define PHY_X_RS_ABLMIS (1<<4) /* Bit 4: duplex or pause cap mismatch */ 858#define PHY_X_RS_PAUMIS (1<<3) /* Bit 3: pause capability missmatch */ 859 /* Bit 2..0: reserved */ 860/* 861 * Remote Fault Bits (PHY_X_AN_RFB) encoding 862 */ 863#define X_RFB_OK (0<<12) /* Bit 12..13 No errors, Link OK */ 864#define X_RFB_LF (1<<12) /* Bit 12..13 Link Failure */ 865#define X_RFB_OFF (2<<12) /* Bit 12..13 Offline */ 866#define X_RFB_AN_ERR (3<<12) /* Bit 12..13 Autonegotiation Error */ 867 868/* 869 * Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding 870 */ 871#define PHY_X_P_NO_PAUSE (0<<7) /* Bit 8..7: no Pause Mode */ 872#define PHY_X_P_SYM_MD (1<<7) /* Bit 8..7: symmetric Pause Mode */ 873#define PHY_X_P_ASYM_MD (2<<7) /* Bit 8..7: asymmetric Pause Mode */ 874#define PHY_X_P_BOTH_MD (3<<7) /* Bit 8..7: both Pause Mode */ 875 876 877/* 878 * Broadcom-Specific 879 */ 880/***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 881#define PHY_B_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 882#define PHY_B_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */ 883#define PHY_B_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */ 884#define PHY_B_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */ 885#define PHY_B_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ 886#define PHY_B_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ 887 /* Bit 7..0: reserved */ 888 889/***** PHY_BCOM_1000T_STAT 16 bit ro 1000Base-T Status Reg *****/ 890#define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ 891#define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ 892#define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ 893#define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ 894#define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ 895#define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ 896 /* Bit 9..8: reserved */ 897#define PHY_B_1000S_IEC (255<<0)/* Bit 7..0: Idle Error Count */ 898 899/***** PHY_BCOM_EXT_STAT 16 bit ro Extended Status Register *****/ 900#define PHY_B_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */ 901#define PHY_B_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */ 902#define PHY_B_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */ 903#define PHY_B_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */ 904 /* Bit 11..0: reserved */ 905 906/***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/ 907#define PHY_B_PEC_MAC_PHY (1<<15) /* Bit 15: 10BIT/GMI-Interface */ 908#define PHY_B_PEC_DIS_CROSS (1<<14) /* Bit 14: Disable MDI Crossover */ 909#define PHY_B_PEC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */ 910#define PHY_B_PEC_INT_DIS (1<<12) /* Bit 12: Interrupts Disabled */ 911#define PHY_B_PEC_F_INT (1<<11) /* Bit 11: Force Interrupt */ 912#define PHY_B_PEC_BY_45 (1<<10) /* Bit 10: Bypass 4B5B-Decoder */ 913#define PHY_B_PEC_BY_SCR (1<<9) /* Bit 9: Bypass Scrambler */ 914#define PHY_B_PEC_BY_MLT3 (1<<8) /* Bit 8: Bypass MLT3 Encoder */ 915#define PHY_B_PEC_BY_RXA (1<<7) /* Bit 7: Bypass Rx Alignm. */ 916#define PHY_B_PEC_RES_SCR (1<<6) /* Bit 6: Reset Scrambler */ 917#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Ena LED Traffic Mode */ 918#define PHY_B_PEC_LED_ON (1<<4) /* Bit 4: Force LED's on */ 919#define PHY_B_PEC_LED_OFF (1<<3) /* Bit 3: Force LED's off */ 920#define PHY_B_PEC_EX_IPG (1<<2) /* Bit 2: Extend Tx IPG Mode */ 921#define PHY_B_PEC_3_LED (1<<1) /* Bit 1: Three Link LED mode */ 922#define PHY_B_PEC_HIGH_LA (1<<0) /* Bit 0: GMII Fifo Elasticy */ 923 924/***** PHY_BCOM_P_EXT_STAT 16 bit ro PHY Extended Status Reg *****/ 925 /* Bit 15..14: reserved */ 926#define PHY_B_PES_CROSS_STAT (1<<13) /* Bit 13: MDI Crossover Status */ 927#define PHY_B_PES_INT_STAT (1<<12) /* Bit 12: Interrupt Status */ 928#define PHY_B_PES_RRS (1<<11) /* Bit 11: Remote Receiver Stat. */ 929#define PHY_B_PES_LRS (1<<10) /* Bit 10: Local Receiver Stat. */ 930#define PHY_B_PES_LOCKED (1<<9) /* Bit 9: Locked */ 931#define PHY_B_PES_LS (1<<8) /* Bit 8: Link Status */ 932#define PHY_B_PES_RF (1<<7) /* Bit 7: Remote Fault */ 933#define PHY_B_PES_CE_ER (1<<6) /* Bit 6: Carrier Ext Error */ 934#define PHY_B_PES_BAD_SSD (1<<5) /* Bit 5: Bad SSD */ 935#define PHY_B_PES_BAD_ESD (1<<4) /* Bit 4: Bad ESD */ 936#define PHY_B_PES_RX_ER (1<<3) /* Bit 3: Receive Error */ 937#define PHY_B_PES_TX_ER (1<<2) /* Bit 2: Transmit Error */ 938#define PHY_B_PES_LOCK_ER (1<<1) /* Bit 1: Lock Error */ 939#define PHY_B_PES_MLT3_ER (1<<0) /* Bit 0: MLT3 code Error */ 940 941/***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/ 942 /* Bit 15..8: reserved */ 943#define PHY_B_FC_CTR (255<<0)/* Bit 7..0: False Carrier Counter */ 944 945/***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/ 946#define PHY_B_RC_LOC (255<<8)/* Bit 15..8: Local Rx NOT_OK cnt */ 947#define PHY_B_RC_REM (255<<0)/* Bit 7..0: Remote Rx NOT_OK cnt */ 948 949/***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/ 950#define PHY_B_AC_L_SQE (1<<15) /* Bit 15: Low Squelch */ 951#define PHY_B_AC_LONG_PACK (1<<14) /* Bit 14: Rx Long Packets */ 952#define PHY_B_AC_ER_CTRL (3<<12) /* Bit 13..12: Edgerate Control */ 953 /* Bit 11: reserved */ 954#define PHY_B_AC_TX_TST (1<<10) /* Bit 10: tx test bit, always 1 */ 955 /* Bit 9.. 8: reserved */ 956#define PHY_B_AC_DIS_PRF (1<<7) /* Bit 7: dis part resp filter */ 957 /* Bit 6: reserved */ 958#define PHY_B_AC_DIS_PM (1<<5) /* Bit 5: dis power management */ 959 /* Bit 4: reserved */ 960#define PHY_B_AC_DIAG (1<<3) /* Bit 3: Diagnostic Mode */ 961 /* Bit 2.. 0: reserved */ 962 963/***** PHY_BCOM_AUX_STAT 16 bit ro Auxiliary Status Reg *****/ 964#define PHY_B_AS_AN_C (1<<15) /* Bit 15: AutoNeg complete */ 965#define PHY_B_AS_AN_CA (1<<14) /* Bit 14: AN Complete Ack */ 966#define PHY_B_AS_ANACK_D (1<<13) /* Bit 13: AN Ack Detect */ 967#define PHY_B_AS_ANAB_D (1<<12) /* Bit 12: AN Ability Detect */ 968#define PHY_B_AS_NPW (1<<11) /* Bit 11: AN Next Page Wait */ 969#define PHY_B_AS_AN_RES (7<<8) /* Bit 10..8: AN HDC */ 970#define PHY_B_AS_PDF (1<<7) /* Bit 7: Parallel Detect. Fault*/ 971#define PHY_B_AS_RF (1<<6) /* Bit 6: Remote Fault */ 972#define PHY_B_AS_ANP_R (1<<5) /* Bit 5: AN Page Received */ 973#define PHY_B_AS_LP_ANAB (1<<4) /* Bit 4: LP AN Ability */ 974#define PHY_B_AS_LP_NPAB (1<<3) /* Bit 3: LP Next Page Ability */ 975#define PHY_B_AS_LS (1<<2) /* Bit 2: Link Status */ 976#define PHY_B_AS_PRR (1<<1) /* Bit 1: Pause Resolution-Rx */ 977#define PHY_B_AS_PRT (1<<0) /* Bit 0: Pause Resolution-Tx */ 978 979/***** PHY_BCOM_INT_STAT 16 bit ro Interrupt Status Reg *****/ 980/***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ 981 /* Bit 15: reserved */ 982#define PHY_B_IS_PSE (1<<14) /* Bit 14: Pair Swap Error */ 983#define PHY_B_IS_MDXI_SC (1<<13) /* Bit 13: MDIX Status Change */ 984#define PHY_B_IS_HCT (1<<12) /* Bit 12: counter above 32k */ 985#define PHY_B_IS_LCT (1<<11) /* Bit 11: counter above 128 */ 986#define PHY_B_IS_AN_PR (1<<10) /* Bit 10: Page Received */ 987#define PHY_B_IS_NO_HDCL (1<<9) /* Bit 9: No HCD Link */ 988#define PHY_B_IS_NO_HDC (1<<8) /* Bit 8: No HCD */ 989#define PHY_B_IS_NEG_USHDC (1<<7) /* Bit 7: Negotiated Unsup. HCD */ 990#define PHY_B_IS_SCR_S_ER (1<<6) /* Bit 6: Scrambler Sync Error */ 991#define PHY_B_IS_RRS_CHANGE (1<<5) /* Bit 5: Remote Rx Stat Change */ 992#define PHY_B_IS_LRS_CHANGE (1<<4) /* Bit 4: Local Rx Stat Change */ 993#define PHY_B_IS_DUP_CHANGE (1<<3) /* Bit 3: Duplex Mode Change */ 994#define PHY_B_IS_LSP_CHANGE (1<<2) /* Bit 2: Link Speed Change */ 995#define PHY_B_IS_LST_CHANGE (1<<1) /* Bit 1: Link Status Changed */ 996#define PHY_B_IS_CRC_ER (1<<0) /* Bit 0: CRC Error */ 997 998#define PHY_B_DEF_MSK (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) 999 1000/* 1001 * Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding 1002 */ 1003#define PHY_B_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */ 1004#define PHY_B_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */ 1005#define PHY_B_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */ 1006#define PHY_B_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */ 1007 1008/* 1009 * Resolved Duplex mode and Capabilities (Aux Status Summary Reg) 1010 */ 1011#define PHY_B_RES_1000FD (7<<8) /* Bit 10..8: 1000Base-T Full Dup. */ 1012#define PHY_B_RES_1000HD (6<<8) /* Bit 10..8: 1000Base-T Half Dup. */ 1013/* others: 100/10: invalid for us */ 1014 1015/* 1016 * Level One-Specific 1017 */ 1018/***** PHY_LONE_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1019#define PHY_L_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 1020#define PHY_L_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */ 1021#define PHY_L_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */ 1022#define PHY_L_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */ 1023#define PHY_L_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ 1024#define PHY_L_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ 1025 /* Bit 7..0: reserved */ 1026 1027/***** PHY_LONE_1000T_STAT 16 bit ro 1000Base-T Status Reg *****/ 1028#define PHY_L_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ 1029#define PHY_L_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ 1030#define PHY_L_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ 1031#define PHY_L_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status*/ 1032#define PHY_L_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ 1033#define PHY_L_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ 1034 /* Bit 9..8: reserved */ 1035#define PHY_B_1000S_IEC (255<<0)/* Bit 7..0: Idle Error Count */ 1036 1037/***** PHY_LONE_EXT_STAT 16 bit ro Extended Status Register *****/ 1038#define PHY_L_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */ 1039#define PHY_L_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */ 1040#define PHY_L_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */ 1041#define PHY_L_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */ 1042 /* Bit 11..0: reserved */ 1043 1044/***** PHY_LONE_PORT_CFG 16 bit r/w Port Configuration Reg *****/ 1045#define PHY_L_PC_REP_MODE (1<<15) /* Bit 15: Repeater Mode */ 1046 /* Bit 14: reserved */ 1047#define PHY_L_PC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */ 1048#define PHY_L_PC_BY_SCR (1<<12) /* Bit 12: Bypass Scrambler */ 1049#define PHY_L_PC_BY_45 (1<<11) /* Bit 11: Bypass 4B5B-Decoder */ 1050#define PHY_L_PC_JAB_DIS (1<<10) /* Bit 10: Jabber Disabled */ 1051#define PHY_L_PC_SQE (1<<9) /* Bit 9: Enable Heartbeat */ 1052#define PHY_L_PC_TP_LOOP (1<<8) /* Bit 8: TP Loopback */ 1053#define PHY_L_PC_SSS (1<<7) /* Bit 7: Smart Speed Selection */ 1054#define PHY_L_PC_FIFO_SIZE (1<<6) /* Bit 6: FIFO Size */ 1055#define PHY_L_PC_PRE_EN (1<<5) /* Bit 5: Preamble Enable */ 1056#define PHY_L_PC_CIM (1<<4) /* Bit 4: Carrier Integrity Mon */ 1057#define PHY_L_PC_10_SER (1<<3) /* Bit 3: Use Serial Output */ 1058#define PHY_L_PC_ANISOL (1<<2) /* Bit 2: Unisolate Port */ 1059#define PHY_L_PC_TEN_BIT (1<<1) /* Bit 1: 10bit iface mode on */ 1060#define PHY_L_PC_ALTCLOCK (1<<0) /* Bit 0: (ro) ALTCLOCK Mode on */ 1061 1062/***** PHY_LONE_Q_STAT 16 bit ro Quick Status Reg *****/ 1063#define PHY_L_QS_D_RATE (3<<14) /* Bit 15..14: Data Rate */ 1064#define PHY_L_QS_TX_STAT (1<<13) /* Bit 13: Transmitting */ 1065#define PHY_L_QS_RX_STAT (1<<12) /* Bit 12: Receiving */ 1066#define PHY_L_QS_COL_STAT (1<<11) /* Bit 11: Collision */ 1067#define PHY_L_QS_L_STAT (1<<10) /* Bit 10: Link is up */ 1068#define PHY_L_QS_DUP_MOD (1<<9) /* Bit 9: Full/Half Duplex */ 1069#define PHY_L_QS_AN (1<<8) /* Bit 8: AutoNeg is On */ 1070#define PHY_L_QS_AN_C (1<<7) /* Bit 7: AN is Complete */ 1071#define PHY_L_QS_LLE (7<<4) /* Bit 6: Line Length Estim. */ 1072#define PHY_L_QS_PAUSE (1<<3) /* Bit 3: LP advertised Pause */ 1073#define PHY_L_QS_AS_PAUSE (1<<2) /* Bit 2: LP adv. asym. Pause */ 1074#define PHY_L_QS_ISOLATE (1<<1) /* Bit 1: CIM Isolated */ 1075#define PHY_L_QS_EVENT (1<<0) /* Bit 0: Event has occurred */ 1076 1077/***** PHY_LONE_INT_ENAB 16 bit r/w Interrupt Enable Reg *****/ 1078/***** PHY_LONE_INT_STAT 16 bit ro Interrupt Status Reg *****/ 1079 /* Bit 15..14: reserved */ 1080#define PHY_L_IS_AN_F (1<<13) /* Bit 13: Autoneg fault */ 1081 /* Bit 12: not described */ 1082#define PHY_L_IS_CROSS (1<<11) /* Bit 11: Crossover used */ 1083#define PHY_L_IS_POL (1<<10) /* Bit 10: Polarity correct. used*/ 1084#define PHY_L_IS_SS (1<<9) /* Bit 9: Smart Speed Downgrade*/ 1085#define PHY_L_IS_CFULL (1<<8) /* Bit 8: Counter Full */ 1086#define PHY_L_IS_AN_C (1<<7) /* Bit 7: AutoNeg Complete */ 1087#define PHY_L_IS_SPEED (1<<6) /* Bit 6: Speed Changed */ 1088#define PHY_L_IS_DUP (1<<5) /* Bit 5: Duplex Changed */ 1089#define PHY_L_IS_LS (1<<4) /* Bit 4: Link Status Changed */ 1090#define PHY_L_IS_ISOL (1<<3) /* Bit 3: Isolate Occured */ 1091#define PHY_L_IS_MDINT (1<<2) /* Bit 2: (ro) STAT: MII Int Pending */ 1092#define PHY_L_IS_INTEN (1<<1) /* Bit 1: ENAB: Enable IRQs */ 1093#define PHY_L_IS_FORCE (1<<0) /* Bit 0: ENAB: Force Interrupt */ 1094 1095/* int. mask */ 1096#define PHY_L_DEF_MSK (PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN) 1097 1098/***** PHY_LONE_LED_CFG 16 bit r/w LED Configuration Reg *****/ 1099#define PHY_L_LC_LEDC (3<<14) /* Bit 15..14: Col/Blink/On/Off */ 1100#define PHY_L_LC_LEDR (3<<12) /* Bit 13..12: Rx/Blink/On/Off */ 1101#define PHY_L_LC_LEDT (3<<10) /* Bit 11..10: Tx/Blink/On/Off */ 1102#define PHY_L_LC_LEDG (3<<8) /* Bit 9..8: Giga/Blink/On/Off */ 1103#define PHY_L_LC_LEDS (3<<6) /* Bit 7..6: 10-100/Blink/On/Off */ 1104#define PHY_L_LC_LEDL (3<<4) /* Bit 5..4: Link/Blink/On/Off */ 1105#define PHY_L_LC_LEDF (3<<2) /* Bit 3..2: Duplex/Blink/On/Off */ 1106#define PHY_L_LC_PSTRECH (1<<1) /* Bit 1: Strech LED Pulses */ 1107#define PHY_L_LC_FREQ (1<<0) /* Bit 0: 30/100 ms */ 1108 1109/***** PHY_LONE_PORT_CTRL 16 bit r/w Port Control Reg *****/ 1110#define PHY_L_PC_TX_TCLK (1<<15) /* Bit 15: Enable TX_TCLK */ 1111 /* Bit 14: reserved */ 1112#define PHY_L_PC_ALT_NP (1<<13) /* Bit 14: Alternate Next Page */ 1113#define PHY_L_PC_GMII_ALT (1<<12) /* Bit 13: Alternate GMII driver */ 1114 /* Bit 11: reserved */ 1115#define PHY_L_PC_TEN_CRS (1<<10) /* Bit 10: Extend CRS*/ 1116 /* Bit 9..0: not described */ 1117 1118/***** PHY_LONE_CIM 16 bit ro CIM Reg *****/ 1119#define PHY_L_CIM_ISOL (255<<8)/* Bit 15..8: Isolate Count */ 1120#define PHY_L_CIM_FALSE_CAR (255<<0)/* Bit 7..0: False Carrier Count */ 1121 1122 1123/* 1124 * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding 1125 */ 1126#define PHY_L_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */ 1127#define PHY_L_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */ 1128#define PHY_L_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */ 1129#define PHY_L_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */ 1130 1131 1132/* 1133 * National-Specific 1134 */ 1135/***** PHY_NAT_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1136#define PHY_N_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 1137#define PHY_N_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */ 1138#define PHY_N_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */ 1139#define PHY_N_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */ 1140#define PHY_N_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ 1141#define PHY_N_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ 1142#define PHY_N_1000C_APC (1<<7) /* Bit 7: Asymetric Pause Cap. */ 1143 /* Bit 6..0: reserved */ 1144 1145/***** PHY_NAT_1000T_STAT 16 bit ro 1000Base-T Status Reg *****/ 1146#define PHY_N_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ 1147#define PHY_N_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ 1148#define PHY_N_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ 1149#define PHY_N_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status*/ 1150#define PHY_N_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ 1151#define PHY_N_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ 1152#define PHY_N_1000C_LP_APC (1<<9) /* Bit 9: LP Asym. Pause Cap. */ 1153 /* Bit 8: reserved */ 1154#define PHY_N_1000S_IEC (255<<0)/* Bit 7..0: Idle Error Count */ 1155 1156/***** PHY_NAT_EXT_STAT 16 bit ro Extended Status Register *****/ 1157#define PHY_N_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */ 1158#define PHY_N_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */ 1159#define PHY_N_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */ 1160#define PHY_N_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */ 1161 /* Bit 11..0: reserved */ 1162 1163/* todo: those are still missing */ 1164/***** PHY_NAT_EXT_CTRL1 16 bit ro Extended Control Reg1 *****/ 1165/***** PHY_NAT_Q_STAT1 16 bit ro Quick Status Reg1 *****/ 1166/***** PHY_NAT_10B_OP 16 bit ro 10Base-T Operations Reg *****/ 1167/***** PHY_NAT_EXT_CTRL2 16 bit ro Extended Control Reg1 *****/ 1168/***** PHY_NAT_Q_STAT2 16 bit ro Quick Status Reg2 *****/ 1169/***** PHY_NAT_PHY_ADDR 16 bit ro PHY Address Register *****/ 1170 1171/* typedefs *******************************************************************/ 1172 1173 1174/* function prototypes ********************************************************/ 1175 1176#ifdef __cplusplus 1177} 1178#endif /* __cplusplus */ 1179 1180#endif /* __INC_XMAC_H */ 1181