1/* $Linux: hydra.h,v 1.0 1994/10/26 02:03:47 cgd Exp $ */ 2 3/* 4 * Copyright (c) 1994 Timo Rossi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Timo Rossi 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * The Hydra Systems card uses the National Semiconductor 35 * 8390 NIC (Network Interface Controller) chip, located 36 * at card base address + 0xffe1. NIC registers are accessible 37 * only at odd byte addresses, so the register offsets must 38 * be multiplied by two. 39 * 40 * Card address PROM is located at card base + 0xffc0 (even byte addresses) 41 * 42 * RAM starts at the card base address, and is 16K or 64K. 43 * The current Amiga NetBSD hydra driver is hardwired for 16K. 44 * It seems that the RAM should be accessed as words or longwords only. 45 * 46 */ 47 48/* adapted for Linux by Topi Kanerva 03/29/95 49 with original author's permission */ 50 51#define HYDRA_NIC_BASE 0xffe1 52 53/* Page0 registers */ 54 55#define NIC_CR 0 /* Command register */ 56#define NIC_PSTART (1*2) /* Page start (write) */ 57#define NIC_PSTOP (2*2) /* Page stop (write) */ 58#define NIC_BNDRY (3*2) /* Boundary pointer */ 59#define NIC_TSR (4*2) /* Transmit status (read) */ 60#define NIC_TPSR (4*2) /* Transmit page start (write) */ 61#define NIC_NCR (5*2) /* Number of collisions, read */ 62#define NIC_TBCR0 (5*2) /* Transmit byte count low (write) */ 63#define NIC_FIFO (6*2) /* FIFO reg. (read) */ 64#define NIC_TBCR1 (6*2) /* Transmit byte count high (write) */ 65#define NIC_ISR (7*2) /* Interrupt status register */ 66#define NIC_RBCR0 (0xa*2) /* Remote byte count low (write) */ 67#define NIC_RBCR1 (0xb*2) /* Remote byte count high (write) */ 68#define NIC_RSR (0xc*2) /* Receive status (read) */ 69#define NIC_RCR (0xc*2) /* Receive config (write) */ 70#define NIC_CNTR0 (0xd*2) /* Frame alignment error count (read) */ 71#define NIC_TCR (0xd*2) /* Transmit config (write) */ 72#define NIC_CNTR1 (0xe*2) /* CRC error counter (read) */ 73#define NIC_DCR (0xe*2) /* Data config (write) */ 74#define NIC_CNTR2 (0xf*2) /* missed packet counter (read) */ 75#define NIC_IMR (0xf*2) /* Interrupt mask reg. (write) */ 76 77/* Page1 registers */ 78 79#define NIC_PAR0 (1*2) /* Physical address */ 80#define NIC_PAR1 (2*2) 81#define NIC_PAR2 (3*2) 82#define NIC_PAR3 (4*2) 83#define NIC_PAR4 (5*2) 84#define NIC_PAR5 (6*2) 85#define NIC_CURR (7*2) /* Current RX ring-buffer page */ 86#define NIC_MAR0 (8*2) /* Multicast address */ 87#define NIC_MAR1 (9*2) 88#define NIC_MAR2 (0xa*2) 89#define NIC_MAR3 (0xb*2) 90#define NIC_MAR4 (0xc*2) 91#define NIC_MAR5 (0xd*2) 92#define NIC_MAR6 (0xe*2) 93#define NIC_MAR7 (0xf*2) 94 95/* Command register definitions */ 96 97#define CR_STOP 0x01 /* Stop -- software reset command */ 98#define CR_START 0x02 /* Start */ 99#define CR_TXP 0x04 /* Transmit packet */ 100 101#define CR_RD0 0x08 /* Remote DMA cmd */ 102#define CR_RD1 0x10 103#define CR_RD2 0x20 104 105#define CR_NODMA CR_RD2 106 107#define CR_PS0 0x40 /* Page select */ 108#define CR_PS1 0x80 109 110#define CR_PAGE0 0 111#define CR_PAGE1 CR_PS0 112#define CR_PAGE2 CR_PS1 113 114/* Interrupt status reg. definitions */ 115 116#define ISR_PRX 0x01 /* Packet received without errors */ 117#define ISR_PTX 0x02 /* Packet transmitted without errors */ 118#define ISR_RXE 0x04 /* Receive error */ 119#define ISR_TXE 0x08 /* Transmit error */ 120#define ISR_OVW 0x10 /* Ring buffer overrun */ 121#define ISR_CNT 0x20 /* Counter overflow */ 122#define ISR_RDC 0x40 /* Remote DMA compile */ 123#define ISR_RST 0x80 /* Reset status */ 124 125/* Data config reg. definitions */ 126 127#define DCR_WTS 0x01 /* Word transfer select */ 128#define DCR_BOS 0x02 /* Byte order select */ 129#define DCR_LAS 0x04 /* Long address select */ 130#define DCR_LS 0x08 /* Loopback select */ 131#define DCR_AR 0x10 /* Auto-init remote */ 132#define DCR_FT0 0x20 /* FIFO threshold select */ 133#define DCR_FT1 0x40 134 135/* Transmit config reg. definitions */ 136 137#define TCR_CRC 0x01 /* Inhibit CRC */ 138#define TCR_LB0 0x02 /* Loopback control */ 139#define TCR_LB1 0x04 140#define TCR_ATD 0x08 /* Auto transmit disable */ 141#define TCR_OFST 0x10 /* Collision offset enable */ 142 143/* Transmit status reg. definitions */ 144 145#define TSR_PTX 0x01 /* Packet transmitted */ 146#define TSR_COL 0x04 /* Transmit collided */ 147#define TSR_ABT 0x08 /* Transmit aborted */ 148#define TSR_CRS 0x10 /* Carrier sense lost */ 149#define TSR_FU 0x20 /* FIFO underrun */ 150#define TSR_CDH 0x40 /* CD Heartbeat */ 151#define TSR_OWC 0x80 /* Out of Window Collision */ 152 153/* Receiver config register definitions */ 154 155#define RCR_SEP 0x01 /* Save errored packets */ 156#define RCR_AR 0x02 /* Accept runt packets */ 157#define RCR_AB 0x04 /* Accept broadcast */ 158#define RCR_AM 0x08 /* Accept multicast */ 159#define RCR_PRO 0x10 /* Promiscuous mode */ 160#define RCR_MON 0x20 /* Monitor mode */ 161 162/* Receiver status register definitions */ 163 164#define RSR_PRX 0x01 /* Packet received without error */ 165#define RSR_CRC 0x02 /* CRC error */ 166#define RSR_FAE 0x04 /* Frame alignment error */ 167#define RSR_FO 0x08 /* FIFO overrun */ 168#define RSR_MPA 0x10 /* Missed packet */ 169#define RSR_PHY 0x20 /* Physical address */ 170#define RSR_DIS 0x40 /* Received disabled */ 171#define RSR_DFR 0x80 /* Deferring (jabber) */ 172 173/* Hydra System card address PROM offset */ 174 175#define HYDRA_ADDRPROM 0xffc0 176 177 178