1/* hamachi.c: A Packet Engines GNIC-II Gigabit Ethernet driver for Linux. */ 2/* 3 Written 1998-2000 by Donald Becker. 4 Updates 2000 by Keith Underwood. 5 6 This software may be used and distributed according to the terms of 7 the GNU General Public License (GPL), incorporated herein by reference. 8 Drivers based on or derived from this code fall under the GPL and must 9 retain the authorship, copyright and license notice. This file is not 10 a complete program and may only be used when the entire operating 11 system is licensed under the GPL. 12 13 The author may be reached as becker@scyld.com, or C/O 14 Scyld Computing Corporation 15 410 Severn Ave., Suite 210 16 Annapolis MD 21403 17 18 This driver is for the Packet Engines GNIC-II PCI Gigabit Ethernet 19 adapter. 20 21 Support and updates available at 22 http://www.scyld.com/network/hamachi.html 23 or 24 http://www.parl.clemson.edu/~keithu/hamachi.html 25 26 27 28 Linux kernel changelog: 29 30 LK1.0.1: 31 - fix lack of pci_dev<->dev association 32 - ethtool support (jgarzik) 33 34*/ 35 36#define DRV_NAME "hamachi" 37#define DRV_VERSION "1.01+LK1.0.1" 38#define DRV_RELDATE "5/18/2001" 39 40 41/* A few user-configurable values. */ 42 43static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ 44#define final_version 45#define hamachi_debug debug 46/* Maximum events (Rx packets, etc.) to handle at each interrupt. */ 47static int max_interrupt_work = 40; 48static int mtu; 49/* Default values selected by testing on a dual processor PIII-450 */ 50/* These six interrupt control parameters may be set directly when loading the 51 * module, or through the rx_params and tx_params variables 52 */ 53static int max_rx_latency = 0x11; 54static int max_rx_gap = 0x05; 55static int min_rx_pkt = 0x18; 56static int max_tx_latency = 0x00; 57static int max_tx_gap = 0x00; 58static int min_tx_pkt = 0x30; 59 60/* Set the copy breakpoint for the copy-only-tiny-frames scheme. 61 -Setting to > 1518 causes all frames to be copied 62 -Setting to 0 disables copies 63*/ 64static int rx_copybreak; 65 66/* An override for the hardware detection of bus width. 67 Set to 1 to force 32 bit PCI bus detection. Set to 4 to force 64 bit. 68 Add 2 to disable parity detection. 69*/ 70static int force32; 71 72 73/* Used to pass the media type, etc. 74 These exist for driver interoperability. 75 No media types are currently defined. 76 - The lower 4 bits are reserved for the media type. 77 - The next three bits may be set to one of the following: 78 0x00000000 : Autodetect PCI bus 79 0x00000010 : Force 32 bit PCI bus 80 0x00000020 : Disable parity detection 81 0x00000040 : Force 64 bit PCI bus 82 Default is autodetect 83 - The next bit can be used to force half-duplex. This is a bad 84 idea since no known implementations implement half-duplex, and, 85 in general, half-duplex for gigabit ethernet is a bad idea. 86 0x00000080 : Force half-duplex 87 Default is full-duplex. 88 - In the original driver, the ninth bit could be used to force 89 full-duplex. Maintain that for compatibility 90 0x00000200 : Force full-duplex 91*/ 92#define MAX_UNITS 8 /* More are supported, limit only on options */ 93static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 94static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 95/* The Hamachi chipset supports 3 parameters each for Rx and Tx 96 * interruput management. Parameters will be loaded as specified into 97 * the TxIntControl and RxIntControl registers. 98 * 99 * The registers are arranged as follows: 100 * 23 - 16 15 - 8 7 - 0 101 * _________________________________ 102 * | min_pkt | max_gap | max_latency | 103 * --------------------------------- 104 * min_pkt : The minimum number of packets processed between 105 * interrupts. 106 * max_gap : The maximum inter-packet gap in units of 8.192 us 107 * max_latency : The absolute time between interrupts in units of 8.192 us 108 * 109 */ 110static int rx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 111static int tx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 112 113/* Operational parameters that are set at compile time. */ 114 115/* Keep the ring sizes a power of two for compile efficiency. 116 The compiler will convert <unsigned>'%'<2^N> into a bit mask. 117 Making the Tx ring too large decreases the effectiveness of channel 118 bonding and packet priority. 119 There are no ill effects from too-large receive rings, except for 120 excessive memory usage */ 121/* Empirically it appears that the Tx ring needs to be a little bigger 122 for these Gbit adapters or you get into an overrun condition really 123 easily. Also, things appear to work a bit better in back-to-back 124 configurations if the Rx ring is 8 times the size of the Tx ring 125*/ 126#define TX_RING_SIZE 64 127#define RX_RING_SIZE 512 128#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct hamachi_desc) 129#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct hamachi_desc) 130 131/* 132 * Enable netdev_ioctl. Added interrupt coalescing parameter adjustment. 133 * 2/19/99 Pete Wyckoff <wyckoff@ca.sandia.gov> 134 */ 135 136/* play with 64-bit addrlen; seems to be a teensy bit slower --pw */ 137/* #define ADDRLEN 64 */ 138 139/* 140 * RX_CHECKSUM turns on card-generated receive checksum generation for 141 * TCP and UDP packets. Otherwise the upper layers do the calculation. 142 * TX_CHECKSUM won't do anything too useful, even if it works. There's no 143 * easy mechanism by which to tell the TCP/UDP stack that it need not 144 * generate checksums for this device. But if somebody can find a way 145 * to get that to work, most of the card work is in here already. 146 * 3/10/1999 Pete Wyckoff <wyckoff@ca.sandia.gov> 147 */ 148#undef TX_CHECKSUM 149#define RX_CHECKSUM 150 151/* Operational parameters that usually are not changed. */ 152/* Time in jiffies before concluding the transmitter is hung. */ 153#define TX_TIMEOUT (5*HZ) 154 155#include <linux/module.h> 156#include <linux/kernel.h> 157#include <linux/sched.h> 158#include <linux/string.h> 159#include <linux/timer.h> 160#include <linux/time.h> 161#include <linux/ptrace.h> 162#include <linux/errno.h> 163#include <linux/ioport.h> 164#include <linux/slab.h> 165#include <linux/interrupt.h> 166#include <linux/pci.h> 167#include <linux/init.h> 168#include <linux/ethtool.h> 169#include <linux/mii.h> 170 171#include <asm/uaccess.h> 172#include <asm/processor.h> /* Processor type for cache alignment. */ 173#include <asm/bitops.h> 174#include <asm/io.h> 175#include <asm/unaligned.h> 176#include <asm/cache.h> 177 178#include <linux/netdevice.h> 179#include <linux/etherdevice.h> 180#include <linux/skbuff.h> 181#include <linux/ip.h> 182#include <linux/delay.h> 183 184static char version[] __initdata = 185KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n" 186KERN_INFO " Some modifications by Eric kasten <kasten@nscl.msu.edu>\n" 187KERN_INFO " Further modifications by Keith Underwood <keithu@parl.clemson.edu>\n"; 188 189 190/* IP_MF appears to be only defined in <netinet/ip.h>, however, 191 we need it for hardware checksumming support. FYI... some of 192 the definitions in <netinet/ip.h> conflict/duplicate those in 193 other linux headers causing many compiler warnings. 194*/ 195#ifndef IP_MF 196 #define IP_MF 0x2000 /* IP more frags from <netinet/ip.h> */ 197#endif 198 199/* Define IP_OFFSET to be IPOPT_OFFSET */ 200#ifndef IP_OFFSET 201 #ifdef IPOPT_OFFSET 202 #define IP_OFFSET IPOPT_OFFSET 203 #else 204 #define IP_OFFSET 2 205 #endif 206#endif 207 208#define RUN_AT(x) (jiffies + (x)) 209 210/* Condensed bus+endian portability operations. */ 211#if ADDRLEN == 64 212#define cpu_to_leXX(addr) cpu_to_le64(addr) 213#define desc_to_virt(addr) bus_to_virt(le64_to_cpu(addr)) 214#else 215#define cpu_to_leXX(addr) cpu_to_le32(addr) 216#define desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) 217#endif 218 219 220/* 221 Theory of Operation 222 223I. Board Compatibility 224 225This device driver is designed for the Packet Engines "Hamachi" 226Gigabit Ethernet chip. The only PCA currently supported is the GNIC-II 64-bit 22766Mhz PCI card. 228 229II. Board-specific settings 230 231No jumpers exist on the board. The chip supports software correction of 232various motherboard wiring errors, however this driver does not support 233that feature. 234 235III. Driver operation 236 237IIIa. Ring buffers 238 239The Hamachi uses a typical descriptor based bus-master architecture. 240The descriptor list is similar to that used by the Digital Tulip. 241This driver uses two statically allocated fixed-size descriptor lists 242formed into rings by a branch from the final descriptor to the beginning of 243the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. 244 245This driver uses a zero-copy receive and transmit scheme similar my other 246network drivers. 247The driver allocates full frame size skbuffs for the Rx ring buffers at 248open() time and passes the skb->data field to the Hamachi as receive data 249buffers. When an incoming frame is less than RX_COPYBREAK bytes long, 250a fresh skbuff is allocated and the frame is copied to the new skbuff. 251When the incoming frame is larger, the skbuff is passed directly up the 252protocol stack and replaced by a newly allocated skbuff. 253 254The RX_COPYBREAK value is chosen to trade-off the memory wasted by 255using a full-sized skbuff for small frames vs. the copying costs of larger 256frames. Gigabit cards are typically used on generously configured machines 257and the underfilled buffers have negligible impact compared to the benefit of 258a single allocation size, so the default value of zero results in never 259copying packets. 260 261IIIb/c. Transmit/Receive Structure 262 263The Rx and Tx descriptor structure are straight-forward, with no historical 264baggage that must be explained. Unlike the awkward DBDMA structure, there 265are no unused fields or option bits that had only one allowable setting. 266 267Two details should be noted about the descriptors: The chip supports both 32 268bit and 64 bit address structures, and the length field is overwritten on 269the receive descriptors. The descriptor length is set in the control word 270for each channel. The development driver uses 32 bit addresses only, however 27164 bit addresses may be enabled for 64 bit architectures e.g. the Alpha. 272 273IIId. Synchronization 274 275This driver is very similar to my other network drivers. 276The driver runs as two independent, single-threaded flows of control. One 277is the send-packet routine, which enforces single-threaded use by the 278dev->tbusy flag. The other thread is the interrupt handler, which is single 279threaded by the hardware and other software. 280 281The send packet thread has partial control over the Tx ring and 'dev->tbusy' 282flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next 283queue slot is empty, it clears the tbusy flag when finished otherwise it sets 284the 'hmp->tx_full' flag. 285 286The interrupt handler has exclusive control over the Rx ring and records stats 287from the Tx ring. After reaping the stats, it marks the Tx queue entry as 288empty by incrementing the dirty_tx mark. Iff the 'hmp->tx_full' flag is set, it 289clears both the tx_full and tbusy flags. 290 291IV. Notes 292 293Thanks to Kim Stearns of Packet Engines for providing a pair of GNIC-II boards. 294 295IVb. References 296 297Hamachi Engineering Design Specification, 5/15/97 298(Note: This version was marked "Confidential".) 299 300IVc. Errata 301 302None noted. 303 304V. Recent Changes 305 30601/15/1999 EPK Enlargement of the TX and RX ring sizes. This appears 307 to help avoid some stall conditions -- this needs further research. 308 30901/15/1999 EPK Creation of the hamachi_tx function. This function cleans 310 the Tx ring and is called from hamachi_start_xmit (this used to be 311 called from hamachi_interrupt but it tends to delay execution of the 312 interrupt handler and thus reduce bandwidth by reducing the latency 313 between hamachi_rx()'s). Notably, some modification has been made so 314 that the cleaning loop checks only to make sure that the DescOwn bit 315 isn't set in the status flag since the card is not required 316 to set the entire flag to zero after processing. 317 31801/15/1999 EPK In the hamachi_start_tx function, the Tx ring full flag is 319 checked before attempting to add a buffer to the ring. If the ring is full 320 an attempt is made to free any dirty buffers and thus find space for 321 the new buffer or the function returns non-zero which should case the 322 scheduler to reschedule the buffer later. 323 32401/15/1999 EPK Some adjustments were made to the chip intialization. 325 End-to-end flow control should now be fully active and the interrupt 326 algorithm vars have been changed. These could probably use further tuning. 327 32801/15/1999 EPK Added the max_{rx,tx}_latency options. These are used to 329 set the rx and tx latencies for the Hamachi interrupts. If you're having 330 problems with network stalls, try setting these to higher values. 331 Valid values are 0x00 through 0xff. 332 33301/15/1999 EPK In general, the overall bandwidth has increased and 334 latencies are better (sometimes by a factor of 2). Stalls are rare at 335 this point, however there still appears to be a bug somewhere between the 336 hardware and driver. TCP checksum errors under load also appear to be 337 eliminated at this point. 338 33901/18/1999 EPK Ensured that the DescEndRing bit was being set on both the 340 Rx and Tx rings. This appears to have been affecting whether a particular 341 peer-to-peer connection would hang under high load. I believe the Rx 342 rings was typically getting set correctly, but the Tx ring wasn't getting 343 the DescEndRing bit set during initialization. ??? Does this mean the 344 hamachi card is using the DescEndRing in processing even if a particular 345 slot isn't in use -- hypothetically, the card might be searching the 346 entire Tx ring for slots with the DescOwn bit set and then processing 347 them. If the DescEndRing bit isn't set, then it might just wander off 348 through memory until it hits a chunk of data with that bit set 349 and then looping back. 350 35102/09/1999 EPK Added Michel Mueller's TxDMA Interrupt and Tx-timeout 352 problem (TxCmd and RxCmd need only to be set when idle or stopped. 353 35402/09/1999 EPK Added code to check/reset dev->tbusy in hamachi_interrupt. 355 (Michel Mueller pointed out the ``permanently busy'' potential 356 problem here). 357 35802/22/1999 EPK Added Pete Wyckoff's ioctl to control the Tx/Rx latencies. 359 36002/23/1999 EPK Verified that the interrupt status field bits for Tx were 361 incorrectly defined and corrected (as per Michel Mueller). 362 36302/23/1999 EPK Corrected the Tx full check to check that at least 4 slots 364 were available before reseting the tbusy and tx_full flags 365 (as per Michel Mueller). 366 36703/11/1999 EPK Added Pete Wyckoff's hardware checksumming support. 368 36912/31/1999 KDU Cleaned up assorted things and added Don's code to force 37032 bit. 371 37202/20/2000 KDU Some of the control was just plain odd. Cleaned up the 373hamachi_start_xmit() and hamachi_interrupt() code. There is still some 374re-structuring I would like to do. 375 37603/01/2000 KDU Experimenting with a WIDE range of interrupt mitigation 377parameters on a dual P3-450 setup yielded the new default interrupt 378mitigation parameters. Tx should interrupt VERY infrequently due to 379Eric's scheme. Rx should be more often... 380 38103/13/2000 KDU Added a patch to make the Rx Checksum code interact 382nicely with non-linux machines. 383 38403/13/2000 KDU Experimented with some of the configuration values: 385 386 -It seems that enabling PCI performance commands for descriptors 387 (changing RxDMACtrl and TxDMACtrl lower nibble from 5 to D) has minimal 388 performance impact for any of my tests. (ttcp, netpipe, netperf) I will 389 leave them that way until I hear further feedback. 390 391 -Increasing the PCI_LATENCY_TIMER to 130 392 (2 + (burst size of 128 * (0 wait states + 1))) seems to slightly 393 degrade performance. Leaving default at 64 pending further information. 394 39503/14/2000 KDU Further tuning: 396 397 -adjusted boguscnt in hamachi_rx() to depend on interrupt 398 mitigation parameters chosen. 399 400 -Selected a set of interrupt parameters based on some extensive testing. 401 These may change with more testing. 402 403TO DO: 404 405-Consider borrowing from the acenic driver code to check PCI_COMMAND for 406PCI_COMMAND_INVALIDATE. Set maximum burst size to cache line size in 407that case. 408 409-fix the reset procedure. It doesn't quite work. 410*/ 411 412/* A few values that may be tweaked. */ 413/* Size of each temporary Rx buffer, calculated as: 414 * 1518 bytes (ethernet packet) + 2 bytes (to get 8 byte alignment for 415 * the card) + 8 bytes of status info + 8 bytes for the Rx Checksum + 416 * 2 more because we use skb_reserve. 417 */ 418#define PKT_BUF_SZ 1538 419 420/* For now, this is going to be set to the maximum size of an ethernet 421 * packet. Eventually, we may want to make it a variable that is 422 * related to the MTU 423 */ 424#define MAX_FRAME_SIZE 1518 425 426/* The rest of these values should never change. */ 427 428static void hamachi_timer(unsigned long data); 429 430enum capability_flags {CanHaveMII=1, }; 431static struct chip_info { 432 u16 vendor_id, device_id, device_id_mask, pad; 433 const char *name; 434 void (*media_timer)(unsigned long data); 435 int flags; 436} chip_tbl[] = { 437 {0x1318, 0x0911, 0xffff, 0, "Hamachi GNIC-II", hamachi_timer, 0}, 438 {0,}, 439}; 440 441/* Offsets to the Hamachi registers. Various sizes. */ 442enum hamachi_offsets { 443 TxDMACtrl=0x00, TxCmd=0x04, TxStatus=0x06, TxPtr=0x08, TxCurPtr=0x10, 444 RxDMACtrl=0x20, RxCmd=0x24, RxStatus=0x26, RxPtr=0x28, RxCurPtr=0x30, 445 PCIClkMeas=0x060, MiscStatus=0x066, ChipRev=0x68, ChipReset=0x06B, 446 LEDCtrl=0x06C, VirtualJumpers=0x06D, GPIO=0x6E, 447 TxChecksum=0x074, RxChecksum=0x076, 448 TxIntrCtrl=0x078, RxIntrCtrl=0x07C, 449 InterruptEnable=0x080, InterruptClear=0x084, IntrStatus=0x088, 450 EventStatus=0x08C, 451 MACCnfg=0x0A0, FrameGap0=0x0A2, FrameGap1=0x0A4, 452 /* See enum MII_offsets below. */ 453 MACCnfg2=0x0B0, RxDepth=0x0B8, FlowCtrl=0x0BC, MaxFrameSize=0x0CE, 454 AddrMode=0x0D0, StationAddr=0x0D2, 455 /* Gigabit AutoNegotiation. */ 456 ANCtrl=0x0E0, ANStatus=0x0E2, ANXchngCtrl=0x0E4, ANAdvertise=0x0E8, 457 ANLinkPartnerAbility=0x0EA, 458 EECmdStatus=0x0F0, EEData=0x0F1, EEAddr=0x0F2, 459 FIFOcfg=0x0F8, 460}; 461 462/* Offsets to the MII-mode registers. */ 463enum MII_offsets { 464 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC, 465 MII_Status=0xAE, 466}; 467 468/* Bits in the interrupt status/mask registers. */ 469enum intr_status_bits { 470 IntrRxDone=0x01, IntrRxPCIFault=0x02, IntrRxPCIErr=0x04, 471 IntrTxDone=0x100, IntrTxPCIFault=0x200, IntrTxPCIErr=0x400, 472 LinkChange=0x10000, NegotiationChange=0x20000, StatsMax=0x40000, }; 473 474/* The Hamachi Rx and Tx buffer descriptors. */ 475struct hamachi_desc { 476 u32 status_n_length; 477#if ADDRLEN == 64 478 u32 pad; 479 u64 addr; 480#else 481 u32 addr; 482#endif 483}; 484 485/* Bits in hamachi_desc.status_n_length */ 486enum desc_status_bits { 487 DescOwn=0x80000000, DescEndPacket=0x40000000, DescEndRing=0x20000000, 488 DescIntr=0x10000000, 489}; 490 491#define PRIV_ALIGN 15 /* Required alignment mask */ 492#define MII_CNT 4 493struct hamachi_private { 494 /* Descriptor rings first for alignment. Tx requires a second descriptor 495 for status. */ 496 struct hamachi_desc *rx_ring; 497 struct hamachi_desc *tx_ring; 498 struct sk_buff* rx_skbuff[RX_RING_SIZE]; 499 struct sk_buff* tx_skbuff[TX_RING_SIZE]; 500 dma_addr_t tx_ring_dma; 501 dma_addr_t rx_ring_dma; 502 struct net_device_stats stats; 503 struct timer_list timer; /* Media selection timer. */ 504 /* Frequently used and paired value: keep adjacent for cache effect. */ 505 spinlock_t lock; 506 int chip_id; 507 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ 508 unsigned int cur_tx, dirty_tx; 509 unsigned int rx_buf_sz; /* Based on MTU+slack. */ 510 unsigned int tx_full:1; /* The Tx queue is full. */ 511 unsigned int full_duplex:1; /* Full-duplex operation requested. */ 512 unsigned int duplex_lock:1; 513 unsigned int medialock:1; /* Do not sense media. */ 514 unsigned int default_port:4; /* Last dev->if_port value. */ 515 /* MII transceiver section. */ 516 int mii_cnt; /* MII device addresses. */ 517 u16 advertising; /* NWay media advertisement */ 518 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */ 519 u32 rx_int_var, tx_int_var; /* interrupt control variables */ 520 u32 option; /* Hold on to a copy of the options */ 521 struct pci_dev *pci_dev; 522}; 523 524MODULE_AUTHOR("Donald Becker <becker@scyld.com>, Eric Kasten <kasten@nscl.msu.edu>, Keith Underwood <keithu@parl.clemson.edu>"); 525MODULE_DESCRIPTION("Packet Engines 'Hamachi' GNIC-II Gigabit Ethernet driver"); 526MODULE_LICENSE("GPL"); 527 528MODULE_PARM(max_interrupt_work, "i"); 529MODULE_PARM(mtu, "i"); 530MODULE_PARM(debug, "i"); 531MODULE_PARM(min_rx_pkt, "i"); 532MODULE_PARM(max_rx_gap, "i"); 533MODULE_PARM(max_rx_latency, "i"); 534MODULE_PARM(min_tx_pkt, "i"); 535MODULE_PARM(max_tx_gap, "i"); 536MODULE_PARM(max_tx_latency, "i"); 537MODULE_PARM(rx_copybreak, "i"); 538MODULE_PARM(rx_params, "1-" __MODULE_STRING(MAX_UNITS) "i"); 539MODULE_PARM(tx_params, "1-" __MODULE_STRING(MAX_UNITS) "i"); 540MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i"); 541MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i"); 542MODULE_PARM(force32, "i"); 543MODULE_PARM_DESC(max_interrupt_work, "GNIC-II maximum events handled per interrupt"); 544MODULE_PARM_DESC(mtu, "GNIC-II MTU (all boards)"); 545MODULE_PARM_DESC(debug, "GNIC-II debug level (0-7)"); 546MODULE_PARM_DESC(min_rx_pkt, "GNIC-II minimum Rx packets processed between interrupts"); 547MODULE_PARM_DESC(max_rx_gap, "GNIC-II maximum Rx inter-packet gap in 8.192 microsecond units"); 548MODULE_PARM_DESC(max_rx_latency, "GNIC-II time between Rx interrupts in 8.192 microsecond units"); 549MODULE_PARM_DESC(min_tx_pkt, "GNIC-II minimum Tx packets processed between interrupts"); 550MODULE_PARM_DESC(max_tx_gap, "GNIC-II maximum Tx inter-packet gap in 8.192 microsecond units"); 551MODULE_PARM_DESC(max_tx_latency, "GNIC-II time between Tx interrupts in 8.192 microsecond units"); 552MODULE_PARM_DESC(rx_copybreak, "GNIC-II copy breakpoint for copy-only-tiny-frames"); 553MODULE_PARM_DESC(rx_params, "GNIC-II min_rx_pkt+max_rx_gap+max_rx_latency"); 554MODULE_PARM_DESC(tx_params, "GNIC-II min_tx_pkt+max_tx_gap+max_tx_latency"); 555MODULE_PARM_DESC(options, "GNIC-II Bits 0-3: media type, bits 4-6: as force32, bit 7: half duplex, bit 9 full duplex"); 556MODULE_PARM_DESC(full_duplex, "GNIC-II full duplex setting(s) (1)"); 557MODULE_PARM_DESC(force32, "GNIC-II: Bit 0: 32 bit PCI, bit 1: disable parity, bit 2: 64 bit PCI (all boards)"); 558 559static int read_eeprom(long ioaddr, int location); 560static int mdio_read(long ioaddr, int phy_id, int location); 561static void mdio_write(long ioaddr, int phy_id, int location, int value); 562static int hamachi_open(struct net_device *dev); 563static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 564static void hamachi_timer(unsigned long data); 565static void hamachi_tx_timeout(struct net_device *dev); 566static void hamachi_init_ring(struct net_device *dev); 567static int hamachi_start_xmit(struct sk_buff *skb, struct net_device *dev); 568static void hamachi_interrupt(int irq, void *dev_instance, struct pt_regs *regs); 569static inline int hamachi_rx(struct net_device *dev); 570static inline int hamachi_tx(struct net_device *dev); 571static void hamachi_error(struct net_device *dev, int intr_status); 572static int hamachi_close(struct net_device *dev); 573static struct net_device_stats *hamachi_get_stats(struct net_device *dev); 574static void set_rx_mode(struct net_device *dev); 575 576 577static int __init hamachi_init_one (struct pci_dev *pdev, 578 const struct pci_device_id *ent) 579{ 580 struct hamachi_private *hmp; 581 int option, i, rx_int_var, tx_int_var, boguscnt; 582 int chip_id = ent->driver_data; 583 int irq; 584 long ioaddr; 585 static int card_idx; 586 struct net_device *dev; 587 void *ring_space; 588 dma_addr_t ring_dma; 589 int ret = -ENOMEM; 590 591/* when built into the kernel, we only print version if device is found */ 592#ifndef MODULE 593 static int printed_version; 594 if (!printed_version++) 595 printk(version); 596#endif 597 598 if (pci_enable_device(pdev)) { 599 ret = -EIO; 600 goto err_out; 601 } 602 603 ioaddr = pci_resource_start(pdev, 0); 604#ifdef __alpha__ /* Really "64 bit addrs" */ 605 ioaddr |= (pci_resource_start(pdev, 1) << 32); 606#endif 607 608 pci_set_master(pdev); 609 610 i = pci_request_regions(pdev, DRV_NAME); 611 if (i) return i; 612 613 irq = pdev->irq; 614 ioaddr = (long) ioremap(ioaddr, 0x400); 615 if (!ioaddr) 616 goto err_out_release; 617 618 dev = alloc_etherdev(sizeof(struct hamachi_private)); 619 if (!dev) 620 goto err_out_iounmap; 621 622 SET_MODULE_OWNER(dev); 623 624#ifdef TX_CHECKSUM 625 printk("check that skbcopy in ip_queue_xmit isn't happening\n"); 626 dev->hard_header_len += 8; /* for cksum tag */ 627#endif 628 629 for (i = 0; i < 6; i++) 630 dev->dev_addr[i] = 1 ? read_eeprom(ioaddr, 4 + i) 631 : readb(ioaddr + StationAddr + i); 632 633#if !defined(final_version) 634 if (hamachi_debug > 4) 635 for (i = 0; i < 0x10; i++) 636 printk("%2.2x%s", 637 read_eeprom(ioaddr, i), i % 16 != 15 ? " " : "\n"); 638#endif 639 640 hmp = dev->priv; 641 spin_lock_init(&hmp->lock); 642 643 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma); 644 if (!ring_space) 645 goto err_out_cleardev; 646 hmp->tx_ring = (struct hamachi_desc *)ring_space; 647 hmp->tx_ring_dma = ring_dma; 648 649 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma); 650 if (!ring_space) 651 goto err_out_unmap_tx; 652 hmp->rx_ring = (struct hamachi_desc *)ring_space; 653 hmp->rx_ring_dma = ring_dma; 654 655 /* Check for options being passed in */ 656 option = card_idx < MAX_UNITS ? options[card_idx] : 0; 657 if (dev->mem_start) 658 option = dev->mem_start; 659 660 /* If the bus size is misidentified, do the following. */ 661 force32 = force32 ? force32 : 662 ((option >= 0) ? ((option & 0x00000070) >> 4) : 0 ); 663 if (force32) 664 writeb(force32, ioaddr + VirtualJumpers); 665 666 /* Hmmm, do we really need to reset the chip???. */ 667 writeb(0x01, ioaddr + ChipReset); 668 669 /* After a reset, the clock speed measurement of the PCI bus will not 670 * be valid for a moment. Wait for a little while until it is. If 671 * it takes more than 10ms, forget it. 672 */ 673 udelay(10); 674 i = readb(ioaddr + PCIClkMeas); 675 for (boguscnt = 0; (!(i & 0x080)) && boguscnt < 1000; boguscnt++){ 676 udelay(10); 677 i = readb(ioaddr + PCIClkMeas); 678 } 679 680 dev->base_addr = ioaddr; 681 dev->irq = irq; 682 pci_set_drvdata(pdev, dev); 683 684 hmp->chip_id = chip_id; 685 hmp->pci_dev = pdev; 686 687 /* The lower four bits are the media type. */ 688 if (option > 0) { 689 hmp->option = option; 690 if (option & 0x200) 691 hmp->full_duplex = 1; 692 else if (option & 0x080) 693 hmp->full_duplex = 0; 694 hmp->default_port = option & 15; 695 if (hmp->default_port) 696 hmp->medialock = 1; 697 } 698 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0) 699 hmp->full_duplex = 1; 700 701 /* lock the duplex mode if someone specified a value */ 702 if (hmp->full_duplex || (option & 0x080)) 703 hmp->duplex_lock = 1; 704 705 /* Set interrupt tuning parameters */ 706 max_rx_latency = max_rx_latency & 0x00ff; 707 max_rx_gap = max_rx_gap & 0x00ff; 708 min_rx_pkt = min_rx_pkt & 0x00ff; 709 max_tx_latency = max_tx_latency & 0x00ff; 710 max_tx_gap = max_tx_gap & 0x00ff; 711 min_tx_pkt = min_tx_pkt & 0x00ff; 712 713 rx_int_var = card_idx < MAX_UNITS ? rx_params[card_idx] : -1; 714 tx_int_var = card_idx < MAX_UNITS ? tx_params[card_idx] : -1; 715 hmp->rx_int_var = rx_int_var >= 0 ? rx_int_var : 716 (min_rx_pkt << 16 | max_rx_gap << 8 | max_rx_latency); 717 hmp->tx_int_var = tx_int_var >= 0 ? tx_int_var : 718 (min_tx_pkt << 16 | max_tx_gap << 8 | max_tx_latency); 719 720 721 /* The Hamachi-specific entries in the device structure. */ 722 dev->open = &hamachi_open; 723 dev->hard_start_xmit = &hamachi_start_xmit; 724 dev->stop = &hamachi_close; 725 dev->get_stats = &hamachi_get_stats; 726 dev->set_multicast_list = &set_rx_mode; 727 dev->do_ioctl = &netdev_ioctl; 728 dev->tx_timeout = &hamachi_tx_timeout; 729 dev->watchdog_timeo = TX_TIMEOUT; 730 if (mtu) 731 dev->mtu = mtu; 732 733 i = register_netdev(dev); 734 if (i) { 735 ret = i; 736 goto err_out_unmap_rx; 737 } 738 739 printk(KERN_INFO "%s: %s type %x at 0x%lx, ", 740 dev->name, chip_tbl[chip_id].name, readl(ioaddr + ChipRev), 741 ioaddr); 742 for (i = 0; i < 5; i++) 743 printk("%2.2x:", dev->dev_addr[i]); 744 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq); 745 i = readb(ioaddr + PCIClkMeas); 746 printk(KERN_INFO "%s: %d-bit %d Mhz PCI bus (%d), Virtual Jumpers " 747 "%2.2x, LPA %4.4x.\n", 748 dev->name, readw(ioaddr + MiscStatus) & 1 ? 64 : 32, 749 i ? 2000/(i&0x7f) : 0, i&0x7f, (int)readb(ioaddr + VirtualJumpers), 750 readw(ioaddr + ANLinkPartnerAbility)); 751 752 if (chip_tbl[hmp->chip_id].flags & CanHaveMII) { 753 int phy, phy_idx = 0; 754 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) { 755 int mii_status = mdio_read(ioaddr, phy, 1); 756 if (mii_status != 0xffff && 757 mii_status != 0x0000) { 758 hmp->phys[phy_idx++] = phy; 759 hmp->advertising = mdio_read(ioaddr, phy, 4); 760 printk(KERN_INFO "%s: MII PHY found at address %d, status " 761 "0x%4.4x advertising %4.4x.\n", 762 dev->name, phy, mii_status, hmp->advertising); 763 } 764 } 765 hmp->mii_cnt = phy_idx; 766 } 767 /* Configure gigabit autonegotiation. */ 768 writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */ 769 writew(0x08e0, ioaddr + ANAdvertise); /* Set our advertise word. */ 770 writew(0x1000, ioaddr + ANCtrl); /* Enable negotiation */ 771 772 card_idx++; 773 return 0; 774 775err_out_unmap_rx: 776 pci_free_consistent(pdev, RX_TOTAL_SIZE, hmp->rx_ring, 777 hmp->rx_ring_dma); 778err_out_unmap_tx: 779 pci_free_consistent(pdev, TX_TOTAL_SIZE, hmp->tx_ring, 780 hmp->tx_ring_dma); 781err_out_cleardev: 782 kfree (dev); 783err_out_iounmap: 784 iounmap((char *)ioaddr); 785err_out_release: 786 pci_release_regions(pdev); 787err_out: 788 return ret; 789} 790 791static int __init read_eeprom(long ioaddr, int location) 792{ 793 int bogus_cnt = 1000; 794 795 /* We should check busy first - per docs -KDU */ 796 while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0); 797 writew(location, ioaddr + EEAddr); 798 writeb(0x02, ioaddr + EECmdStatus); 799 bogus_cnt = 1000; 800 while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0); 801 if (hamachi_debug > 5) 802 printk(" EEPROM status is %2.2x after %d ticks.\n", 803 (int)readb(ioaddr + EECmdStatus), 1000- bogus_cnt); 804 return readb(ioaddr + EEData); 805} 806 807/* MII Managemen Data I/O accesses. 808 These routines assume the MDIO controller is idle, and do not exit until 809 the command is finished. */ 810 811static int mdio_read(long ioaddr, int phy_id, int location) 812{ 813 int i; 814 815 /* We should check busy first - per docs -KDU */ 816 for (i = 10000; i >= 0; i--) 817 if ((readw(ioaddr + MII_Status) & 1) == 0) 818 break; 819 writew((phy_id<<8) + location, ioaddr + MII_Addr); 820 writew(0x0001, ioaddr + MII_Cmd); 821 for (i = 10000; i >= 0; i--) 822 if ((readw(ioaddr + MII_Status) & 1) == 0) 823 break; 824 return readw(ioaddr + MII_Rd_Data); 825} 826 827static void mdio_write(long ioaddr, int phy_id, int location, int value) 828{ 829 int i; 830 831 /* We should check busy first - per docs -KDU */ 832 for (i = 10000; i >= 0; i--) 833 if ((readw(ioaddr + MII_Status) & 1) == 0) 834 break; 835 writew((phy_id<<8) + location, ioaddr + MII_Addr); 836 writew(value, ioaddr + MII_Wr_Data); 837 838 /* Wait for the command to finish. */ 839 for (i = 10000; i >= 0; i--) 840 if ((readw(ioaddr + MII_Status) & 1) == 0) 841 break; 842 return; 843} 844 845 846static int hamachi_open(struct net_device *dev) 847{ 848 struct hamachi_private *hmp = dev->priv; 849 long ioaddr = dev->base_addr; 850 int i; 851 u32 rx_int_var, tx_int_var; 852 u16 fifo_info; 853 854 i = request_irq(dev->irq, &hamachi_interrupt, SA_SHIRQ, dev->name, dev); 855 if (i) 856 return i; 857 858 if (hamachi_debug > 1) 859 printk(KERN_DEBUG "%s: hamachi_open() irq %d.\n", 860 dev->name, dev->irq); 861 862 hamachi_init_ring(dev); 863 864#if ADDRLEN == 64 865 /* writellll anyone ? */ 866 writel(cpu_to_le64(hmp->rx_ring_dma), ioaddr + RxPtr); 867 writel(cpu_to_le64(hmp->rx_ring_dma) >> 32, ioaddr + RxPtr + 4); 868 writel(cpu_to_le64(hmp->tx_ring_dma), ioaddr + TxPtr); 869 writel(cpu_to_le64(hmp->tx_ring_dma) >> 32, ioaddr + TxPtr + 4); 870#else 871 writel(cpu_to_le32(hmp->rx_ring_dma), ioaddr + RxPtr); 872 writel(cpu_to_le32(hmp->tx_ring_dma), ioaddr + TxPtr); 873#endif 874 875 /* TODO: It would make sense to organize this as words since the card 876 * documentation does. -KDU 877 */ 878 for (i = 0; i < 6; i++) 879 writeb(dev->dev_addr[i], ioaddr + StationAddr + i); 880 881 /* Initialize other registers: with so many this eventually this will 882 converted to an offset/value list. */ 883 884 /* Configure the FIFO */ 885 fifo_info = (readw(ioaddr + GPIO) & 0x00C0) >> 6; 886 switch (fifo_info){ 887 case 0 : 888 /* No FIFO */ 889 writew(0x0000, ioaddr + FIFOcfg); 890 break; 891 case 1 : 892 /* Configure the FIFO for 512K external, 16K used for Tx. */ 893 writew(0x0028, ioaddr + FIFOcfg); 894 break; 895 case 2 : 896 /* Configure the FIFO for 1024 external, 32K used for Tx. */ 897 writew(0x004C, ioaddr + FIFOcfg); 898 break; 899 case 3 : 900 /* Configure the FIFO for 2048 external, 32K used for Tx. */ 901 writew(0x006C, ioaddr + FIFOcfg); 902 break; 903 default : 904 printk(KERN_WARNING "%s: Unsupported external memory config!\n", 905 dev->name); 906 /* Default to no FIFO */ 907 writew(0x0000, ioaddr + FIFOcfg); 908 break; 909 } 910 911 if (dev->if_port == 0) 912 dev->if_port = hmp->default_port; 913 914 915 /* Setting the Rx mode will start the Rx process. */ 916 /* If someone didn't choose a duplex, default to full-duplex */ 917 if (hmp->duplex_lock != 1) 918 hmp->full_duplex = 1; 919 920 /* always 1, takes no more time to do it */ 921 writew(0x0001, ioaddr + RxChecksum); 922#ifdef TX_CHECKSUM 923 writew(0x0001, ioaddr + TxChecksum); 924#else 925 writew(0x0000, ioaddr + TxChecksum); 926#endif 927 writew(0x8000, ioaddr + MACCnfg); /* Soft reset the MAC */ 928 writew(0x215F, ioaddr + MACCnfg); 929 writew(0x000C, ioaddr + FrameGap0); 930 /* WHAT?!?!? Why isn't this documented somewhere? -KDU */ 931 writew(0x1018, ioaddr + FrameGap1); 932 /* Why do we enable receives/transmits here? -KDU */ 933 writew(0x0780, ioaddr + MACCnfg2); /* Upper 16 bits control LEDs. */ 934 /* Enable automatic generation of flow control frames, period 0xffff. */ 935 writel(0x0030FFFF, ioaddr + FlowCtrl); 936 writew(MAX_FRAME_SIZE, ioaddr + MaxFrameSize); /* dev->mtu+14 ??? */ 937 938 /* Enable legacy links. */ 939 writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */ 940 /* Initial Link LED to blinking red. */ 941 writeb(0x03, ioaddr + LEDCtrl); 942 943 /* Configure interrupt mitigation. This has a great effect on 944 performance, so systems tuning should start here!. */ 945 946 rx_int_var = hmp->rx_int_var; 947 tx_int_var = hmp->tx_int_var; 948 949 if (hamachi_debug > 1) { 950 printk("max_tx_latency: %d, max_tx_gap: %d, min_tx_pkt: %d\n", 951 tx_int_var & 0x00ff, (tx_int_var & 0x00ff00) >> 8, 952 (tx_int_var & 0x00ff0000) >> 16); 953 printk("max_rx_latency: %d, max_rx_gap: %d, min_rx_pkt: %d\n", 954 rx_int_var & 0x00ff, (rx_int_var & 0x00ff00) >> 8, 955 (rx_int_var & 0x00ff0000) >> 16); 956 printk("rx_int_var: %x, tx_int_var: %x\n", rx_int_var, tx_int_var); 957 } 958 959 writel(tx_int_var, ioaddr + TxIntrCtrl); 960 writel(rx_int_var, ioaddr + RxIntrCtrl); 961 962 set_rx_mode(dev); 963 964 netif_start_queue(dev); 965 966 /* Enable interrupts by setting the interrupt mask. */ 967 writel(0x80878787, ioaddr + InterruptEnable); 968 writew(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */ 969 970 /* Configure and start the DMA channels. */ 971 /* Burst sizes are in the low three bits: size = 4<<(val&7) */ 972#if ADDRLEN == 64 973 writew(0x005D, ioaddr + RxDMACtrl); /* 128 dword bursts */ 974 writew(0x005D, ioaddr + TxDMACtrl); 975#else 976 writew(0x001D, ioaddr + RxDMACtrl); 977 writew(0x001D, ioaddr + TxDMACtrl); 978#endif 979 writew(0x0001, dev->base_addr + RxCmd); 980 981 if (hamachi_debug > 2) { 982 printk(KERN_DEBUG "%s: Done hamachi_open(), status: Rx %x Tx %x.\n", 983 dev->name, readw(ioaddr + RxStatus), readw(ioaddr + TxStatus)); 984 } 985 /* Set the timer to check for link beat. */ 986 init_timer(&hmp->timer); 987 hmp->timer.expires = RUN_AT((24*HZ)/10); /* 2.4 sec. */ 988 hmp->timer.data = (unsigned long)dev; 989 hmp->timer.function = &hamachi_timer; /* timer handler */ 990 add_timer(&hmp->timer); 991 992 return 0; 993} 994 995static inline int hamachi_tx(struct net_device *dev) 996{ 997 struct hamachi_private *hmp = dev->priv; 998 999 /* Update the dirty pointer until we find an entry that is 1000 still owned by the card */ 1001 for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++) { 1002 int entry = hmp->dirty_tx % TX_RING_SIZE; 1003 struct sk_buff *skb; 1004 1005 if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn)) 1006 break; 1007 /* Free the original skb. */ 1008 skb = hmp->tx_skbuff[entry]; 1009 if (skb != 0) { 1010 pci_unmap_single(hmp->pci_dev, 1011 hmp->tx_ring[entry].addr, skb->len, 1012 PCI_DMA_TODEVICE); 1013 dev_kfree_skb(skb); 1014 hmp->tx_skbuff[entry] = 0; 1015 } 1016 hmp->tx_ring[entry].status_n_length = 0; 1017 if (entry >= TX_RING_SIZE-1) 1018 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |= 1019 cpu_to_le32(DescEndRing); 1020 hmp->stats.tx_packets++; 1021 } 1022 1023 return 0; 1024} 1025 1026static void hamachi_timer(unsigned long data) 1027{ 1028 struct net_device *dev = (struct net_device *)data; 1029 struct hamachi_private *hmp = dev->priv; 1030 long ioaddr = dev->base_addr; 1031 int next_tick = 10*HZ; 1032 1033 if (hamachi_debug > 2) { 1034 printk(KERN_INFO "%s: Hamachi Autonegotiation status %4.4x, LPA " 1035 "%4.4x.\n", dev->name, readw(ioaddr + ANStatus), 1036 readw(ioaddr + ANLinkPartnerAbility)); 1037 printk(KERN_INFO "%s: Autonegotiation regs %4.4x %4.4x %4.4x " 1038 "%4.4x %4.4x %4.4x.\n", dev->name, 1039 readw(ioaddr + 0x0e0), 1040 readw(ioaddr + 0x0e2), 1041 readw(ioaddr + 0x0e4), 1042 readw(ioaddr + 0x0e6), 1043 readw(ioaddr + 0x0e8), 1044 readw(ioaddr + 0x0eA)); 1045 } 1046 /* We could do something here... nah. */ 1047 hmp->timer.expires = RUN_AT(next_tick); 1048 add_timer(&hmp->timer); 1049} 1050 1051static void hamachi_tx_timeout(struct net_device *dev) 1052{ 1053 int i; 1054 struct hamachi_private *hmp = dev->priv; 1055 long ioaddr = dev->base_addr; 1056 1057 printk(KERN_WARNING "%s: Hamachi transmit timed out, status %8.8x," 1058 " resetting...\n", dev->name, (int)readw(ioaddr + TxStatus)); 1059 1060 { 1061 int i; 1062 printk(KERN_DEBUG " Rx ring %p: ", hmp->rx_ring); 1063 for (i = 0; i < RX_RING_SIZE; i++) 1064 printk(" %8.8x", (unsigned int)hmp->rx_ring[i].status_n_length); 1065 printk("\n"KERN_DEBUG" Tx ring %p: ", hmp->tx_ring); 1066 for (i = 0; i < TX_RING_SIZE; i++) 1067 printk(" %4.4x", hmp->tx_ring[i].status_n_length); 1068 printk("\n"); 1069 } 1070 1071 /* Reinit the hardware and make sure the Rx and Tx processes 1072 are up and running. 1073 */ 1074 dev->if_port = 0; 1075 /* The right way to do Reset. -KDU 1076 * -Clear OWN bit in all Rx/Tx descriptors 1077 * -Wait 50 uS for channels to go idle 1078 * -Turn off MAC receiver 1079 * -Issue Reset 1080 */ 1081 1082 for (i = 0; i < RX_RING_SIZE; i++) 1083 hmp->rx_ring[i].status_n_length &= cpu_to_le32(~DescOwn); 1084 1085 /* Presume that all packets in the Tx queue are gone if we have to 1086 * re-init the hardware. 1087 */ 1088 for (i = 0; i < TX_RING_SIZE; i++){ 1089 struct sk_buff *skb; 1090 1091 if (i >= TX_RING_SIZE - 1) 1092 hmp->tx_ring[i].status_n_length = cpu_to_le32( 1093 DescEndRing | 1094 (hmp->tx_ring[i].status_n_length & 0x0000FFFF)); 1095 else 1096 hmp->tx_ring[i].status_n_length &= 0x0000ffff; 1097 skb = hmp->tx_skbuff[i]; 1098 if (skb){ 1099 pci_unmap_single(hmp->pci_dev, hmp->tx_ring[i].addr, 1100 skb->len, PCI_DMA_TODEVICE); 1101 dev_kfree_skb(skb); 1102 hmp->tx_skbuff[i] = 0; 1103 } 1104 } 1105 1106 udelay(60); /* Sleep 60 us just for safety sake */ 1107 writew(0x0002, dev->base_addr + RxCmd); /* STOP Rx */ 1108 1109 writeb(0x01, ioaddr + ChipReset); /* Reinit the hardware */ 1110 1111 hmp->tx_full = 0; 1112 hmp->cur_rx = hmp->cur_tx = 0; 1113 hmp->dirty_rx = hmp->dirty_tx = 0; 1114 /* Rx packets are also presumed lost; however, we need to make sure a 1115 * ring of buffers is in tact. -KDU 1116 */ 1117 for (i = 0; i < RX_RING_SIZE; i++){ 1118 struct sk_buff *skb = hmp->rx_skbuff[i]; 1119 1120 if (skb){ 1121 pci_unmap_single(hmp->pci_dev, hmp->rx_ring[i].addr, 1122 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE); 1123 dev_kfree_skb(skb); 1124 hmp->rx_skbuff[i] = 0; 1125 } 1126 } 1127 /* Fill in the Rx buffers. Handle allocation failure gracefully. */ 1128 for (i = 0; i < RX_RING_SIZE; i++) { 1129 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz); 1130 hmp->rx_skbuff[i] = skb; 1131 if (skb == NULL) 1132 break; 1133 skb->dev = dev; /* Mark as being used by this device. */ 1134 skb_reserve(skb, 2); /* 16 byte align the IP header. */ 1135 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev, 1136 skb->tail, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE)); 1137 hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn | 1138 DescEndPacket | DescIntr | (hmp->rx_buf_sz - 2)); 1139 } 1140 hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE); 1141 /* Mark the last entry as wrapping the ring. */ 1142 hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing); 1143 1144 /* Trigger an immediate transmit demand. */ 1145 dev->trans_start = jiffies; 1146 hmp->stats.tx_errors++; 1147 1148 /* Restart the chip's Tx/Rx processes . */ 1149 writew(0x0002, dev->base_addr + TxCmd); /* STOP Tx */ 1150 writew(0x0001, dev->base_addr + TxCmd); /* START Tx */ 1151 writew(0x0001, dev->base_addr + RxCmd); /* START Rx */ 1152 1153 netif_wake_queue(dev); 1154} 1155 1156 1157/* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1158static void hamachi_init_ring(struct net_device *dev) 1159{ 1160 struct hamachi_private *hmp = dev->priv; 1161 int i; 1162 1163 hmp->tx_full = 0; 1164 hmp->cur_rx = hmp->cur_tx = 0; 1165 hmp->dirty_rx = hmp->dirty_tx = 0; 1166 1167 /* My attempt at a reasonable correction */ 1168 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1169 * card needs room to do 8 byte alignment, +2 so we can reserve 1170 * the first 2 bytes, and +16 gets room for the status word from the 1171 * card. -KDU 1172 */ 1173 hmp->rx_buf_sz = (dev->mtu <= 1492 ? PKT_BUF_SZ : 1174 (((dev->mtu+26+7) & ~7) + 2 + 16)); 1175 1176 /* Initialize all Rx descriptors. */ 1177 for (i = 0; i < RX_RING_SIZE; i++) { 1178 hmp->rx_ring[i].status_n_length = 0; 1179 hmp->rx_skbuff[i] = 0; 1180 } 1181 /* Fill in the Rx buffers. Handle allocation failure gracefully. */ 1182 for (i = 0; i < RX_RING_SIZE; i++) { 1183 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz); 1184 hmp->rx_skbuff[i] = skb; 1185 if (skb == NULL) 1186 break; 1187 skb->dev = dev; /* Mark as being used by this device. */ 1188 skb_reserve(skb, 2); /* 16 byte align the IP header. */ 1189 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev, 1190 skb->tail, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE)); 1191 /* -2 because it doesn't REALLY have that first 2 bytes -KDU */ 1192 hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn | 1193 DescEndPacket | DescIntr | (hmp->rx_buf_sz -2)); 1194 } 1195 hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE); 1196 hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing); 1197 1198 for (i = 0; i < TX_RING_SIZE; i++) { 1199 hmp->tx_skbuff[i] = 0; 1200 hmp->tx_ring[i].status_n_length = 0; 1201 } 1202 /* Mark the last entry of the ring */ 1203 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing); 1204 1205 return; 1206} 1207 1208 1209#ifdef TX_CHECKSUM 1210#define csum_add(it, val) \ 1211do { \ 1212 it += (u16) (val); \ 1213 if (it & 0xffff0000) { \ 1214 it &= 0xffff; \ 1215 ++it; \ 1216 } \ 1217} while (0) 1218 /* printk("add %04x --> %04x\n", val, it); \ */ 1219 1220/* uh->len already network format, do not swap */ 1221#define pseudo_csum_udp(sum,ih,uh) do { \ 1222 sum = 0; \ 1223 csum_add(sum, (ih)->saddr >> 16); \ 1224 csum_add(sum, (ih)->saddr & 0xffff); \ 1225 csum_add(sum, (ih)->daddr >> 16); \ 1226 csum_add(sum, (ih)->daddr & 0xffff); \ 1227 csum_add(sum, __constant_htons(IPPROTO_UDP)); \ 1228 csum_add(sum, (uh)->len); \ 1229} while (0) 1230 1231/* swap len */ 1232#define pseudo_csum_tcp(sum,ih,len) do { \ 1233 sum = 0; \ 1234 csum_add(sum, (ih)->saddr >> 16); \ 1235 csum_add(sum, (ih)->saddr & 0xffff); \ 1236 csum_add(sum, (ih)->daddr >> 16); \ 1237 csum_add(sum, (ih)->daddr & 0xffff); \ 1238 csum_add(sum, __constant_htons(IPPROTO_TCP)); \ 1239 csum_add(sum, htons(len)); \ 1240} while (0) 1241#endif 1242 1243static int hamachi_start_xmit(struct sk_buff *skb, struct net_device *dev) 1244{ 1245 struct hamachi_private *hmp = dev->priv; 1246 unsigned entry; 1247 u16 status; 1248 1249 /* Ok, now make sure that the queue has space before trying to 1250 add another skbuff. if we return non-zero the scheduler 1251 should interpret this as a queue full and requeue the buffer 1252 for later. 1253 */ 1254 if (hmp->tx_full) { 1255 /* We should NEVER reach this point -KDU */ 1256 printk(KERN_WARNING "%s: Hamachi transmit queue full at slot %d.\n",dev->name, hmp->cur_tx); 1257 1258 /* Wake the potentially-idle transmit channel. */ 1259 /* If we don't need to read status, DON'T -KDU */ 1260 status=readw(dev->base_addr + TxStatus); 1261 if( !(status & 0x0001) || (status & 0x0002)) 1262 writew(0x0001, dev->base_addr + TxCmd); 1263 return 1; 1264 } 1265 1266 /* Caution: the write order is important here, set the field 1267 with the "ownership" bits last. */ 1268 1269 /* Calculate the next Tx descriptor entry. */ 1270 entry = hmp->cur_tx % TX_RING_SIZE; 1271 1272 hmp->tx_skbuff[entry] = skb; 1273 1274#ifdef TX_CHECKSUM 1275 { 1276 /* tack on checksum tag */ 1277 u32 tagval = 0; 1278 struct ethhdr *eh = (struct ethhdr *)skb->data; 1279 if (eh->h_proto == __constant_htons(ETH_P_IP)) { 1280 struct iphdr *ih = (struct iphdr *)((char *)eh + ETH_HLEN); 1281 if (ih->protocol == IPPROTO_UDP) { 1282 struct udphdr *uh 1283 = (struct udphdr *)((char *)ih + ih->ihl*4); 1284 u32 offset = ((unsigned char *)uh + 6) - skb->data; 1285 u32 pseudo; 1286 pseudo_csum_udp(pseudo, ih, uh); 1287 pseudo = htons(pseudo); 1288 printk("udp cksum was %04x, sending pseudo %04x\n", 1289 uh->check, pseudo); 1290 uh->check = 0; /* zero out uh->check before card calc */ 1291 /* 1292 * start at 14 (skip ethhdr), store at offset (uh->check), 1293 * use pseudo value given. 1294 */ 1295 tagval = (14 << 24) | (offset << 16) | pseudo; 1296 } else if (ih->protocol == IPPROTO_TCP) { 1297 printk("tcp, no auto cksum\n"); 1298 } 1299 } 1300 *(u32 *)skb_push(skb, 8) = tagval; 1301 } 1302#endif 1303 1304 hmp->tx_ring[entry].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev, 1305 skb->data, skb->len, PCI_DMA_TODEVICE)); 1306 1307 /* Hmmmm, could probably put a DescIntr on these, but the way 1308 the driver is currently coded makes Tx interrupts unnecessary 1309 since the clearing of the Tx ring is handled by the start_xmit 1310 routine. This organization helps mitigate the interrupts a 1311 bit and probably renders the max_tx_latency param useless. 1312 1313 Update: Putting a DescIntr bit on all of the descriptors and 1314 mitigating interrupt frequency with the tx_min_pkt parameter. -KDU 1315 */ 1316 if (entry >= TX_RING_SIZE-1) /* Wrap ring */ 1317 hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn | 1318 DescEndPacket | DescEndRing | DescIntr | skb->len); 1319 else 1320 hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn | 1321 DescEndPacket | DescIntr | skb->len); 1322 hmp->cur_tx++; 1323 1324 /* Non-x86 Todo: explicitly flush cache lines here. */ 1325 1326 /* Wake the potentially-idle transmit channel. */ 1327 /* If we don't need to read status, DON'T -KDU */ 1328 status=readw(dev->base_addr + TxStatus); 1329 if( !(status & 0x0001) || (status & 0x0002)) 1330 writew(0x0001, dev->base_addr + TxCmd); 1331 1332 /* Immediately before returning, let's clear as many entries as we can. */ 1333 hamachi_tx(dev); 1334 1335 /* We should kick the bottom half here, since we are not accepting 1336 * interrupts with every packet. i.e. realize that Gigabit ethernet 1337 * can transmit faster than ordinary machines can load packets; 1338 * hence, any packet that got put off because we were in the transmit 1339 * routine should IMMEDIATELY get a chance to be re-queued. -KDU 1340 */ 1341 if ((hmp->cur_tx - hmp->dirty_tx) < (TX_RING_SIZE - 4)) 1342 netif_wake_queue(dev); /* Typical path */ 1343 else { 1344 hmp->tx_full = 1; 1345 netif_stop_queue(dev); 1346 } 1347 dev->trans_start = jiffies; 1348 1349 if (hamachi_debug > 4) { 1350 printk(KERN_DEBUG "%s: Hamachi transmit frame #%d queued in slot %d.\n", 1351 dev->name, hmp->cur_tx, entry); 1352 } 1353 return 0; 1354} 1355 1356/* The interrupt handler does all of the Rx thread work and cleans up 1357 after the Tx thread. */ 1358static void hamachi_interrupt(int irq, void *dev_instance, struct pt_regs *rgs) 1359{ 1360 struct net_device *dev = dev_instance; 1361 struct hamachi_private *hmp; 1362 long ioaddr, boguscnt = max_interrupt_work; 1363 1364#ifndef final_version /* Can never occur. */ 1365 if (dev == NULL) { 1366 printk (KERN_ERR "hamachi_interrupt(): irq %d for unknown device.\n", irq); 1367 return; 1368 } 1369#endif 1370 1371 ioaddr = dev->base_addr; 1372 hmp = dev->priv; 1373 spin_lock(&hmp->lock); 1374 1375 do { 1376 u32 intr_status = readl(ioaddr + InterruptClear); 1377 1378 if (hamachi_debug > 4) 1379 printk(KERN_DEBUG "%s: Hamachi interrupt, status %4.4x.\n", 1380 dev->name, intr_status); 1381 1382 if (intr_status == 0) 1383 break; 1384 1385 if (intr_status & IntrRxDone) 1386 hamachi_rx(dev); 1387 1388 if (intr_status & IntrTxDone){ 1389 /* This code should RARELY need to execute. After all, this is 1390 * a gigabit link, it should consume packets as fast as we put 1391 * them in AND we clear the Tx ring in hamachi_start_xmit(). 1392 */ 1393 if (hmp->tx_full){ 1394 for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++){ 1395 int entry = hmp->dirty_tx % TX_RING_SIZE; 1396 struct sk_buff *skb; 1397 1398 if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn)) 1399 break; 1400 skb = hmp->tx_skbuff[entry]; 1401 /* Free the original skb. */ 1402 if (skb){ 1403 pci_unmap_single(hmp->pci_dev, 1404 hmp->tx_ring[entry].addr, 1405 skb->len, 1406 PCI_DMA_TODEVICE); 1407 dev_kfree_skb_irq(skb); 1408 hmp->tx_skbuff[entry] = 0; 1409 } 1410 hmp->tx_ring[entry].status_n_length = 0; 1411 if (entry >= TX_RING_SIZE-1) 1412 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |= 1413 cpu_to_le32(DescEndRing); 1414 hmp->stats.tx_packets++; 1415 } 1416 if (hmp->cur_tx - hmp->dirty_tx < TX_RING_SIZE - 4){ 1417 /* The ring is no longer full */ 1418 hmp->tx_full = 0; 1419 netif_wake_queue(dev); 1420 } 1421 } else { 1422 netif_wake_queue(dev); 1423 } 1424 } 1425 1426 1427 /* Abnormal error summary/uncommon events handlers. */ 1428 if (intr_status & 1429 (IntrTxPCIFault | IntrTxPCIErr | IntrRxPCIFault | IntrRxPCIErr | 1430 LinkChange | NegotiationChange | StatsMax)) 1431 hamachi_error(dev, intr_status); 1432 1433 if (--boguscnt < 0) { 1434 printk(KERN_WARNING "%s: Too much work at interrupt, status=0x%4.4x.\n", 1435 dev->name, intr_status); 1436 break; 1437 } 1438 } while (1); 1439 1440 if (hamachi_debug > 3) 1441 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n", 1442 dev->name, readl(ioaddr + IntrStatus)); 1443 1444#ifndef final_version 1445 /* Code that should never be run! Perhaps remove after testing.. */ 1446 { 1447 static int stopit = 10; 1448 if (dev->start == 0 && --stopit < 0) { 1449 printk(KERN_ERR "%s: Emergency stop, looping startup interrupt.\n", 1450 dev->name); 1451 free_irq(irq, dev); 1452 } 1453 } 1454#endif 1455 1456 spin_unlock(&hmp->lock); 1457} 1458 1459#ifdef TX_CHECKSUM 1460/* 1461 * Copied from eth_type_trans(), with reduced header, since we don't 1462 * get it on RX, only on TX. 1463 */ 1464static unsigned short hamachi_eth_type_trans(struct sk_buff *skb, 1465 struct net_device *dev) 1466{ 1467 struct ethhdr *eth; 1468 unsigned char *rawp; 1469 1470 skb->mac.raw=skb->data; 1471 skb_pull(skb,dev->hard_header_len-8); /* artificially enlarged on tx */ 1472 eth= skb->mac.ethernet; 1473 1474 if(*eth->h_dest&1) 1475 { 1476 if(memcmp(eth->h_dest,dev->broadcast, ETH_ALEN)==0) 1477 skb->pkt_type=PACKET_BROADCAST; 1478 else 1479 skb->pkt_type=PACKET_MULTICAST; 1480 } 1481 1482 /* 1483 * This ALLMULTI check should be redundant by 1.4 1484 * so don't forget to remove it. 1485 * 1486 * Seems, you forgot to remove it. All silly devices 1487 * seems to set IFF_PROMISC. 1488 */ 1489 1490 else if(dev->flags&(IFF_PROMISC/*|IFF_ALLMULTI*/)) 1491 { 1492 if(memcmp(eth->h_dest,dev->dev_addr, ETH_ALEN)) 1493 skb->pkt_type=PACKET_OTHERHOST; 1494 } 1495 1496 if (ntohs(eth->h_proto) >= 1536) 1497 return eth->h_proto; 1498 1499 rawp = skb->data; 1500 1501 /* 1502 * This is a magic hack to spot IPX packets. Older Novell breaks 1503 * the protocol design and runs IPX over 802.3 without an 802.2 LLC 1504 * layer. We look for FFFF which isn't a used 802.2 SSAP/DSAP. This 1505 * won't work for fault tolerant netware but does for the rest. 1506 */ 1507 if (*(unsigned short *)rawp == 0xFFFF) 1508 return htons(ETH_P_802_3); 1509 1510 /* 1511 * Real 802.2 LLC 1512 */ 1513 return htons(ETH_P_802_2); 1514} 1515#endif /* TX_CHECKSUM */ 1516 1517/* This routine is logically part of the interrupt handler, but seperated 1518 for clarity and better register allocation. */ 1519static int hamachi_rx(struct net_device *dev) 1520{ 1521 struct hamachi_private *hmp = dev->priv; 1522 int entry = hmp->cur_rx % RX_RING_SIZE; 1523 int boguscnt = (hmp->dirty_rx + RX_RING_SIZE) - hmp->cur_rx; 1524 1525 if (hamachi_debug > 4) { 1526 printk(KERN_DEBUG " In hamachi_rx(), entry %d status %4.4x.\n", 1527 entry, hmp->rx_ring[entry].status_n_length); 1528 } 1529 1530 /* If EOP is set on the next entry, it's a new packet. Send it up. */ 1531 while (1) { 1532 struct hamachi_desc *desc = &(hmp->rx_ring[entry]); 1533 u32 desc_status = le32_to_cpu(desc->status_n_length); 1534 u16 data_size = desc_status; /* Implicit truncate */ 1535 u8 *buf_addr; 1536 s32 frame_status; 1537 1538 if (desc_status & DescOwn) 1539 break; 1540 pci_dma_sync_single(hmp->pci_dev, desc->addr, hmp->rx_buf_sz, 1541 PCI_DMA_FROMDEVICE); 1542 buf_addr = desc_to_virt(desc->addr); 1543 frame_status = le32_to_cpu(get_unaligned((s32*)&(buf_addr[data_size - 12]))); 1544 if (hamachi_debug > 4) 1545 printk(KERN_DEBUG " hamachi_rx() status was %8.8x.\n", 1546 frame_status); 1547 if (--boguscnt < 0) 1548 break; 1549 if ( ! (desc_status & DescEndPacket)) { 1550 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned " 1551 "multiple buffers, entry %#x length %d status %4.4x!\n", 1552 dev->name, hmp->cur_rx, data_size, desc_status); 1553 printk(KERN_WARNING "%s: Oversized Ethernet frame %p vs %p.\n", 1554 dev->name, desc, &hmp->rx_ring[hmp->cur_rx % RX_RING_SIZE]); 1555 printk(KERN_WARNING "%s: Oversized Ethernet frame -- next status %x/%x last status %x.\n", 1556 dev->name, 1557 hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length & 0xffff0000, 1558 hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length & 0x0000ffff, 1559 hmp->rx_ring[(hmp->cur_rx-1) % RX_RING_SIZE].status_n_length); 1560 hmp->stats.rx_length_errors++; 1561 } /* else Omit for prototype errata??? */ 1562 if (frame_status & 0x00380000) { 1563 /* There was an error. */ 1564 if (hamachi_debug > 2) 1565 printk(KERN_DEBUG " hamachi_rx() Rx error was %8.8x.\n", 1566 frame_status); 1567 hmp->stats.rx_errors++; 1568 if (frame_status & 0x00600000) hmp->stats.rx_length_errors++; 1569 if (frame_status & 0x00080000) hmp->stats.rx_frame_errors++; 1570 if (frame_status & 0x00100000) hmp->stats.rx_crc_errors++; 1571 if (frame_status < 0) hmp->stats.rx_dropped++; 1572 } else { 1573 struct sk_buff *skb; 1574 /* Omit CRC */ 1575 u16 pkt_len = (frame_status & 0x07ff) - 4; 1576#ifdef RX_CHECKSUM 1577 u32 pfck = *(u32 *) &buf_addr[data_size - 8]; 1578#endif 1579 1580 1581#ifndef final_version 1582 if (hamachi_debug > 4) 1583 printk(KERN_DEBUG " hamachi_rx() normal Rx pkt length %d" 1584 " of %d, bogus_cnt %d.\n", 1585 pkt_len, data_size, boguscnt); 1586 if (hamachi_debug > 5) 1587 printk(KERN_DEBUG"%s: rx status %8.8x %8.8x %8.8x %8.8x %8.8x.\n", 1588 dev->name, 1589 *(s32*)&(buf_addr[data_size - 20]), 1590 *(s32*)&(buf_addr[data_size - 16]), 1591 *(s32*)&(buf_addr[data_size - 12]), 1592 *(s32*)&(buf_addr[data_size - 8]), 1593 *(s32*)&(buf_addr[data_size - 4])); 1594#endif 1595 /* Check if the packet is long enough to accept without copying 1596 to a minimally-sized skbuff. */ 1597 if (pkt_len < rx_copybreak 1598 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) { 1599#ifdef RX_CHECKSUM 1600 printk(KERN_ERR "%s: rx_copybreak non-zero " 1601 "not good with RX_CHECKSUM\n", dev->name); 1602#endif 1603 skb->dev = dev; 1604 skb_reserve(skb, 2); /* 16 byte align the IP header */ 1605 /* Call copy + cksum if available. */ 1606 eth_copy_and_sum(skb, 1607 hmp->rx_skbuff[entry]->data, pkt_len, 0); 1608 skb_put(skb, pkt_len); 1609 } else { 1610 pci_unmap_single(hmp->pci_dev, 1611 hmp->rx_ring[entry].addr, 1612 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE); 1613 skb_put(skb = hmp->rx_skbuff[entry], pkt_len); 1614 hmp->rx_skbuff[entry] = NULL; 1615 } 1616#ifdef TX_CHECKSUM 1617 /* account for extra TX hard_header bytes */ 1618 skb->protocol = hamachi_eth_type_trans(skb, dev); 1619#else 1620 skb->protocol = eth_type_trans(skb, dev); 1621#endif 1622 1623 1624#ifdef RX_CHECKSUM 1625 /* TCP or UDP on ipv4, DIX encoding */ 1626 if (pfck>>24 == 0x91 || pfck>>24 == 0x51) { 1627 struct iphdr *ih = (struct iphdr *) skb->data; 1628 /* Check that IP packet is at least 46 bytes, otherwise, 1629 * there may be pad bytes included in the hardware checksum. 1630 * This wouldn't happen if everyone padded with 0. 1631 */ 1632 if (ntohs(ih->tot_len) >= 46){ 1633 /* don't worry about frags */ 1634 if (!(ih->frag_off & __constant_htons(IP_MF|IP_OFFSET))) { 1635 u32 inv = *(u32 *) &buf_addr[data_size - 16]; 1636 u32 *p = (u32 *) &buf_addr[data_size - 20]; 1637 register u32 crc, p_r, p_r1; 1638 1639 if (inv & 4) { 1640 inv &= ~4; 1641 --p; 1642 } 1643 p_r = *p; 1644 p_r1 = *(p-1); 1645 switch (inv) { 1646 case 0: 1647 crc = (p_r & 0xffff) + (p_r >> 16); 1648 break; 1649 case 1: 1650 crc = (p_r >> 16) + (p_r & 0xffff) 1651 + (p_r1 >> 16 & 0xff00); 1652 break; 1653 case 2: 1654 crc = p_r + (p_r1 >> 16); 1655 break; 1656 case 3: 1657 crc = p_r + (p_r1 & 0xff00) + (p_r1 >> 16); 1658 break; 1659 default: /*NOTREACHED*/ crc = 0; 1660 } 1661 if (crc & 0xffff0000) { 1662 crc &= 0xffff; 1663 ++crc; 1664 } 1665 /* tcp/udp will add in pseudo */ 1666 skb->csum = ntohs(pfck & 0xffff); 1667 if (skb->csum > crc) 1668 skb->csum -= crc; 1669 else 1670 skb->csum += (~crc & 0xffff); 1671 /* 1672 * could do the pseudo myself and return 1673 * CHECKSUM_UNNECESSARY 1674 */ 1675 skb->ip_summed = CHECKSUM_HW; 1676 } 1677 } 1678 } 1679#endif /* RX_CHECKSUM */ 1680 1681 netif_rx(skb); 1682 dev->last_rx = jiffies; 1683 hmp->stats.rx_packets++; 1684 } 1685 entry = (++hmp->cur_rx) % RX_RING_SIZE; 1686 } 1687 1688 /* Refill the Rx ring buffers. */ 1689 for (; hmp->cur_rx - hmp->dirty_rx > 0; hmp->dirty_rx++) { 1690 struct hamachi_desc *desc; 1691 1692 entry = hmp->dirty_rx % RX_RING_SIZE; 1693 desc = &(hmp->rx_ring[entry]); 1694 if (hmp->rx_skbuff[entry] == NULL) { 1695 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz); 1696 1697 hmp->rx_skbuff[entry] = skb; 1698 if (skb == NULL) 1699 break; /* Better luck next round. */ 1700 skb->dev = dev; /* Mark as being used by this device. */ 1701 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ 1702 desc->addr = cpu_to_leXX(pci_map_single(hmp->pci_dev, 1703 skb->tail, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE)); 1704 } 1705 desc->status_n_length = cpu_to_le32(hmp->rx_buf_sz); 1706 if (entry >= RX_RING_SIZE-1) 1707 desc->status_n_length |= cpu_to_le32(DescOwn | 1708 DescEndPacket | DescEndRing | DescIntr); 1709 else 1710 desc->status_n_length |= cpu_to_le32(DescOwn | 1711 DescEndPacket | DescIntr); 1712 } 1713 1714 /* Restart Rx engine if stopped. */ 1715 /* If we don't need to check status, don't. -KDU */ 1716 if (readw(dev->base_addr + RxStatus) & 0x0002) 1717 writew(0x0001, dev->base_addr + RxCmd); 1718 1719 return 0; 1720} 1721 1722/* This is more properly named "uncommon interrupt events", as it covers more 1723 than just errors. */ 1724static void hamachi_error(struct net_device *dev, int intr_status) 1725{ 1726 long ioaddr = dev->base_addr; 1727 struct hamachi_private *hmp = dev->priv; 1728 1729 if (intr_status & (LinkChange|NegotiationChange)) { 1730 if (hamachi_debug > 1) 1731 printk(KERN_INFO "%s: Link changed: AutoNegotiation Ctrl" 1732 " %4.4x, Status %4.4x %4.4x Intr status %4.4x.\n", 1733 dev->name, readw(ioaddr + 0x0E0), readw(ioaddr + 0x0E2), 1734 readw(ioaddr + ANLinkPartnerAbility), 1735 readl(ioaddr + IntrStatus)); 1736 if (readw(ioaddr + ANStatus) & 0x20) 1737 writeb(0x01, ioaddr + LEDCtrl); 1738 else 1739 writeb(0x03, ioaddr + LEDCtrl); 1740 } 1741 if (intr_status & StatsMax) { 1742 hamachi_get_stats(dev); 1743 /* Read the overflow bits to clear. */ 1744 readl(ioaddr + 0x370); 1745 readl(ioaddr + 0x3F0); 1746 } 1747 if ((intr_status & ~(LinkChange|StatsMax|NegotiationChange|IntrRxDone|IntrTxDone)) 1748 && hamachi_debug) 1749 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n", 1750 dev->name, intr_status); 1751 /* Hmmmmm, it's not clear how to recover from PCI faults. */ 1752 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault)) 1753 hmp->stats.tx_fifo_errors++; 1754 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault)) 1755 hmp->stats.rx_fifo_errors++; 1756} 1757 1758static int hamachi_close(struct net_device *dev) 1759{ 1760 long ioaddr = dev->base_addr; 1761 struct hamachi_private *hmp = dev->priv; 1762 struct sk_buff *skb; 1763 int i; 1764 1765 netif_stop_queue(dev); 1766 1767 if (hamachi_debug > 1) { 1768 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x Rx %4.4x Int %2.2x.\n", 1769 dev->name, readw(ioaddr + TxStatus), 1770 readw(ioaddr + RxStatus), readl(ioaddr + IntrStatus)); 1771 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n", 1772 dev->name, hmp->cur_tx, hmp->dirty_tx, hmp->cur_rx, hmp->dirty_rx); 1773 } 1774 1775 /* Disable interrupts by clearing the interrupt mask. */ 1776 writel(0x0000, ioaddr + InterruptEnable); 1777 1778 /* Stop the chip's Tx and Rx processes. */ 1779 writel(2, ioaddr + RxCmd); 1780 writew(2, ioaddr + TxCmd); 1781 1782#ifdef __i386__ 1783 if (hamachi_debug > 2) { 1784 printk("\n"KERN_DEBUG" Tx ring at %8.8x:\n", 1785 (int)hmp->tx_ring_dma); 1786 for (i = 0; i < TX_RING_SIZE; i++) 1787 printk(" %c #%d desc. %8.8x %8.8x.\n", 1788 readl(ioaddr + TxCurPtr) == (long)&hmp->tx_ring[i] ? '>' : ' ', 1789 i, hmp->tx_ring[i].status_n_length, hmp->tx_ring[i].addr); 1790 printk("\n"KERN_DEBUG " Rx ring %8.8x:\n", 1791 (int)hmp->rx_ring_dma); 1792 for (i = 0; i < RX_RING_SIZE; i++) { 1793 printk(KERN_DEBUG " %c #%d desc. %4.4x %8.8x\n", 1794 readl(ioaddr + RxCurPtr) == (long)&hmp->rx_ring[i] ? '>' : ' ', 1795 i, hmp->rx_ring[i].status_n_length, hmp->rx_ring[i].addr); 1796 if (hamachi_debug > 6) { 1797 if (*(u8*)hmp->rx_skbuff[i]->tail != 0x69) { 1798 u16 *addr = (u16 *) 1799 hmp->rx_skbuff[i]->tail; 1800 int j; 1801 1802 for (j = 0; j < 0x50; j++) 1803 printk(" %4.4x", addr[j]); 1804 printk("\n"); 1805 } 1806 } 1807 } 1808 } 1809#endif /* __i386__ debugging only */ 1810 1811 free_irq(dev->irq, dev); 1812 1813 del_timer_sync(&hmp->timer); 1814 1815 /* Free all the skbuffs in the Rx queue. */ 1816 for (i = 0; i < RX_RING_SIZE; i++) { 1817 skb = hmp->rx_skbuff[i]; 1818 hmp->rx_ring[i].status_n_length = 0; 1819 hmp->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */ 1820 if (skb) { 1821 pci_unmap_single(hmp->pci_dev, 1822 hmp->rx_ring[i].addr, hmp->rx_buf_sz, 1823 PCI_DMA_FROMDEVICE); 1824 dev_kfree_skb(skb); 1825 hmp->rx_skbuff[i] = 0; 1826 } 1827 } 1828 for (i = 0; i < TX_RING_SIZE; i++) { 1829 skb = hmp->tx_skbuff[i]; 1830 if (skb) { 1831 pci_unmap_single(hmp->pci_dev, 1832 hmp->tx_ring[i].addr, skb->len, 1833 PCI_DMA_TODEVICE); 1834 dev_kfree_skb(skb); 1835 hmp->tx_skbuff[i] = 0; 1836 } 1837 } 1838 1839 writeb(0x00, ioaddr + LEDCtrl); 1840 1841 return 0; 1842} 1843 1844static struct net_device_stats *hamachi_get_stats(struct net_device *dev) 1845{ 1846 long ioaddr = dev->base_addr; 1847 struct hamachi_private *hmp = dev->priv; 1848 1849 /* We should lock this segment of code for SMP eventually, although 1850 the vulnerability window is very small and statistics are 1851 non-critical. */ 1852 /* Ok, what goes here? This appears to be stuck at 21 packets 1853 according to ifconfig. It does get incremented in hamachi_tx(), 1854 so I think I'll comment it out here and see if better things 1855 happen. 1856 */ 1857 /* hmp->stats.tx_packets = readl(ioaddr + 0x000); */ 1858 1859 hmp->stats.rx_bytes = readl(ioaddr + 0x330); /* Total Uni+Brd+Multi */ 1860 hmp->stats.tx_bytes = readl(ioaddr + 0x3B0); /* Total Uni+Brd+Multi */ 1861 hmp->stats.multicast = readl(ioaddr + 0x320); /* Multicast Rx */ 1862 1863 hmp->stats.rx_length_errors = readl(ioaddr + 0x368); /* Over+Undersized */ 1864 hmp->stats.rx_over_errors = readl(ioaddr + 0x35C); /* Jabber */ 1865 hmp->stats.rx_crc_errors = readl(ioaddr + 0x360); /* Jabber */ 1866 hmp->stats.rx_frame_errors = readl(ioaddr + 0x364); /* Symbol Errs */ 1867 hmp->stats.rx_missed_errors = readl(ioaddr + 0x36C); /* Dropped */ 1868 1869 return &hmp->stats; 1870} 1871 1872static void set_rx_mode(struct net_device *dev) 1873{ 1874 long ioaddr = dev->base_addr; 1875 1876 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 1877 /* Unconditionally log net taps. */ 1878 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name); 1879 writew(0x000F, ioaddr + AddrMode); 1880 } else if ((dev->mc_count > 63) || (dev->flags & IFF_ALLMULTI)) { 1881 /* Too many to match, or accept all multicasts. */ 1882 writew(0x000B, ioaddr + AddrMode); 1883 } else if (dev->mc_count > 0) { /* Must use the CAM filter. */ 1884 struct dev_mc_list *mclist; 1885 int i; 1886 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; 1887 i++, mclist = mclist->next) { 1888 writel(*(u32*)(mclist->dmi_addr), ioaddr + 0x100 + i*8); 1889 writel(0x20000 | (*(u16*)&mclist->dmi_addr[4]), 1890 ioaddr + 0x104 + i*8); 1891 } 1892 /* Clear remaining entries. */ 1893 for (; i < 64; i++) 1894 writel(0, ioaddr + 0x104 + i*8); 1895 writew(0x0003, ioaddr + AddrMode); 1896 } else { /* Normal, unicast/broadcast-only mode. */ 1897 writew(0x0001, ioaddr + AddrMode); 1898 } 1899} 1900 1901static int netdev_ethtool_ioctl(struct net_device *dev, void *useraddr) 1902{ 1903 struct hamachi_private *hmp = dev->priv; 1904 u32 ethcmd; 1905 1906 if (copy_from_user(ðcmd, useraddr, sizeof(ethcmd))) 1907 return -EFAULT; 1908 1909 switch (ethcmd) { 1910 case ETHTOOL_GDRVINFO: { 1911 struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO}; 1912 strcpy(info.driver, DRV_NAME); 1913 strcpy(info.version, DRV_VERSION); 1914 strcpy(info.bus_info, hmp->pci_dev->slot_name); 1915 if (copy_to_user(useraddr, &info, sizeof(info))) 1916 return -EFAULT; 1917 return 0; 1918 } 1919 1920 } 1921 1922 return -EOPNOTSUPP; 1923} 1924 1925static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1926{ 1927 long ioaddr = dev->base_addr; 1928 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data; 1929 1930 switch(cmd) { 1931 case SIOCETHTOOL: 1932 return netdev_ethtool_ioctl(dev, (void *) rq->ifr_data); 1933 case SIOCGMIIPHY: /* Get address of MII PHY in use. */ 1934 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */ 1935 data->phy_id = ((struct hamachi_private *)dev->priv)->phys[0] & 0x1f; 1936 /* Fall Through */ 1937 1938 case SIOCGMIIREG: /* Read MII PHY register. */ 1939 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */ 1940 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f); 1941 return 0; 1942 1943 case SIOCSMIIREG: /* Write MII PHY register. */ 1944 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */ 1945 /* TODO: Check the sequencing of this. Might need to stop and 1946 * restart Rx and Tx engines. -KDU 1947 */ 1948 if (!capable(CAP_NET_ADMIN)) 1949 return -EPERM; 1950 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in); 1951 return 0; 1952 case SIOCDEVPRIVATE+3: { /* set rx,tx intr params */ 1953 u32 *d = (u32 *)&rq->ifr_data; 1954 /* Should add this check here or an ordinary user can do nasty 1955 * things. -KDU 1956 * 1957 * TODO: Shut down the Rx and Tx engines while doing this. 1958 */ 1959 if (!capable(CAP_NET_ADMIN)) 1960 return -EPERM; 1961 writel(d[0], dev->base_addr + TxIntrCtrl); 1962 writel(d[1], dev->base_addr + RxIntrCtrl); 1963 printk(KERN_NOTICE "%s: tx %08x, rx %08x intr\n", dev->name, 1964 (u32) readl(dev->base_addr + TxIntrCtrl), 1965 (u32) readl(dev->base_addr + RxIntrCtrl)); 1966 return 0; 1967 } 1968 default: 1969 return -EOPNOTSUPP; 1970 } 1971} 1972 1973 1974static void __devexit hamachi_remove_one (struct pci_dev *pdev) 1975{ 1976 struct net_device *dev = pci_get_drvdata(pdev); 1977 1978 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */ 1979 if (dev) { 1980 struct hamachi_private *hmp = dev->priv; 1981 1982 pci_free_consistent(pdev, RX_TOTAL_SIZE, hmp->rx_ring, 1983 hmp->rx_ring_dma); 1984 pci_free_consistent(pdev, TX_TOTAL_SIZE, hmp->tx_ring, 1985 hmp->tx_ring_dma); 1986 unregister_netdev(dev); 1987 iounmap((char *)dev->base_addr); 1988 kfree(dev); 1989 pci_release_regions(pdev); 1990 pci_set_drvdata(pdev, NULL); 1991 } 1992} 1993 1994static struct pci_device_id hamachi_pci_tbl[] __initdata = { 1995 { 0x1318, 0x0911, PCI_ANY_ID, PCI_ANY_ID, }, 1996 { 0, } 1997}; 1998MODULE_DEVICE_TABLE(pci, hamachi_pci_tbl); 1999 2000static struct pci_driver hamachi_driver = { 2001 name: DRV_NAME, 2002 id_table: hamachi_pci_tbl, 2003 probe: hamachi_init_one, 2004 remove: __devexit_p(hamachi_remove_one), 2005}; 2006 2007static int __init hamachi_init (void) 2008{ 2009/* when a module, this is printed whether or not devices are found in probe */ 2010#ifdef MODULE 2011 printk(version); 2012#endif 2013 if (pci_register_driver(&hamachi_driver) > 0) 2014 return 0; 2015 pci_unregister_driver(&hamachi_driver); 2016 return -ENODEV; 2017} 2018 2019static void __exit hamachi_exit (void) 2020{ 2021 pci_unregister_driver(&hamachi_driver); 2022} 2023 2024 2025module_init(hamachi_init); 2026module_exit(hamachi_exit); 2027