1 2 3#include <linux/config.h> 4#include <linux/types.h> 5#include <linux/kernel.h> 6#include <linux/delay.h> 7#include <linux/timer.h> 8#include <linux/mm.h> 9#include <linux/ioport.h> 10#include <linux/blkdev.h> 11#include <linux/hdreg.h> 12 13#include <linux/interrupt.h> 14#include <linux/pci.h> 15#include <linux/init.h> 16#include <linux/ide.h> 17 18#include <asm/uaccess.h> 19#include <asm/io.h> 20#include <asm/irq.h> 21 22#include "ide_modes.h" 23 24#define DISPLAY_HPT366_TIMINGS 25 26/* various tuning parameters */ 27#define HPT_RESET_STATE_ENGINE 28/*#define HPT_DELAY_INTERRUPT*/ 29/*#define HPT_SERIALIZE_IO*/ 30 31#if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) 32#include <linux/stat.h> 33#include <linux/proc_fs.h> 34#endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */ 35 36extern char *ide_dmafunc_verbose(ide_dma_action_t dmafunc); 37 38const char *quirk_drives[] = { 39 "QUANTUM FIREBALLlct08 08", 40 "QUANTUM FIREBALLP KA6.4", 41 "QUANTUM FIREBALLP LM20.4", 42 "QUANTUM FIREBALLP LM20.5", 43 NULL 44}; 45 46const char *bad_ata100_5[] = { 47 "IBM-DTLA-307075", 48 "IBM-DTLA-307060", 49 "IBM-DTLA-307045", 50 "IBM-DTLA-307030", 51 "IBM-DTLA-307020", 52 "IBM-DTLA-307015", 53 "IBM-DTLA-305040", 54 "IBM-DTLA-305030", 55 "IBM-DTLA-305020", 56 "IC35L010AVER07-0", 57 "IC35L020AVER07-0", 58 "IC35L030AVER07-0", 59 "IC35L040AVER07-0", 60 "IC35L060AVER07-0", 61 "WDC AC310200R", 62 NULL 63}; 64 65const char *bad_ata66_4[] = { 66 "IBM-DTLA-307075", 67 "IBM-DTLA-307060", 68 "IBM-DTLA-307045", 69 "IBM-DTLA-307030", 70 "IBM-DTLA-307020", 71 "IBM-DTLA-307015", 72 "IBM-DTLA-305040", 73 "IBM-DTLA-305030", 74 "IBM-DTLA-305020", 75 "IC35L010AVER07-0", 76 "IC35L020AVER07-0", 77 "IC35L030AVER07-0", 78 "IC35L040AVER07-0", 79 "IC35L060AVER07-0", 80 "WDC AC310200R", 81 NULL 82}; 83 84const char *bad_ata66_3[] = { 85 "WDC AC310200R", 86 NULL 87}; 88 89const char *bad_ata33[] = { 90 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", 91 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", 92 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", 93 "Maxtor 90510D4", 94 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", 95 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", 96 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", 97 NULL 98}; 99 100struct chipset_bus_clock_list_entry { 101 byte xfer_speed; 102 unsigned int chipset_settings; 103}; 104 105/* key for bus clock timings 106 * bit 107 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW 108 * DMA. cycles = value + 1 109 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW 110 * DMA. cycles = value + 1 111 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file 112 * register access. 113 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file 114 * register access. 115 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer. 116 * during task file register access. 117 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA 118 * xfer. 119 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task 120 * register access. 121 * 28 UDMA enable 122 * 29 DMA enable 123 * 30 PIO_MST enable. if set, the chip is in bus master mode during 124 * PIO. 125 * 31 FIFO enable. 126 */ 127struct chipset_bus_clock_list_entry forty_base [] = { 128 129 { XFER_UDMA_4, 0x900fd943 }, 130 { XFER_UDMA_3, 0x900ad943 }, 131 { XFER_UDMA_2, 0x900bd943 }, 132 { XFER_UDMA_1, 0x9008d943 }, 133 { XFER_UDMA_0, 0x9008d943 }, 134 135 { XFER_MW_DMA_2, 0xa008d943 }, 136 { XFER_MW_DMA_1, 0xa010d955 }, 137 { XFER_MW_DMA_0, 0xa010d9fc }, 138 139 { XFER_PIO_4, 0xc008d963 }, 140 { XFER_PIO_3, 0xc010d974 }, 141 { XFER_PIO_2, 0xc010d997 }, 142 { XFER_PIO_1, 0xc010d9c7 }, 143 { XFER_PIO_0, 0xc018d9d9 }, 144 { 0, 0x0120d9d9 } 145}; 146 147struct chipset_bus_clock_list_entry thirty_three_base [] = { 148 149 { XFER_UDMA_4, 0x90c9a731 }, 150 { XFER_UDMA_3, 0x90cfa731 }, 151 { XFER_UDMA_2, 0x90caa731 }, 152 { XFER_UDMA_1, 0x90cba731 }, 153 { XFER_UDMA_0, 0x90c8a731 }, 154 155 { XFER_MW_DMA_2, 0xa0c8a731 }, 156 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */ 157 { XFER_MW_DMA_0, 0xa0c8a797 }, 158 159 { XFER_PIO_4, 0xc0c8a731 }, 160 { XFER_PIO_3, 0xc0c8a742 }, 161 { XFER_PIO_2, 0xc0d0a753 }, 162 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */ 163 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */ 164 { 0, 0x0120a7a7 } 165}; 166 167struct chipset_bus_clock_list_entry twenty_five_base [] = { 168 169 { XFER_UDMA_4, 0x90c98521 }, 170 { XFER_UDMA_3, 0x90cf8521 }, 171 { XFER_UDMA_2, 0x90cf8521 }, 172 { XFER_UDMA_1, 0x90cb8521 }, 173 { XFER_UDMA_0, 0x90cb8521 }, 174 175 { XFER_MW_DMA_2, 0xa0ca8521 }, 176 { XFER_MW_DMA_1, 0xa0ca8532 }, 177 { XFER_MW_DMA_0, 0xa0ca8575 }, 178 179 { XFER_PIO_4, 0xc0ca8521 }, 180 { XFER_PIO_3, 0xc0ca8532 }, 181 { XFER_PIO_2, 0xc0ca8542 }, 182 { XFER_PIO_1, 0xc0d08572 }, 183 { XFER_PIO_0, 0xc0d08585 }, 184 { 0, 0x01208585 } 185}; 186 187/* these are the current (4 sep 2001) timings from highpoint */ 188struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = { 189 { XFER_UDMA_5, 0x12446231 }, 190 { XFER_UDMA_4, 0x12446231 }, 191 { XFER_UDMA_3, 0x126c6231 }, 192 { XFER_UDMA_2, 0x12486231 }, 193 { XFER_UDMA_1, 0x124c6233 }, 194 { XFER_UDMA_0, 0x12506297 }, 195 196 { XFER_MW_DMA_2, 0x22406c31 }, 197 { XFER_MW_DMA_1, 0x22406c33 }, 198 { XFER_MW_DMA_0, 0x22406c97 }, 199 200 { XFER_PIO_4, 0x06414e31 }, 201 { XFER_PIO_3, 0x06414e42 }, 202 { XFER_PIO_2, 0x06414e53 }, 203 { XFER_PIO_1, 0x06814e93 }, 204 { XFER_PIO_0, 0x06814ea7 }, 205 { 0, 0x06814ea7 } 206}; 207 208/* 2x 33MHz timings */ 209struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = { 210 { XFER_UDMA_5, 0x1488e673 }, 211 { XFER_UDMA_4, 0x1488e673 }, 212 { XFER_UDMA_3, 0x1498e673 }, 213 { XFER_UDMA_2, 0x1490e673 }, 214 { XFER_UDMA_1, 0x1498e677 }, 215 { XFER_UDMA_0, 0x14a0e73f }, 216 217 { XFER_MW_DMA_2, 0x2480fa73 }, 218 { XFER_MW_DMA_1, 0x2480fa77 }, 219 { XFER_MW_DMA_0, 0x2480fb3f }, 220 221 { XFER_PIO_4, 0x0c82be73 }, 222 { XFER_PIO_3, 0x0c82be95 }, 223 { XFER_PIO_2, 0x0c82beb7 }, 224 { XFER_PIO_1, 0x0d02bf37 }, 225 { XFER_PIO_0, 0x0d02bf5f }, 226 { 0, 0x0d02bf5f } 227}; 228 229struct chipset_bus_clock_list_entry fifty_base_hpt370[] = { 230 { XFER_UDMA_5, 0x12848242 }, 231 { XFER_UDMA_4, 0x12ac8242 }, 232 { XFER_UDMA_3, 0x128c8242 }, 233 { XFER_UDMA_2, 0x120c8242 }, 234 { XFER_UDMA_1, 0x12148254 }, 235 { XFER_UDMA_0, 0x121882ea }, 236 237 { XFER_MW_DMA_2, 0x22808242 }, 238 { XFER_MW_DMA_1, 0x22808254 }, 239 { XFER_MW_DMA_0, 0x228082ea }, 240 241 { XFER_PIO_4, 0x0a81f442 }, 242 { XFER_PIO_3, 0x0a81f443 }, 243 { XFER_PIO_2, 0x0a81f454 }, 244 { XFER_PIO_1, 0x0ac1f465 }, 245 { XFER_PIO_0, 0x0ac1f48a }, 246 { 0, 0x0ac1f48a } 247}; 248 249#define HPT366_DEBUG_DRIVE_INFO 0 250#define HPT370_ALLOW_ATA100_5 1 251#define HPT366_ALLOW_ATA66_4 1 252#define HPT366_ALLOW_ATA66_3 1 253#define HPT366_MAX_DEVS 8 254 255#define F_LOW_PCI_33 0x23 256#define F_LOW_PCI_40 0x29 257#define F_LOW_PCI_50 0x2d 258#define F_LOW_PCI_66 0x42 259 260static struct pci_dev *hpt_devs[HPT366_MAX_DEVS]; 261static int n_hpt_devs; 262 263static unsigned int pci_rev_check_hpt3xx(struct pci_dev *dev); 264static unsigned int pci_rev2_check_hpt3xx(struct pci_dev *dev); 265byte hpt366_proc = 0; 266byte hpt363_shared_irq; 267byte hpt363_shared_pin; 268extern char *ide_xfer_verbose (byte xfer_rate); 269 270#if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) 271static int hpt366_get_info(char *, char **, off_t, int); 272extern int (*hpt366_display_info)(char *, char **, off_t, int); /* ide-proc.c */ 273extern char *ide_media_verbose(ide_drive_t *); 274 275static int hpt366_get_info (char *buffer, char **addr, off_t offset, int count) 276{ 277 char *p = buffer; 278 char *chipset_nums[] = {"366", "366", "368", "370", "370A"}; 279 int i; 280 281 p += sprintf(p, "\n " 282 "HighPoint HPT366/368/370\n"); 283 for (i = 0; i < n_hpt_devs; i++) { 284 struct pci_dev *dev = hpt_devs[i]; 285 unsigned long iobase = dev->resource[4].start; 286 u32 class_rev; 287 u8 c0, c1; 288 289 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 290 class_rev &= 0xff; 291 292 p += sprintf(p, "\nController: %d\n", i); 293 p += sprintf(p, "Chipset: HPT%s\n", chipset_nums[class_rev]); 294 p += sprintf(p, "--------------- Primary Channel " 295 "--------------- Secondary Channel " 296 "--------------\n"); 297 298 /* get the bus master status registers */ 299 c0 = inb_p(iobase + 0x2); 300 c1 = inb_p(iobase + 0xa); 301 p += sprintf(p, "Enabled: %s" 302 " %s\n", 303 (c0 & 0x80) ? "no" : "yes", 304 (c1 & 0x80) ? "no" : "yes"); 305 306 if (pci_rev_check_hpt3xx(dev)) { 307 u8 cbl; 308 cbl = inb_p(iobase + 0x7b); 309 outb_p(cbl | 1, iobase + 0x7b); 310 outb_p(cbl & ~1, iobase + 0x7b); 311 cbl = inb_p(iobase + 0x7a); 312 p += sprintf(p, "Cable: ATA-%d" 313 " ATA-%d\n", 314 (cbl & 0x02) ? 33 : 66, 315 (cbl & 0x01) ? 33 : 66); 316 p += sprintf(p, "\n"); 317 } 318 319 p += sprintf(p, "--------------- drive0 --------- drive1 " 320 "------- drive0 ---------- drive1 -------\n"); 321 p += sprintf(p, "DMA capable: %s %s" 322 " %s %s\n", 323 (c0 & 0x20) ? "yes" : "no ", 324 (c0 & 0x40) ? "yes" : "no ", 325 (c1 & 0x20) ? "yes" : "no ", 326 (c1 & 0x40) ? "yes" : "no "); 327 328 { 329 u8 c2, c3; 330 /* older revs don't have these registers mapped 331 * into io space */ 332 pci_read_config_byte(dev, 0x43, &c0); 333 pci_read_config_byte(dev, 0x47, &c1); 334 pci_read_config_byte(dev, 0x4b, &c2); 335 pci_read_config_byte(dev, 0x4f, &c3); 336 337 p += sprintf(p, "Mode: %s %s" 338 " %s %s\n", 339 (c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " : 340 (c0 & 0x80) ? "PIO " : "off ", 341 (c1 & 0x10) ? "UDMA" : (c1 & 0x20) ? "DMA " : 342 (c1 & 0x80) ? "PIO " : "off ", 343 (c2 & 0x10) ? "UDMA" : (c2 & 0x20) ? "DMA " : 344 (c2 & 0x80) ? "PIO " : "off ", 345 (c3 & 0x10) ? "UDMA" : (c3 & 0x20) ? "DMA " : 346 (c3 & 0x80) ? "PIO " : "off "); 347 } 348 } 349 p += sprintf(p, "\n"); 350 351 return p-buffer;/* => must be less than 4k! */ 352} 353#endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */ 354 355static unsigned int pci_rev_check_hpt3xx (struct pci_dev *dev) 356{ 357 unsigned int class_rev; 358 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 359 class_rev &= 0xff; 360 return ((int) (class_rev > 0x02) ? 1 : 0); 361} 362 363static unsigned int pci_rev2_check_hpt3xx (struct pci_dev *dev) 364{ 365 unsigned int class_rev; 366 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 367 class_rev &= 0xff; 368 return ((int) (class_rev > 0x01) ? 1 : 0); 369} 370 371static int check_in_drive_lists (ide_drive_t *drive, const char **list) 372{ 373 struct hd_driveid *id = drive->id; 374 375 if (quirk_drives == list) { 376 while (*list) { 377 if (strstr(id->model, *list++)) { 378 return 1; 379 } 380 } 381 } else { 382 while (*list) { 383 if (!strcmp(*list++,id->model)) { 384 return 1; 385 } 386 } 387 } 388 return 0; 389} 390 391static unsigned int pci_bus_clock_list (byte speed, struct chipset_bus_clock_list_entry * chipset_table) 392{ 393 for ( ; chipset_table->xfer_speed ; chipset_table++) 394 if (chipset_table->xfer_speed == speed) { 395 return chipset_table->chipset_settings; 396 } 397 return chipset_table->chipset_settings; 398} 399 400static void hpt366_tune_chipset (ide_drive_t *drive, byte speed) 401{ 402 byte regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40; 403 byte regfast = (HWIF(drive)->channel) ? 0x55 : 0x51; 404 /* 405 * since the channel is always 0 it does not matter. 406 */ 407 408 unsigned int reg1 = 0; 409 unsigned int reg2 = 0; 410 byte drive_fast = 0; 411 412 /* 413 * Disable the "fast interrupt" prediction. 414 */ 415 pci_read_config_byte(HWIF(drive)->pci_dev, regfast, &drive_fast); 416 if (drive_fast & 0x02) 417 pci_write_config_byte(HWIF(drive)->pci_dev, regfast, drive_fast & ~0x20); 418 419 pci_read_config_dword(HWIF(drive)->pci_dev, regtime, ®1); 420 /* detect bus speed by looking at control reg timing: */ 421 switch((reg1 >> 8) & 7) { 422 case 5: 423 reg2 = pci_bus_clock_list(speed, forty_base); 424 break; 425 case 9: 426 reg2 = pci_bus_clock_list(speed, twenty_five_base); 427 break; 428 default: 429 case 7: 430 reg2 = pci_bus_clock_list(speed, thirty_three_base); 431 break; 432 } 433 /* 434 * Disable on-chip PIO FIFO/buffer (to avoid problems handling I/O errors later) 435 */ 436 if (speed >= XFER_MW_DMA_0) { 437 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000); 438 } else { 439 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000); 440 } 441 reg2 &= ~0x80000000; 442 443 pci_write_config_dword(HWIF(drive)->pci_dev, regtime, reg2); 444} 445 446static void hpt370_tune_chipset (ide_drive_t *drive, byte speed) 447{ 448 byte regfast = (HWIF(drive)->channel) ? 0x55 : 0x51; 449 unsigned int list_conf = 0; 450 unsigned int drive_conf = 0; 451 unsigned int conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000; 452 byte drive_pci = 0x40 + (drive->dn * 4); 453 byte new_fast, drive_fast = 0; 454 struct pci_dev *dev = HWIF(drive)->pci_dev; 455 456 /* 457 * Disable the "fast interrupt" prediction. 458 * don't holdoff on interrupts. (== 0x01 despite what the docs say) 459 */ 460 pci_read_config_byte(dev, regfast, &drive_fast); 461 new_fast = drive_fast; 462 if (new_fast & 0x02) 463 new_fast &= ~0x02; 464 465#ifdef HPT_DELAY_INTERRUPT 466 if (new_fast & 0x01) 467 new_fast &= ~0x01; 468#else 469 if ((new_fast & 0x01) == 0) 470 new_fast |= 0x01; 471#endif 472 if (new_fast != drive_fast) 473 pci_write_config_byte(HWIF(drive)->pci_dev, regfast, new_fast); 474 475 list_conf = pci_bus_clock_list(speed, 476 (struct chipset_bus_clock_list_entry *) 477 dev->sysdata); 478 479 pci_read_config_dword(dev, drive_pci, &drive_conf); 480 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask); 481 482 if (speed < XFER_MW_DMA_0) { 483 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */ 484 } 485 486 pci_write_config_dword(dev, drive_pci, list_conf); 487} 488 489static int hpt3xx_tune_chipset (ide_drive_t *drive, byte speed) 490{ 491 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0)) 492 return -1; 493 494 if (!drive->init_speed) 495 drive->init_speed = speed; 496 497 if (pci_rev_check_hpt3xx(HWIF(drive)->pci_dev)) { 498 hpt370_tune_chipset(drive, speed); 499 } else { 500 hpt366_tune_chipset(drive, speed); 501 } 502 drive->current_speed = speed; 503 return ((int) ide_config_drive_speed(drive, speed)); 504} 505 506static void config_chipset_for_pio (ide_drive_t *drive) 507{ 508 unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90}; 509 unsigned short xfer_pio = drive->id->eide_pio_modes; 510 byte timing, speed, pio; 511 512 pio = ide_get_best_pio_mode(drive, 255, 5, NULL); 513 514 if (xfer_pio> 4) 515 xfer_pio = 0; 516 517 if (drive->id->eide_pio_iordy > 0) { 518 for (xfer_pio = 5; 519 xfer_pio>0 && 520 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio]; 521 xfer_pio--); 522 } else { 523 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 : 524 (drive->id->eide_pio_modes & 2) ? 0x04 : 525 (drive->id->eide_pio_modes & 1) ? 0x03 : 526 (drive->id->tPIO & 2) ? 0x02 : 527 (drive->id->tPIO & 1) ? 0x01 : xfer_pio; 528 } 529 530 timing = (xfer_pio >= pio) ? xfer_pio : pio; 531 532 switch(timing) { 533 case 4: speed = XFER_PIO_4;break; 534 case 3: speed = XFER_PIO_3;break; 535 case 2: speed = XFER_PIO_2;break; 536 case 1: speed = XFER_PIO_1;break; 537 default: 538 speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW; 539 break; 540 } 541 (void) hpt3xx_tune_chipset(drive, speed); 542} 543 544static void hpt3xx_tune_drive (ide_drive_t *drive, byte pio) 545{ 546 byte speed; 547 switch(pio) { 548 case 4: speed = XFER_PIO_4;break; 549 case 3: speed = XFER_PIO_3;break; 550 case 2: speed = XFER_PIO_2;break; 551 case 1: speed = XFER_PIO_1;break; 552 default: speed = XFER_PIO_0;break; 553 } 554 (void) hpt3xx_tune_chipset(drive, speed); 555} 556 557#ifdef CONFIG_BLK_DEV_IDEDMA 558/* 559 * This allows the configuration of ide_pci chipset registers 560 * for cards that learn about the drive's UDMA, DMA, PIO capabilities 561 * after the drive is reported by the OS. Initally for designed for 562 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc. 563 * 564 * check_in_drive_lists(drive, bad_ata66_4) 565 * check_in_drive_lists(drive, bad_ata66_3) 566 * check_in_drive_lists(drive, bad_ata33) 567 * 568 */ 569static int config_chipset_for_dma (ide_drive_t *drive) 570{ 571 struct hd_driveid *id = drive->id; 572 byte speed = 0x00; 573 byte ultra66 = eighty_ninty_three(drive); 574 int rval; 575 576 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0)) 577 return ((int) ide_dma_off_quietly); 578 579 if ((id->dma_ultra & 0x0020) && 580 (!check_in_drive_lists(drive, bad_ata100_5)) && 581 (HPT370_ALLOW_ATA100_5) && 582 (pci_rev_check_hpt3xx(HWIF(drive)->pci_dev)) && 583 (ultra66)) { 584 speed = XFER_UDMA_5; 585 } else if ((id->dma_ultra & 0x0010) && 586 (!check_in_drive_lists(drive, bad_ata66_4)) && 587 (HPT366_ALLOW_ATA66_4) && 588 (ultra66)) { 589 speed = XFER_UDMA_4; 590 } else if ((id->dma_ultra & 0x0008) && 591 (!check_in_drive_lists(drive, bad_ata66_3)) && 592 (HPT366_ALLOW_ATA66_3) && 593 (ultra66)) { 594 speed = XFER_UDMA_3; 595 } else if (id->dma_ultra && (!check_in_drive_lists(drive, bad_ata33))) { 596 if (id->dma_ultra & 0x0004) { 597 speed = XFER_UDMA_2; 598 } else if (id->dma_ultra & 0x0002) { 599 speed = XFER_UDMA_1; 600 } else if (id->dma_ultra & 0x0001) { 601 speed = XFER_UDMA_0; 602 } 603 } else if (id->dma_mword & 0x0004) { 604 speed = XFER_MW_DMA_2; 605 } else if (id->dma_mword & 0x0002) { 606 speed = XFER_MW_DMA_1; 607 } else if (id->dma_mword & 0x0001) { 608 speed = XFER_MW_DMA_0; 609 } else { 610 return ((int) ide_dma_off_quietly); 611 } 612 613 (void) hpt3xx_tune_chipset(drive, speed); 614 615 rval = (int)( ((id->dma_ultra >> 11) & 7) ? ide_dma_on : 616 ((id->dma_ultra >> 8) & 7) ? ide_dma_on : 617 ((id->dma_mword >> 8) & 7) ? ide_dma_on : 618 ide_dma_off_quietly); 619 return rval; 620} 621 622int hpt3xx_quirkproc (ide_drive_t *drive) 623{ 624 return ((int) check_in_drive_lists(drive, quirk_drives)); 625} 626 627void hpt3xx_intrproc (ide_drive_t *drive) 628{ 629 if (drive->quirk_list) { 630 /* drives in the quirk_list may not like intr setups/cleanups */ 631 } else { 632 OUT_BYTE((drive)->ctl|2, HWIF(drive)->io_ports[IDE_CONTROL_OFFSET]); 633 } 634} 635 636void hpt3xx_maskproc (ide_drive_t *drive, int mask) 637{ 638 if (drive->quirk_list) { 639 if (pci_rev_check_hpt3xx(HWIF(drive)->pci_dev)) { 640 byte reg5a = 0; 641 pci_read_config_byte(HWIF(drive)->pci_dev, 0x5a, ®5a); 642 if (((reg5a & 0x10) >> 4) != mask) 643 pci_write_config_byte(HWIF(drive)->pci_dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10)); 644 } else { 645 if (mask) { 646 disable_irq(HWIF(drive)->irq); 647 } else { 648 enable_irq(HWIF(drive)->irq); 649 } 650 } 651 } else { 652 if (IDE_CONTROL_REG) 653 OUT_BYTE(mask ? (drive->ctl | 2) : (drive->ctl & ~2), IDE_CONTROL_REG); 654 } 655} 656 657static int config_drive_xfer_rate (ide_drive_t *drive) 658{ 659 struct hd_driveid *id = drive->id; 660 ide_dma_action_t dma_func = ide_dma_on; 661 662 if (id && (id->capability & 1) && HWIF(drive)->autodma) { 663 /* Consult the list of known "bad" drives */ 664 if (ide_dmaproc(ide_dma_bad_drive, drive)) { 665 dma_func = ide_dma_off; 666 goto fast_ata_pio; 667 } 668 dma_func = ide_dma_off_quietly; 669 if (id->field_valid & 4) { 670 if (id->dma_ultra & 0x002F) { 671 /* Force if Capable UltraDMA */ 672 dma_func = config_chipset_for_dma(drive); 673 if ((id->field_valid & 2) && 674 (dma_func != ide_dma_on)) 675 goto try_dma_modes; 676 } 677 } else if (id->field_valid & 2) { 678try_dma_modes: 679 if (id->dma_mword & 0x0007) { 680 /* Force if Capable regular DMA modes */ 681 dma_func = config_chipset_for_dma(drive); 682 if (dma_func != ide_dma_on) 683 goto no_dma_set; 684 } 685 } else if (ide_dmaproc(ide_dma_good_drive, drive)) { 686 if (id->eide_dma_time > 150) { 687 goto no_dma_set; 688 } 689 /* Consult the list of known "good" drives */ 690 dma_func = config_chipset_for_dma(drive); 691 if (dma_func != ide_dma_on) 692 goto no_dma_set; 693 } else { 694 goto fast_ata_pio; 695 } 696 } else if ((id->capability & 8) || (id->field_valid & 2)) { 697fast_ata_pio: 698 dma_func = ide_dma_off_quietly; 699no_dma_set: 700 701 config_chipset_for_pio(drive); 702 } 703 return HWIF(drive)->dmaproc(dma_func, drive); 704} 705 706/* 707 * hpt366_dmaproc() initiates/aborts (U)DMA read/write operations on a drive. 708 * 709 * This is specific to the HPT366 UDMA bios chipset 710 * by HighPoint|Triones Technologies, Inc. 711 */ 712int hpt366_dmaproc (ide_dma_action_t func, ide_drive_t *drive) 713{ 714 byte reg50h = 0, reg52h = 0, reg5ah = 0, dma_stat = 0; 715 unsigned long dma_base = HWIF(drive)->dma_base; 716 717 switch (func) { 718 case ide_dma_check: 719 return config_drive_xfer_rate(drive); 720 case ide_dma_test_irq: /* returns 1 if dma irq issued, 0 otherwise */ 721 dma_stat = inb(dma_base+2); 722 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */ 723 case ide_dma_lostirq: 724 pci_read_config_byte(HWIF(drive)->pci_dev, 0x50, ®50h); 725 pci_read_config_byte(HWIF(drive)->pci_dev, 0x52, ®52h); 726 pci_read_config_byte(HWIF(drive)->pci_dev, 0x5a, ®5ah); 727 printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n", 728 drive->name, 729 ide_dmafunc_verbose(func), 730 reg50h, reg52h, reg5ah); 731 if (reg5ah & 0x10) 732 pci_write_config_byte(HWIF(drive)->pci_dev, 0x5a, reg5ah & ~0x10); 733 /* fall through to a reset */ 734 break; 735 case ide_dma_timeout: 736 default: 737 break; 738 } 739 return ide_dmaproc(func, drive); /* use standard DMA stuff */ 740} 741 742int hpt370_dmaproc (ide_dma_action_t func, ide_drive_t *drive) 743{ 744 ide_hwif_t *hwif = HWIF(drive); 745 unsigned long dma_base = hwif->dma_base; 746 byte regstate = hwif->channel ? 0x54 : 0x50; 747 byte reginfo = hwif->channel ? 0x56 : 0x52; 748 byte dma_stat; 749 750 switch (func) { 751 case ide_dma_check: 752 return config_drive_xfer_rate(drive); 753 case ide_dma_test_irq: /* returns 1 if dma irq issued, 0 otherwise */ 754 dma_stat = inb(dma_base+2); 755 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */ 756 757 case ide_dma_end: 758 dma_stat = inb(dma_base + 2); 759 if (dma_stat & 0x01) { 760 udelay(20); /* wait a little */ 761 dma_stat = inb(dma_base + 2); 762 } 763 if ((dma_stat & 0x01) == 0) 764 break; 765 766 func = ide_dma_timeout; 767 /* fallthrough */ 768 769 case ide_dma_timeout: 770 case ide_dma_lostirq: 771 pci_read_config_byte(hwif->pci_dev, reginfo, 772 &dma_stat); 773 printk("%s: %d bytes in FIFO\n", drive->name, 774 dma_stat); 775 pci_write_config_byte(hwif->pci_dev, regstate, 0x37); 776 udelay(10); 777 dma_stat = inb(dma_base); 778 outb(dma_stat & ~0x1, dma_base); /* stop dma */ 779 dma_stat = inb(dma_base + 2); 780 outb(dma_stat | 0x6, dma_base+2); /* clear errors */ 781 /* fallthrough */ 782 783#ifdef HPT_RESET_STATE_ENGINE 784 case ide_dma_begin: 785#endif 786 pci_write_config_byte(hwif->pci_dev, regstate, 0x37); 787 udelay(10); 788 break; 789 790 default: 791 break; 792 } 793 return ide_dmaproc(func, drive); /* use standard DMA stuff */ 794} 795#endif /* CONFIG_BLK_DEV_IDEDMA */ 796 797/* 798 * Since SUN Cobalt is attempting to do this operation, I should disclose 799 * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date 800 * HOTSWAP ATA Infrastructure. 801 */ 802void hpt3xx_reset (ide_drive_t *drive) 803{ 804} 805 806static int hpt3xx_tristate (ide_drive_t * drive, int state) 807{ 808 ide_hwif_t *hwif = HWIF(drive); 809 struct pci_dev *dev = hwif->pci_dev; 810 byte reset = (hwif->channel) ? 0x80 : 0x40; 811 byte state_reg = (hwif->channel) ? 0x57 : 0x53; 812 byte reg59h = 0; 813 byte regXXh = 0; 814 815 if (!hwif) 816 return -EINVAL; 817 818// hwif->bus_state = state; 819 820 pci_read_config_byte(dev, 0x59, ®59h); 821 pci_read_config_byte(dev, state_reg, ®XXh); 822 823 if (state) { 824 (void) ide_do_reset(drive); 825 pci_write_config_byte(dev, state_reg, regXXh|0x80); 826 pci_write_config_byte(dev, 0x59, reg59h|reset); 827 } else { 828 pci_write_config_byte(dev, 0x59, reg59h & ~(reset)); 829 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80)); 830 (void) ide_do_reset(drive); 831 } 832 return 0; 833} 834 835/* 836 * set/get power state for a drive. 837 * turning the power off does the following things: 838 * 1) soft-reset the drive 839 * 2) tri-states the ide bus 840 * 841 * when we turn things back on, we need to re-initialize things. 842 */ 843#define TRISTATE_BIT 0x8000 844static int hpt370_busproc(ide_drive_t * drive, int state) 845{ 846 ide_hwif_t *hwif = HWIF(drive); 847 byte tristate, resetmask, bus_reg; 848 u16 tri_reg; 849 850 if (!hwif) 851 return -EINVAL; 852 853 hwif->bus_state = state; 854 855 if (hwif->channel) { 856 /* secondary channel */ 857 tristate = 0x56; 858 resetmask = 0x80; 859 } else { 860 /* primary channel */ 861 tristate = 0x52; 862 resetmask = 0x40; 863 } 864 865 /* grab status */ 866 pci_read_config_word(hwif->pci_dev, tristate, &tri_reg); 867 pci_read_config_byte(hwif->pci_dev, 0x59, &bus_reg); 868 869 /* set the state. we don't set it if we don't need to do so. 870 * make sure that the drive knows that it has failed if it's off */ 871 switch (state) { 872 case BUSSTATE_ON: 873 hwif->drives[0].failures = 0; 874 hwif->drives[1].failures = 0; 875 if ((bus_reg & resetmask) == 0) 876 return 0; 877 tri_reg &= ~TRISTATE_BIT; 878 bus_reg &= ~resetmask; 879 break; 880 case BUSSTATE_OFF: 881 hwif->drives[0].failures = hwif->drives[0].max_failures + 1; 882 hwif->drives[1].failures = hwif->drives[1].max_failures + 1; 883 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask)) 884 return 0; 885 tri_reg &= ~TRISTATE_BIT; 886 bus_reg |= resetmask; 887 break; 888 case BUSSTATE_TRISTATE: 889 hwif->drives[0].failures = hwif->drives[0].max_failures + 1; 890 hwif->drives[1].failures = hwif->drives[1].max_failures + 1; 891 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask)) 892 return 0; 893 tri_reg |= TRISTATE_BIT; 894 bus_reg |= resetmask; 895 break; 896 } 897 pci_write_config_byte(hwif->pci_dev, 0x59, bus_reg); 898 pci_write_config_word(hwif->pci_dev, tristate, tri_reg); 899 900 return 0; 901} 902 903static void __init init_hpt370(struct pci_dev *dev) 904{ 905 int adjust, i; 906 u16 freq; 907 u32 pll; 908 byte reg5bh; 909 910 /* 911 * default to pci clock. make sure MA15/16 are set to output 912 * to prevent drives having problems with 40-pin cables. 913 */ 914 pci_write_config_byte(dev, 0x5b, 0x23); 915 916 /* 917 * set up the PLL. we need to adjust it so that it's stable. 918 * freq = Tpll * 192 / Tpci 919 */ 920 pci_read_config_word(dev, 0x78, &freq); 921 freq &= 0x1FF; 922 if (freq < 0x9c) { 923 pll = F_LOW_PCI_33; 924 dev->sysdata = (void *) thirty_three_base_hpt370; 925 printk("HPT370: using 33MHz PCI clock\n"); 926 } else if (freq < 0xb0) { 927 pll = F_LOW_PCI_40; 928 } else if (freq < 0xc8) { 929 pll = F_LOW_PCI_50; 930 dev->sysdata = (void *) fifty_base_hpt370; 931 printk("HPT370: using 50MHz PCI clock\n"); 932 } else { 933 pll = F_LOW_PCI_66; 934 dev->sysdata = (void *) sixty_six_base_hpt370; 935 printk("HPT370: using 66MHz PCI clock\n"); 936 } 937 938 /* 939 * only try the pll if we don't have a table for the clock 940 * speed that we're running at. NOTE: the internal PLL will 941 * result in slow reads when using a 33MHz PCI clock. we also 942 * don't like to use the PLL because it will cause glitches 943 * on PRST/SRST when the HPT state engine gets reset. 944 */ 945 if (dev->sysdata) 946 goto init_hpt370_done; 947 948 /* 949 * adjust PLL based upon PCI clock, enable it, and wait for 950 * stabilization. 951 */ 952 adjust = 0; 953 freq = (pll < F_LOW_PCI_50) ? 2 : 4; 954 while (adjust++ < 6) { 955 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 | 956 pll | 0x100); 957 958 /* wait for clock stabilization */ 959 for (i = 0; i < 0x50000; i++) { 960 pci_read_config_byte(dev, 0x5b, ®5bh); 961 if (reg5bh & 0x80) { 962 /* spin looking for the clock to destabilize */ 963 for (i = 0; i < 0x1000; ++i) { 964 pci_read_config_byte(dev, 0x5b, 965 ®5bh); 966 if ((reg5bh & 0x80) == 0) 967 goto pll_recal; 968 } 969 pci_read_config_dword(dev, 0x5c, &pll); 970 pci_write_config_dword(dev, 0x5c, 971 pll & ~0x100); 972 pci_write_config_byte(dev, 0x5b, 0x21); 973 dev->sysdata = (void *) fifty_base_hpt370; 974 printk("HPT370: using 50MHz internal PLL\n"); 975 goto init_hpt370_done; 976 } 977 } 978pll_recal: 979 if (adjust & 1) 980 pll -= (adjust >> 1); 981 else 982 pll += (adjust >> 1); 983 } 984 985init_hpt370_done: 986 /* reset state engine */ 987 pci_write_config_byte(dev, 0x50, 0x37); 988 pci_write_config_byte(dev, 0x54, 0x37); 989 udelay(100); 990} 991 992unsigned int __init pci_init_hpt366 (struct pci_dev *dev, const char *name) 993{ 994 byte test = 0; 995 996 if (dev->resource[PCI_ROM_RESOURCE].start) 997 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); 998 999 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test); 1000 if (test != (L1_CACHE_BYTES / 4)) 1001 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 1002 1003 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test); 1004 if (test != 0x78) 1005 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 1006 1007 pci_read_config_byte(dev, PCI_MIN_GNT, &test); 1008 if (test != 0x08) 1009 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 1010 1011 pci_read_config_byte(dev, PCI_MAX_LAT, &test); 1012 if (test != 0x08) 1013 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 1014 1015 if (pci_rev_check_hpt3xx(dev)) { 1016 init_hpt370(dev); 1017 hpt_devs[n_hpt_devs++] = dev; 1018 } else { 1019 hpt_devs[n_hpt_devs++] = dev; 1020 } 1021 1022#if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) 1023 if (!hpt366_proc) { 1024 hpt366_proc = 1; 1025 hpt366_display_info = &hpt366_get_info; 1026 } 1027#endif /* DISPLAY_HPT366_TIMINGS && CONFIG_PROC_FS */ 1028 1029 return dev->irq; 1030} 1031 1032unsigned int __init ata66_hpt366 (ide_hwif_t *hwif) 1033{ 1034 byte ata66 = 0; 1035 byte regmask = (hwif->channel) ? 0x01 : 0x02; 1036 1037 pci_read_config_byte(hwif->pci_dev, 0x5a, &ata66); 1038#ifdef DEBUG 1039 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n", 1040 ata66, (ata66 & regmask) ? "33" : "66", 1041 PCI_FUNC(hwif->pci_dev->devfn)); 1042#endif /* DEBUG */ 1043 return ((ata66 & regmask) ? 0 : 1); 1044} 1045 1046void __init ide_init_hpt366 (ide_hwif_t *hwif) 1047{ 1048 int hpt_rev; 1049 1050 hwif->tuneproc = &hpt3xx_tune_drive; 1051 hwif->speedproc = &hpt3xx_tune_chipset; 1052 hwif->quirkproc = &hpt3xx_quirkproc; 1053 hwif->intrproc = &hpt3xx_intrproc; 1054 hwif->maskproc = &hpt3xx_maskproc; 1055 1056#ifdef HPT_SERIALIZE_IO 1057 /* serialize access to this device */ 1058 if (hwif->mate) 1059 hwif->serialized = hwif->mate->serialized = 1; 1060#endif 1061 1062 hpt_rev = pci_rev_check_hpt3xx(hwif->pci_dev); 1063 if (hpt_rev) { 1064 /* set up ioctl for power status. note: power affects both 1065 * drives on each channel */ 1066 hwif->busproc = &hpt370_busproc; 1067 } 1068 1069 if (pci_rev2_check_hpt3xx(hwif->pci_dev)) { 1070 /* do nothing now but will split device types */ 1071 hwif->resetproc = &hpt3xx_reset; 1072/* 1073 * don't do until we can parse out the cobalt box argh ... 1074 * hwif->busproc = &hpt3xx_tristate; 1075 */ 1076 } 1077 1078#ifdef CONFIG_BLK_DEV_IDEDMA 1079 if (hwif->dma_base) { 1080 if (hpt_rev) { 1081 byte reg5ah = 0; 1082 pci_read_config_byte(hwif->pci_dev, 0x5a, ®5ah); 1083 if (reg5ah & 0x10) /* interrupt force enable */ 1084 pci_write_config_byte(hwif->pci_dev, 0x5a, reg5ah & ~0x10); 1085 hwif->dmaproc = &hpt370_dmaproc; 1086 } else { 1087 hwif->dmaproc = &hpt366_dmaproc; 1088 } 1089 if (!noautodma) 1090 hwif->autodma = 1; 1091 else 1092 hwif->autodma = 0; 1093 } else { 1094 hwif->autodma = 0; 1095 hwif->drives[0].autotune = 1; 1096 hwif->drives[1].autotune = 1; 1097 } 1098#else /* !CONFIG_BLK_DEV_IDEDMA */ 1099 hwif->drives[0].autotune = 1; 1100 hwif->drives[1].autotune = 1; 1101 hwif->autodma = 0; 1102#endif /* CONFIG_BLK_DEV_IDEDMA */ 1103} 1104 1105void __init ide_dmacapable_hpt366 (ide_hwif_t *hwif, unsigned long dmabase) 1106{ 1107 byte masterdma = 0, slavedma = 0; 1108 byte dma_new = 0, dma_old = inb(dmabase+2); 1109 byte primary = hwif->channel ? 0x4b : 0x43; 1110 byte secondary = hwif->channel ? 0x4f : 0x47; 1111 unsigned long flags; 1112 1113 __save_flags(flags); /* local CPU only */ 1114 __cli(); /* local CPU only */ 1115 1116 dma_new = dma_old; 1117 pci_read_config_byte(hwif->pci_dev, primary, &masterdma); 1118 pci_read_config_byte(hwif->pci_dev, secondary, &slavedma); 1119 1120 if (masterdma & 0x30) dma_new |= 0x20; 1121 if (slavedma & 0x30) dma_new |= 0x40; 1122 if (dma_new != dma_old) outb(dma_new, dmabase+2); 1123 1124 __restore_flags(flags); /* local CPU only */ 1125 1126 ide_setup_dma(hwif, dmabase, 8); 1127} 1128