1/*
2 * linux/drivers/ide/amd74xx.c		Version 0.05	June 9, 2000
3 *
4 * Copyright (C) 1999-2000		Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 */
8
9#include <linux/config.h>
10#include <linux/types.h>
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/timer.h>
14#include <linux/mm.h>
15#include <linux/ioport.h>
16#include <linux/blkdev.h>
17#include <linux/hdreg.h>
18
19#include <linux/interrupt.h>
20#include <linux/init.h>
21#include <linux/pci.h>
22#include <linux/ide.h>
23
24#include <asm/io.h>
25#include <asm/irq.h>
26
27#include "ide_modes.h"
28
29#define DISPLAY_VIPER_TIMINGS
30
31#if defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS)
32#include <linux/stat.h>
33#include <linux/proc_fs.h>
34
35static int amd74xx_get_info(char *, char **, off_t, int);
36extern int (*amd74xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
37extern char *ide_media_verbose(ide_drive_t *);
38static struct pci_dev *bmide_dev;
39
40static int amd74xx_get_info (char *buffer, char **addr, off_t offset, int count)
41{
42	char *p = buffer;
43	u32 bibma = pci_resource_start(bmide_dev, 4);
44	u8 c0 = 0, c1 = 0;
45
46	/*
47	 * at that point bibma+0x2 et bibma+0xa are byte registers
48	 * to investigate:
49	 */
50	c0 = inb_p((unsigned short)bibma + 0x02);
51	c1 = inb_p((unsigned short)bibma + 0x0a);
52
53	p += sprintf(p, "\n                                AMD %04X VIPER Chipset.\n", bmide_dev->device);
54	p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
55	p += sprintf(p, "                %sabled                         %sabled\n",
56			(c0&0x80) ? "dis" : " en",
57			(c1&0x80) ? "dis" : " en");
58	p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
59	p += sprintf(p, "DMA enabled:    %s              %s             %s               %s\n",
60			(c0&0x20) ? "yes" : "no ", (c0&0x40) ? "yes" : "no ",
61			(c1&0x20) ? "yes" : "no ", (c1&0x40) ? "yes" : "no " );
62	p += sprintf(p, "UDMA\n");
63	p += sprintf(p, "DMA\n");
64	p += sprintf(p, "PIO\n");
65
66	return p-buffer;	/* => must be less than 4k! */
67}
68#endif  /* defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS) */
69
70byte amd74xx_proc = 0;
71
72extern char *ide_xfer_verbose (byte xfer_rate);
73
74static unsigned int amd74xx_swdma_check (struct pci_dev *dev)
75{
76	unsigned int class_rev;
77
78	if ((dev->device == PCI_DEVICE_ID_AMD_VIPER_7411) ||
79	    (dev->device == PCI_DEVICE_ID_AMD_VIPER_7441))
80		return 0;
81
82	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
83	class_rev &= 0xff;
84	return ((int) (class_rev >= 7) ? 1 : 0);
85}
86
87static int amd74xx_swdma_error(ide_drive_t *drive)
88{
89	printk("%s: single-word DMA not support (revision < C4)\n", drive->name);
90	return 0;
91}
92
93/*
94 * Here is where all the hard work goes to program the chipset.
95 *
96 */
97static int amd74xx_tune_chipset (ide_drive_t *drive, byte speed)
98{
99	ide_hwif_t *hwif	= HWIF(drive);
100	struct pci_dev *dev	= hwif->pci_dev;
101	int err			= 0;
102	byte unit		= (drive->select.b.unit & 0x01);
103#ifdef CONFIG_BLK_DEV_IDEDMA
104	unsigned long dma_base	= hwif->dma_base;
105#endif /* CONFIG_BLK_DEV_IDEDMA */
106	byte drive_pci		= 0x00;
107	byte drive_pci2		= 0x00;
108	byte ultra_timing	= 0x00;
109	byte dma_pio_timing	= 0x00;
110	byte pio_timing		= 0x00;
111
112        switch (drive->dn) {
113		case 0: drive_pci = 0x53; drive_pci2 = 0x4b; break;
114		case 1: drive_pci = 0x52; drive_pci2 = 0x4a; break;
115		case 2: drive_pci = 0x51; drive_pci2 = 0x49; break;
116		case 3: drive_pci = 0x50; drive_pci2 = 0x48; break;
117		default:
118                        return -1;
119        }
120
121	pci_read_config_byte(dev, drive_pci, &ultra_timing);
122	pci_read_config_byte(dev, drive_pci2, &dma_pio_timing);
123	pci_read_config_byte(dev, 0x4c, &pio_timing);
124
125#ifdef DEBUG
126	printk("%s:%d: Speed 0x%02x UDMA 0x%02x DMAPIO 0x%02x PIO 0x%02x\n",
127		drive->name, drive->dn, speed, ultra_timing, dma_pio_timing, pio_timing);
128#endif
129
130	ultra_timing	&= ~0xC7;
131	dma_pio_timing	&= ~0xFF;
132	pio_timing	&= ~(0x03 << drive->dn);
133
134#ifdef DEBUG
135	printk("%s: UDMA 0x%02x DMAPIO 0x%02x PIO 0x%02x\n",
136		drive->name, ultra_timing, dma_pio_timing, pio_timing);
137#endif
138
139	switch(speed) {
140#ifdef CONFIG_BLK_DEV_IDEDMA
141		case XFER_UDMA_7:
142		case XFER_UDMA_6:
143			speed = XFER_UDMA_5;
144		case XFER_UDMA_5:
145			ultra_timing |= 0x46;
146			dma_pio_timing |= 0x20;
147			break;
148		case XFER_UDMA_4:
149			ultra_timing |= 0x45;
150			dma_pio_timing |= 0x20;
151			break;
152		case XFER_UDMA_3:
153			ultra_timing |= 0x44;
154			dma_pio_timing |= 0x20;
155			break;
156		case XFER_UDMA_2:
157			ultra_timing |= 0x40;
158			dma_pio_timing |= 0x20;
159			break;
160		case XFER_UDMA_1:
161			ultra_timing |= 0x41;
162			dma_pio_timing |= 0x20;
163			break;
164		case XFER_UDMA_0:
165		ultra_timing |= 0x42;
166			dma_pio_timing |= 0x20;
167			break;
168		case XFER_MW_DMA_2:
169			dma_pio_timing |= 0x20;
170			break;
171		case XFER_MW_DMA_1:
172			dma_pio_timing |= 0x21;
173			break;
174		case XFER_MW_DMA_0:
175			dma_pio_timing |= 0x77;
176			break;
177		case XFER_SW_DMA_2:
178			if (!amd74xx_swdma_check(dev))
179				return amd74xx_swdma_error(drive);
180			dma_pio_timing |= 0x42;
181			break;
182		case XFER_SW_DMA_1:
183			if (!amd74xx_swdma_check(dev))
184				return amd74xx_swdma_error(drive);
185			dma_pio_timing |= 0x65;
186			break;
187		case XFER_SW_DMA_0:
188			if (!amd74xx_swdma_check(dev))
189				return amd74xx_swdma_error(drive);
190			dma_pio_timing |= 0xA8;
191			break;
192#endif /* CONFIG_BLK_DEV_IDEDMA */
193		case XFER_PIO_4:
194			dma_pio_timing |= 0x20;
195			break;
196		case XFER_PIO_3:
197			dma_pio_timing |= 0x22;
198			break;
199		case XFER_PIO_2:
200			dma_pio_timing |= 0x42;
201			break;
202		case XFER_PIO_1:
203			dma_pio_timing |= 0x65;
204			break;
205		case XFER_PIO_0:
206		default:
207			dma_pio_timing |= 0xA8;
208			break;
209        }
210
211	pio_timing |= (0x03 << drive->dn);
212
213	if (!drive->init_speed)
214		drive->init_speed = speed;
215
216#ifdef CONFIG_BLK_DEV_IDEDMA
217	pci_write_config_byte(dev, drive_pci, ultra_timing);
218#endif /* CONFIG_BLK_DEV_IDEDMA */
219	pci_write_config_byte(dev, drive_pci2, dma_pio_timing);
220	pci_write_config_byte(dev, 0x4c, pio_timing);
221
222#ifdef DEBUG
223	printk("%s: UDMA 0x%02x DMAPIO 0x%02x PIO 0x%02x\n",
224		drive->name, ultra_timing, dma_pio_timing, pio_timing);
225#endif
226
227#ifdef CONFIG_BLK_DEV_IDEDMA
228	if (speed > XFER_PIO_4) {
229		outb(inb(dma_base+2)|(1<<(5+unit)), dma_base+2);
230	} else {
231		outb(inb(dma_base+2) & ~(1<<(5+unit)), dma_base+2);
232	}
233#endif /* CONFIG_BLK_DEV_IDEDMA */
234
235	err = ide_config_drive_speed(drive, speed);
236	drive->current_speed = speed;
237	return (err);
238}
239
240static void config_chipset_for_pio (ide_drive_t *drive)
241{
242	unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
243	unsigned short xfer_pio	= drive->id->eide_pio_modes;
244	byte			timing, speed, pio;
245
246	pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
247
248	if (xfer_pio> 4)
249		xfer_pio = 0;
250
251	if (drive->id->eide_pio_iordy > 0) {
252		for (xfer_pio = 5;
253			xfer_pio>0 &&
254			drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
255			xfer_pio--);
256	} else {
257		xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
258			   (drive->id->eide_pio_modes & 2) ? 0x04 :
259			   (drive->id->eide_pio_modes & 1) ? 0x03 :
260			   (drive->id->tPIO & 2) ? 0x02 :
261			   (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
262	}
263
264	timing = (xfer_pio >= pio) ? xfer_pio : pio;
265
266	switch(timing) {
267		case 4: speed = XFER_PIO_4;break;
268		case 3: speed = XFER_PIO_3;break;
269		case 2: speed = XFER_PIO_2;break;
270		case 1: speed = XFER_PIO_1;break;
271		default:
272			speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
273			break;
274	}
275	(void) amd74xx_tune_chipset(drive, speed);
276	drive->current_speed = speed;
277}
278
279static void amd74xx_tune_drive (ide_drive_t *drive, byte pio)
280{
281	byte speed;
282	switch(pio) {
283		case 4:		speed = XFER_PIO_4;break;
284		case 3:		speed = XFER_PIO_3;break;
285		case 2:		speed = XFER_PIO_2;break;
286		case 1:		speed = XFER_PIO_1;break;
287		default:	speed = XFER_PIO_0;break;
288	}
289	(void) amd74xx_tune_chipset(drive, speed);
290}
291
292#ifdef CONFIG_BLK_DEV_IDEDMA
293/*
294 * This allows the configuration of ide_pci chipset registers
295 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
296 * after the drive is reported by the OS.
297 */
298static int config_chipset_for_dma (ide_drive_t *drive)
299{
300	ide_hwif_t *hwif	= HWIF(drive);
301	struct pci_dev *dev	= hwif->pci_dev;
302	struct hd_driveid *id	= drive->id;
303	byte udma_66		= eighty_ninty_three(drive);
304	byte udma_100		= ((dev->device==PCI_DEVICE_ID_AMD_VIPER_7411)||
305				   (dev->device==PCI_DEVICE_ID_AMD_VIPER_7441)) ? 1 : 0;
306	byte speed		= 0x00;
307	int  rval;
308
309	if (udma_100)
310		udma_66 = eighty_ninty_three(drive);
311
312	if ((id->dma_ultra & 0x0020) && (udma_66) && (udma_100)) {
313		speed = XFER_UDMA_5;
314	} else if ((id->dma_ultra & 0x0010) && (udma_66)) {
315		speed = XFER_UDMA_4;
316	} else if ((id->dma_ultra & 0x0008) && (udma_66)) {
317		speed = XFER_UDMA_3;
318	} else if (id->dma_ultra & 0x0004) {
319		speed = XFER_UDMA_2;
320	} else if (id->dma_ultra & 0x0002) {
321		speed = XFER_UDMA_1;
322	} else if (id->dma_ultra & 0x0001) {
323		speed = XFER_UDMA_0;
324	} else if (id->dma_mword & 0x0004) {
325		speed = XFER_MW_DMA_2;
326	} else if (id->dma_mword & 0x0002) {
327		speed = XFER_MW_DMA_1;
328	} else if (id->dma_mword & 0x0001) {
329		speed = XFER_MW_DMA_0;
330	} else {
331		return ((int) ide_dma_off_quietly);
332	}
333
334	(void) amd74xx_tune_chipset(drive, speed);
335
336	rval = (int)(	((id->dma_ultra >> 11) & 7) ? ide_dma_on :
337			((id->dma_ultra >> 8) & 7) ? ide_dma_on :
338			((id->dma_mword >> 8) & 7) ? ide_dma_on :
339						     ide_dma_off_quietly);
340
341	return rval;
342}
343
344static int config_drive_xfer_rate (ide_drive_t *drive)
345{
346	struct hd_driveid *id = drive->id;
347	ide_dma_action_t dma_func = ide_dma_on;
348
349	if (id && (id->capability & 1) && HWIF(drive)->autodma) {
350		/* Consult the list of known "bad" drives */
351		if (ide_dmaproc(ide_dma_bad_drive, drive)) {
352			dma_func = ide_dma_off;
353			goto fast_ata_pio;
354		}
355		dma_func = ide_dma_off_quietly;
356		if (id->field_valid & 4) {
357			if (id->dma_ultra & 0x003F) {
358				/* Force if Capable UltraDMA */
359				dma_func = config_chipset_for_dma(drive);
360				if ((id->field_valid & 2) &&
361				    (dma_func != ide_dma_on))
362					goto try_dma_modes;
363			}
364		} else if (id->field_valid & 2) {
365try_dma_modes:
366			if ((id->dma_mword & 0x0007) ||
367			    ((id->dma_1word & 0x007) &&
368			     (amd74xx_swdma_check(HWIF(drive)->pci_dev)))) {
369				/* Force if Capable regular DMA modes */
370				dma_func = config_chipset_for_dma(drive);
371				if (dma_func != ide_dma_on)
372					goto no_dma_set;
373			}
374
375		} else if (ide_dmaproc(ide_dma_good_drive, drive)) {
376			if (id->eide_dma_time > 150) {
377				goto no_dma_set;
378			}
379			/* Consult the list of known "good" drives */
380			dma_func = config_chipset_for_dma(drive);
381			if (dma_func != ide_dma_on)
382				goto no_dma_set;
383		} else {
384			goto fast_ata_pio;
385		}
386	} else if ((id->capability & 8) || (id->field_valid & 2)) {
387fast_ata_pio:
388		dma_func = ide_dma_off_quietly;
389no_dma_set:
390
391		config_chipset_for_pio(drive);
392	}
393	return HWIF(drive)->dmaproc(dma_func, drive);
394}
395
396/*
397 * amd74xx_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
398 */
399
400int amd74xx_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
401{
402	switch (func) {
403		case ide_dma_check:
404			return config_drive_xfer_rate(drive);
405		default:
406			break;
407	}
408	return ide_dmaproc(func, drive);	/* use standard DMA stuff */
409}
410#endif /* CONFIG_BLK_DEV_IDEDMA */
411
412unsigned int __init pci_init_amd74xx (struct pci_dev *dev, const char *name)
413{
414	unsigned long fixdma_base = pci_resource_start(dev, 4);
415
416#ifdef CONFIG_BLK_DEV_IDEDMA
417	if (!amd74xx_swdma_check(dev))
418		printk("%s: disabling single-word DMA support (revision < C4)\n", name);
419#endif /* CONFIG_BLK_DEV_IDEDMA */
420
421	if (!fixdma_base) {
422		/*
423		 *
424		 */
425	} else {
426		/*
427		 * enable DMA capable bit, and "not" simplex only
428		 */
429		outb(inb(fixdma_base+2) & 0x60, fixdma_base+2);
430
431		if (inb(fixdma_base+2) & 0x80)
432			printk("%s: simplex device: DMA will fail!!\n", name);
433	}
434#if defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS)
435	if (!amd74xx_proc) {
436		amd74xx_proc = 1;
437		bmide_dev = dev;
438		amd74xx_display_info = &amd74xx_get_info;
439	}
440#endif /* DISPLAY_VIPER_TIMINGS && CONFIG_PROC_FS */
441
442	return 0;
443}
444
445unsigned int __init ata66_amd74xx (ide_hwif_t *hwif)
446{
447	struct pci_dev *dev	= hwif->pci_dev;
448	byte cable_80_pin[2]	= { 0, 0 };
449	byte ata66		= 0;
450	byte tmpbyte;
451
452	/*
453	 * Ultra66 cable detection (from Host View)
454	 * 7411, 7441, 0x42, bit0: primary, bit2: secondary 80 pin
455	 */
456	pci_read_config_byte(dev, 0x42, &tmpbyte);
457
458	/*
459	 * 0x42, bit0 is 1 => primary channel
460	 * has 80-pin (from host view)
461	 */
462	if (tmpbyte & 0x01) cable_80_pin[0] = 1;
463
464	/*
465	 * 0x42, bit2 is 1 => secondary channel
466	 * has 80-pin (from host view)
467	 */
468	if (tmpbyte & 0x04) cable_80_pin[1] = 1;
469
470	switch(dev->device) {
471		case PCI_DEVICE_ID_AMD_VIPER_7441:
472		case PCI_DEVICE_ID_AMD_VIPER_7411:
473			ata66 = (hwif->channel) ?
474				cable_80_pin[1] :
475				cable_80_pin[0];
476		default:
477			break;
478	}
479#ifdef CONFIG_AMD74XX_OVERRIDE
480	return(1);
481#else
482	return (unsigned int) ata66;
483#endif /* CONFIG_AMD74XX_OVERRIDE */
484}
485
486void __init ide_init_amd74xx (ide_hwif_t *hwif)
487{
488	hwif->tuneproc = &amd74xx_tune_drive;
489	hwif->speedproc = &amd74xx_tune_chipset;
490
491#ifndef CONFIG_BLK_DEV_IDEDMA
492	hwif->drives[0].autotune = 1;
493	hwif->drives[1].autotune = 1;
494	hwif->autodma = 0;
495	return;
496#else
497
498	if (hwif->dma_base) {
499		hwif->dmaproc = &amd74xx_dmaproc;
500		if (!noautodma)
501			hwif->autodma = 1;
502	} else {
503		hwif->autodma = 0;
504		hwif->drives[0].autotune = 1;
505		hwif->drives[1].autotune = 1;
506	}
507#endif /* CONFIG_BLK_DEV_IDEDMA */
508}
509
510void __init ide_dmacapable_amd74xx (ide_hwif_t *hwif, unsigned long dmabase)
511{
512	ide_setup_dma(hwif, dmabase, 8);
513}
514