1/*******************************************************************************
2*
3*   (c) 1999 by Computone Corporation
4*
5********************************************************************************
6*
7*
8*   PACKAGE:     Linux tty Device Driver for IntelliPort II family of multiport
9*                serial I/O controllers.
10*
11*   DESCRIPTION: Defines, definitions and includes which are heavily dependant
12*                on O/S, host, compiler, etc. This file is tailored for:
13*                 Linux v2.0.0 and later
14*                 Gnu gcc c2.7.2
15*                 80x86 architecture
16*
17*******************************************************************************/
18
19#ifndef I2OS_H        /* To prevent multiple includes */
20#define I2OS_H 1
21
22#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
23
24//-------------------------------------------------
25// Required Includes
26//-------------------------------------------------
27
28#include "ip2types.h"
29#include <asm/io.h>  /* For inb, etc */
30#include <linux/version.h>
31
32//------------------------------------
33// Defines for I/O instructions:
34//------------------------------------
35
36#define INB(port)                inb(port)
37#define OUTB(port,value)         outb((value),(port))
38#define INW(port)                inw(port)
39#define OUTW(port,value)         outw((value),(port))
40#define OUTSW(port,addr,count)   outsw((port),(addr),(((count)+1)/2))
41#define OUTSB(port,addr,count)   outsb((port),(addr),(((count)+1))&-2)
42#define INSW(port,addr,count)    insw((port),(addr),(((count)+1)/2))
43#define INSB(port,addr,count)    insb((port),(addr),(((count)+1))&-2)
44
45//--------------------------------------------
46// Interrupt control
47//--------------------------------------------
48
49#if LINUX_VERSION_CODE < 0x00020100
50typedef int spinlock_t;
51#define spin_lock_init()
52#define spin_lock(a)
53#define spin_unlock(a)
54#define spin_lock_irqsave(a,b)			{save_flags((b));cli();}
55#define spin_unlock_irqrestore(a,b)		{restore_flags((b));}
56#define write_lock_irqsave(a,b)			spin_lock_irqsave(a,b)
57#define write_unlock_irqrestore(a,b)	spin_unlock_irqrestore(a,b)
58#define read_lock_irqsave(a,b)			spin_lock_irqsave(a,b)
59#define read_unlock_irqrestore(a,b)		spin_unlock_irqrestore(a,b)
60#endif
61
62//#define SAVE_AND_DISABLE_INTS(a,b)	spin_lock_irqsave(a,b)
63//#define RESTORE_INTS(a,b)         	spin_unlock_irqrestore(a,b)
64
65#define LOCK_INIT(a)	rwlock_init(a)
66
67#define SAVE_AND_DISABLE_INTS(a,b) { \
68	/* printk("get_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
69	spin_lock_irqsave(a,b); \
70}
71
72#define RESTORE_INTS(a,b) { \
73	/* printk("rel_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
74	spin_unlock_irqrestore(a,b); \
75}
76
77#define READ_LOCK_IRQSAVE(a,b) { \
78	/* printk("get_read_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
79	read_lock_irqsave(a,b); \
80}
81
82#define READ_UNLOCK_IRQRESTORE(a,b) { \
83	/* printk("rel_read_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
84	read_unlock_irqrestore(a,b); \
85}
86
87#define WRITE_LOCK_IRQSAVE(a,b) { \
88	/* printk("get_write_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
89	write_lock_irqsave(a,b); \
90}
91
92#define WRITE_UNLOCK_IRQRESTORE(a,b) { \
93	/* printk("rel_write_lock: 0x%x,%4d,%s\n",(int)a,__LINE__,__FILE__);*/ \
94	write_unlock_irqrestore(a,b); \
95}
96
97
98//------------------------------------------------------------------------------
99// Hardware-delay loop
100//
101// Probably used in only one place (see i2ellis.c) but this helps keep things
102// together. Note we have unwound the IN instructions. On machines with a
103// reasonable cache, the eight instructions (1 byte each) should fit in cache
104// nicely, and on un-cached machines, the code-fetch would tend not to dominate.
105// Note that cx is shifted so that "count" still reflects the total number of
106// iterations assuming no unwinding.
107//------------------------------------------------------------------------------
108
109//#define  DELAY1MS(port,count,label)
110
111//------------------------------------------------------------------------------
112// Macros to switch to a new stack, saving stack pointers, and to restore the
113// old stack (Used, for example, in i2lib.c) "heap" is the address of some
114// buffer which will become the new stack (working down from highest address).
115// The two words at the two lowest addresses in this stack are for storing the
116// SS and SP.
117//------------------------------------------------------------------------------
118
119//#define  TO_NEW_STACK(heap,size)
120//#define  TO_OLD_STACK(heap)
121
122//------------------------------------------------------------------------------
123// Macros to save the original IRQ vectors and masks, and to patch in new ones.
124//------------------------------------------------------------------------------
125
126//#define  SAVE_IRQ_MASKS(dest)
127//#define  WRITE_IRQ_MASKS(src)
128//#define  SAVE_IRQ_VECTOR(value,dest)
129//#define  WRITE_IRQ_VECTOR(value,src)
130
131//------------------------------------------------------------------------------
132// Macro to copy data from one far pointer to another.
133//------------------------------------------------------------------------------
134
135#define  I2_MOVE_DATA(fpSource,fpDest,count) memmove(fpDest,fpSource,count);
136
137//------------------------------------------------------------------------------
138// Macros to issue eoi's to host interrupt control (IBM AT 8259-style).
139//------------------------------------------------------------------------------
140
141//#define MASTER_EOI
142//#define SLAVE_EOI
143
144#endif   /* I2OS_H */
145
146
147