1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#ifndef __RADEON_DRM_H__ 32#define __RADEON_DRM_H__ 33 34/* WARNING: If you change any of these defines, make sure to change the 35 * defines in the X server file (radeon_sarea.h) 36 */ 37#ifndef __RADEON_SAREA_DEFINES__ 38#define __RADEON_SAREA_DEFINES__ 39 40/* What needs to be changed for the current vertex buffer? 41 */ 42#define RADEON_UPLOAD_CONTEXT 0x00000001 43#define RADEON_UPLOAD_VERTFMT 0x00000002 44#define RADEON_UPLOAD_LINE 0x00000004 45#define RADEON_UPLOAD_BUMPMAP 0x00000008 46#define RADEON_UPLOAD_MASKS 0x00000010 47#define RADEON_UPLOAD_VIEWPORT 0x00000020 48#define RADEON_UPLOAD_SETUP 0x00000040 49#define RADEON_UPLOAD_TCL 0x00000080 50#define RADEON_UPLOAD_MISC 0x00000100 51#define RADEON_UPLOAD_TEX0 0x00000200 52#define RADEON_UPLOAD_TEX1 0x00000400 53#define RADEON_UPLOAD_TEX2 0x00000800 54#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 55#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 56#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 57#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ 58#define RADEON_REQUIRE_QUIESCENCE 0x00010000 59#define RADEON_UPLOAD_ALL 0x0001ffff 60 61#define RADEON_FRONT 0x1 62#define RADEON_BACK 0x2 63#define RADEON_DEPTH 0x4 64 65/* Primitive types 66 */ 67#define RADEON_POINTS 0x1 68#define RADEON_LINES 0x2 69#define RADEON_LINE_STRIP 0x3 70#define RADEON_TRIANGLES 0x4 71#define RADEON_TRIANGLE_FAN 0x5 72#define RADEON_TRIANGLE_STRIP 0x6 73 74/* Vertex/indirect buffer size 75 */ 76#define RADEON_BUFFER_SIZE 65536 77 78/* Byte offsets for indirect buffer data 79 */ 80#define RADEON_INDEX_PRIM_OFFSET 20 81#define RADEON_HOSTDATA_BLIT_OFFSET 32 82 83#define RADEON_SCRATCH_REG_OFFSET 32 84 85/* Keep these small for testing 86 */ 87#define RADEON_NR_SAREA_CLIPRECTS 12 88 89/* There are 2 heaps (local/AGP). Each region within a heap is a 90 * minimum of 64k, and there are at most 64 of them per heap. 91 */ 92#define RADEON_LOCAL_TEX_HEAP 0 93#define RADEON_AGP_TEX_HEAP 1 94#define RADEON_NR_TEX_HEAPS 2 95#define RADEON_NR_TEX_REGIONS 64 96#define RADEON_LOG_TEX_GRANULARITY 16 97 98#define RADEON_MAX_TEXTURE_LEVELS 11 99#define RADEON_MAX_TEXTURE_UNITS 3 100 101#endif /* __RADEON_SAREA_DEFINES__ */ 102 103typedef struct { 104 unsigned int red; 105 unsigned int green; 106 unsigned int blue; 107 unsigned int alpha; 108} radeon_color_regs_t; 109 110typedef struct { 111 /* Context state */ 112 unsigned int pp_misc; /* 0x1c14 */ 113 unsigned int pp_fog_color; 114 unsigned int re_solid_color; 115 unsigned int rb3d_blendcntl; 116 unsigned int rb3d_depthoffset; 117 unsigned int rb3d_depthpitch; 118 unsigned int rb3d_zstencilcntl; 119 120 unsigned int pp_cntl; /* 0x1c38 */ 121 unsigned int rb3d_cntl; 122 unsigned int rb3d_coloroffset; 123 unsigned int re_width_height; 124 unsigned int rb3d_colorpitch; 125 unsigned int se_cntl; 126 127 /* Vertex format state */ 128 unsigned int se_coord_fmt; /* 0x1c50 */ 129 130 /* Line state */ 131 unsigned int re_line_pattern; /* 0x1cd0 */ 132 unsigned int re_line_state; 133 134 unsigned int se_line_width; /* 0x1db8 */ 135 136 /* Bumpmap state */ 137 unsigned int pp_lum_matrix; /* 0x1d00 */ 138 139 unsigned int pp_rot_matrix_0; /* 0x1d58 */ 140 unsigned int pp_rot_matrix_1; 141 142 /* Mask state */ 143 unsigned int rb3d_stencilrefmask; /* 0x1d7c */ 144 unsigned int rb3d_ropcntl; 145 unsigned int rb3d_planemask; 146 147 /* Viewport state */ 148 unsigned int se_vport_xscale; /* 0x1d98 */ 149 unsigned int se_vport_xoffset; 150 unsigned int se_vport_yscale; 151 unsigned int se_vport_yoffset; 152 unsigned int se_vport_zscale; 153 unsigned int se_vport_zoffset; 154 155 /* Setup state */ 156 unsigned int se_cntl_status; /* 0x2140 */ 157 158#ifdef TCL_ENABLE 159 /* TCL state */ 160 radeon_color_regs_t se_tcl_material_emmissive; /* 0x2210 */ 161 radeon_color_regs_t se_tcl_material_ambient; 162 radeon_color_regs_t se_tcl_material_diffuse; 163 radeon_color_regs_t se_tcl_material_specular; 164 unsigned int se_tcl_shininess; 165 unsigned int se_tcl_output_vtx_fmt; 166 unsigned int se_tcl_output_vtx_sel; 167 unsigned int se_tcl_matrix_select_0; 168 unsigned int se_tcl_matrix_select_1; 169 unsigned int se_tcl_ucp_vert_blend_ctl; 170 unsigned int se_tcl_texture_proc_ctl; 171 unsigned int se_tcl_light_model_ctl; 172 unsigned int se_tcl_per_light_ctl[4]; 173#endif 174 175 /* Misc state */ 176 unsigned int re_top_left; /* 0x26c0 */ 177 unsigned int re_misc; 178} drm_radeon_context_regs_t; 179 180/* Setup registers for each texture unit 181 */ 182typedef struct { 183 unsigned int pp_txfilter; 184 unsigned int pp_txformat; 185 unsigned int pp_txoffset; 186 unsigned int pp_txcblend; 187 unsigned int pp_txablend; 188 unsigned int pp_tfactor; 189 190 unsigned int pp_border_color; 191 192#ifdef CUBIC_ENABLE 193 unsigned int pp_cubic_faces; 194 unsigned int pp_cubic_offset[5]; 195#endif 196} drm_radeon_texture_regs_t; 197 198typedef struct { 199 unsigned char next, prev; 200 unsigned char in_use; 201 int age; 202} drm_radeon_tex_region_t; 203 204typedef struct { 205 /* The channel for communication of state information to the kernel 206 * on firing a vertex buffer. 207 */ 208 drm_radeon_context_regs_t context_state; 209 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 210 unsigned int dirty; 211 unsigned int vertsize; 212 unsigned int vc_format; 213 214 /* The current cliprects, or a subset thereof. 215 */ 216 drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS]; 217 unsigned int nbox; 218 219 /* Counters for client-side throttling of rendering clients. 220 */ 221 unsigned int last_frame; 222 unsigned int last_dispatch; 223 unsigned int last_clear; 224 225 drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1]; 226 int tex_age[RADEON_NR_TEX_HEAPS]; 227 int ctx_owner; 228} drm_radeon_sarea_t; 229 230 231/* WARNING: If you change any of these defines, make sure to change the 232 * defines in the Xserver file (xf86drmRadeon.h) 233 */ 234typedef struct drm_radeon_init { 235 enum { 236 RADEON_INIT_CP = 0x01, 237 RADEON_CLEANUP_CP = 0x02 238 } func; 239 unsigned long sarea_priv_offset; 240 int is_pci; 241 int cp_mode; 242 int agp_size; 243 int ring_size; 244 int usec_timeout; 245 246 unsigned int fb_bpp; 247 unsigned int front_offset, front_pitch; 248 unsigned int back_offset, back_pitch; 249 unsigned int depth_bpp; 250 unsigned int depth_offset, depth_pitch; 251 252 unsigned long fb_offset; 253 unsigned long mmio_offset; 254 unsigned long ring_offset; 255 unsigned long ring_rptr_offset; 256 unsigned long buffers_offset; 257 unsigned long agp_textures_offset; 258} drm_radeon_init_t; 259 260typedef struct drm_radeon_cp_stop { 261 int flush; 262 int idle; 263} drm_radeon_cp_stop_t; 264 265typedef struct drm_radeon_fullscreen { 266 enum { 267 RADEON_INIT_FULLSCREEN = 0x01, 268 RADEON_CLEANUP_FULLSCREEN = 0x02 269 } func; 270} drm_radeon_fullscreen_t; 271 272#define CLEAR_X1 0 273#define CLEAR_Y1 1 274#define CLEAR_X2 2 275#define CLEAR_Y2 3 276#define CLEAR_DEPTH 4 277 278typedef union drm_radeon_clear_rect { 279 float f[5]; 280 unsigned int ui[5]; 281} drm_radeon_clear_rect_t; 282 283typedef struct drm_radeon_clear { 284 unsigned int flags; 285 unsigned int clear_color; 286 unsigned int clear_depth; 287 unsigned int color_mask; 288 unsigned int depth_mask; 289 drm_radeon_clear_rect_t *depth_boxes; 290} drm_radeon_clear_t; 291 292typedef struct drm_radeon_vertex { 293 int prim; 294 int idx; /* Index of vertex buffer */ 295 int count; /* Number of vertices in buffer */ 296 int discard; /* Client finished with buffer? */ 297} drm_radeon_vertex_t; 298 299typedef struct drm_radeon_indices { 300 int prim; 301 int idx; 302 int start; 303 int end; 304 int discard; /* Client finished with buffer? */ 305} drm_radeon_indices_t; 306 307typedef struct drm_radeon_tex_image { 308 unsigned int x, y; /* Blit coordinates */ 309 unsigned int width, height; 310 const void *data; 311} drm_radeon_tex_image_t; 312 313typedef struct drm_radeon_texture { 314 int offset; 315 int pitch; 316 int format; 317 int width; /* Texture image coordinates */ 318 int height; 319 drm_radeon_tex_image_t *image; 320} drm_radeon_texture_t; 321 322typedef struct drm_radeon_stipple { 323 unsigned int *mask; 324} drm_radeon_stipple_t; 325 326typedef struct drm_radeon_indirect { 327 int idx; 328 int start; 329 int end; 330 int discard; 331} drm_radeon_indirect_t; 332 333#endif 334