1/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*- 2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com 3 * 4 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include "r128.h" 32#include "drmP.h" 33#include "r128_drv.h" 34 35#include <linux/interrupt.h> /* For task queue support */ 36#include <linux/delay.h> 37 38#define R128_FIFO_DEBUG 0 39 40 41/* CCE microcode (from ATI) */ 42static u32 r128_cce_microcode[] = { 43 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, 44 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, 45 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, 46 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, 47 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, 48 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, 49 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, 50 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, 51 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, 52 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, 53 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, 54 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, 55 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, 56 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, 57 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, 58 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, 59 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, 60 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, 61 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, 62 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, 63 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, 64 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, 65 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, 66 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, 67 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, 68 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, 69 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, 70 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, 71 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, 72 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, 73 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, 74 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, 75 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, 76 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, 77 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 78 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 82 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 83 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 84}; 85 86 87int R128_READ_PLL(drm_device_t *dev, int addr) 88{ 89 drm_r128_private_t *dev_priv = dev->dev_private; 90 91 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f); 92 return R128_READ(R128_CLOCK_CNTL_DATA); 93} 94 95#if R128_FIFO_DEBUG 96static void r128_status( drm_r128_private_t *dev_priv ) 97{ 98 printk( "GUI_STAT = 0x%08x\n", 99 (unsigned int)R128_READ( R128_GUI_STAT ) ); 100 printk( "PM4_STAT = 0x%08x\n", 101 (unsigned int)R128_READ( R128_PM4_STAT ) ); 102 printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n", 103 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) ); 104 printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n", 105 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) ); 106 printk( "PM4_MICRO_CNTL = 0x%08x\n", 107 (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) ); 108 printk( "PM4_BUFFER_CNTL = 0x%08x\n", 109 (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) ); 110} 111#endif 112 113 114/* ================================================================ 115 * Engine, FIFO control 116 */ 117 118static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv ) 119{ 120 u32 tmp; 121 int i; 122 123 tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL; 124 R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp ); 125 126 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 127 if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) { 128 return 0; 129 } 130 udelay( 1 ); 131 } 132 133#if R128_FIFO_DEBUG 134 DRM_ERROR( "%s failed!\n", __FUNCTION__ ); 135#endif 136 return -EBUSY; 137} 138 139static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries ) 140{ 141 int i; 142 143 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 144 int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK; 145 if ( slots >= entries ) return 0; 146 udelay( 1 ); 147 } 148 149#if R128_FIFO_DEBUG 150 DRM_ERROR( "%s failed!\n", __FUNCTION__ ); 151#endif 152 return -EBUSY; 153} 154 155int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ) 156{ 157 int i, ret; 158 159 ret = r128_do_wait_for_fifo( dev_priv, 64 ); 160 if ( ret < 0 ) return ret; 161 162 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 163 if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) { 164 r128_do_pixcache_flush( dev_priv ); 165 return 0; 166 } 167 udelay( 1 ); 168 } 169 170#if R128_FIFO_DEBUG 171 DRM_ERROR( "%s failed!\n", __FUNCTION__ ); 172#endif 173 return -EBUSY; 174} 175 176 177/* ================================================================ 178 * CCE control, initialization 179 */ 180 181/* Load the microcode for the CCE */ 182static void r128_cce_load_microcode( drm_r128_private_t *dev_priv ) 183{ 184 int i; 185 186 DRM_DEBUG( "%s\n", __FUNCTION__ ); 187 188 r128_do_wait_for_idle( dev_priv ); 189 190 R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 ); 191 for ( i = 0 ; i < 256 ; i++ ) { 192 R128_WRITE( R128_PM4_MICROCODE_DATAH, 193 r128_cce_microcode[i * 2] ); 194 R128_WRITE( R128_PM4_MICROCODE_DATAL, 195 r128_cce_microcode[i * 2 + 1] ); 196 } 197} 198 199/* Flush any pending commands to the CCE. This should only be used just 200 * prior to a wait for idle, as it informs the engine that the command 201 * stream is ending. 202 */ 203static void r128_do_cce_flush( drm_r128_private_t *dev_priv ) 204{ 205 u32 tmp; 206 207 tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE; 208 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp ); 209} 210 211/* Wait for the CCE to go idle. 212 */ 213int r128_do_cce_idle( drm_r128_private_t *dev_priv ) 214{ 215 int i; 216 217 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 218 if ( GET_RING_HEAD( &dev_priv->ring ) == dev_priv->ring.tail ) { 219 int pm4stat = R128_READ( R128_PM4_STAT ); 220 if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >= 221 dev_priv->cce_fifo_size ) && 222 !(pm4stat & (R128_PM4_BUSY | 223 R128_PM4_GUI_ACTIVE)) ) { 224 return r128_do_pixcache_flush( dev_priv ); 225 } 226 } 227 udelay( 1 ); 228 } 229 230#if R128_FIFO_DEBUG 231 DRM_ERROR( "failed!\n" ); 232 r128_status( dev_priv ); 233#endif 234 return -EBUSY; 235} 236 237/* Start the Concurrent Command Engine. 238 */ 239static void r128_do_cce_start( drm_r128_private_t *dev_priv ) 240{ 241 r128_do_wait_for_idle( dev_priv ); 242 243 R128_WRITE( R128_PM4_BUFFER_CNTL, 244 dev_priv->cce_mode | dev_priv->ring.size_l2qw ); 245 R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */ 246 R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN ); 247 248 dev_priv->cce_running = 1; 249} 250 251/* Reset the Concurrent Command Engine. This will not flush any pending 252 * commands, so you must wait for the CCE command stream to complete 253 * before calling this routine. 254 */ 255static void r128_do_cce_reset( drm_r128_private_t *dev_priv ) 256{ 257 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); 258 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); 259 SET_RING_HEAD( &dev_priv->ring, 0 ); 260 dev_priv->ring.tail = 0; 261} 262 263/* Stop the Concurrent Command Engine. This will not flush any pending 264 * commands, so you must flush the command stream and wait for the CCE 265 * to go idle before calling this routine. 266 */ 267static void r128_do_cce_stop( drm_r128_private_t *dev_priv ) 268{ 269 R128_WRITE( R128_PM4_MICRO_CNTL, 0 ); 270 R128_WRITE( R128_PM4_BUFFER_CNTL, R128_PM4_NONPM4 ); 271 272 dev_priv->cce_running = 0; 273} 274 275/* Reset the engine. This will stop the CCE if it is running. 276 */ 277static int r128_do_engine_reset( drm_device_t *dev ) 278{ 279 drm_r128_private_t *dev_priv = dev->dev_private; 280 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; 281 282 r128_do_pixcache_flush( dev_priv ); 283 284 clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX ); 285 mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL ); 286 287 R128_WRITE_PLL( R128_MCLK_CNTL, 288 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP ); 289 290 gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL ); 291 292 /* Taken from the sample code - do not change */ 293 R128_WRITE( R128_GEN_RESET_CNTL, 294 gen_reset_cntl | R128_SOFT_RESET_GUI ); 295 R128_READ( R128_GEN_RESET_CNTL ); 296 R128_WRITE( R128_GEN_RESET_CNTL, 297 gen_reset_cntl & ~R128_SOFT_RESET_GUI ); 298 R128_READ( R128_GEN_RESET_CNTL ); 299 300 R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl ); 301 R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index ); 302 R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl ); 303 304 /* Reset the CCE ring */ 305 r128_do_cce_reset( dev_priv ); 306 307 /* The CCE is no longer running after an engine reset */ 308 dev_priv->cce_running = 0; 309 310 /* Reset any pending vertex, indirect buffers */ 311 r128_freelist_reset( dev ); 312 313 return 0; 314} 315 316static void r128_cce_init_ring_buffer( drm_device_t *dev, 317 drm_r128_private_t *dev_priv ) 318{ 319 u32 ring_start; 320 u32 tmp; 321 322 DRM_DEBUG( "%s\n", __FUNCTION__ ); 323 324 /* The manual (p. 2) says this address is in "VM space". This 325 * means it's an offset from the start of AGP space. 326 */ 327#if __REALLY_HAVE_AGP 328 if ( !dev_priv->is_pci ) 329 ring_start = dev_priv->cce_ring->offset - dev->agp->base; 330 else 331#endif 332 ring_start = dev_priv->cce_ring->offset - dev->sg->handle; 333 334 R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET ); 335 336 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); 337 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); 338 339 /* DL_RPTR_ADDR is a physical address in AGP space. */ 340 SET_RING_HEAD( &dev_priv->ring, 0 ); 341 342 if ( !dev_priv->is_pci ) { 343 R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, 344 dev_priv->ring_rptr->offset ); 345 } else { 346 drm_sg_mem_t *entry = dev->sg; 347 unsigned long tmp_ofs, page_ofs; 348 349 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; 350 page_ofs = tmp_ofs >> PAGE_SHIFT; 351 352 R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, 353 entry->busaddr[page_ofs]); 354 DRM_DEBUG( "ring rptr: offset=0x%08llx handle=0x%08lx\n", 355 (u64)entry->busaddr[page_ofs], 356 entry->handle + tmp_ofs ); 357 } 358 359 /* Set watermark control */ 360 R128_WRITE( R128_PM4_BUFFER_WM_CNTL, 361 ((R128_WATERMARK_L/4) << R128_WMA_SHIFT) 362 | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT) 363 | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT) 364 | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) ); 365 366 /* Force read. Why? Because it's in the examples... */ 367 R128_READ( R128_PM4_BUFFER_ADDR ); 368 369 /* Turn on bus mastering */ 370 tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS; 371 R128_WRITE( R128_BUS_CNTL, tmp ); 372} 373 374static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) 375{ 376 drm_r128_private_t *dev_priv; 377 struct list_head *list; 378 379 DRM_DEBUG( "%s\n", __FUNCTION__ ); 380 381 dev_priv = DRM(alloc)( sizeof(drm_r128_private_t), DRM_MEM_DRIVER ); 382 if ( dev_priv == NULL ) 383 return -ENOMEM; 384 385 memset( dev_priv, 0, sizeof(drm_r128_private_t) ); 386 387 dev_priv->is_pci = init->is_pci; 388 389 if ( dev_priv->is_pci && !dev->sg ) { 390 DRM_ERROR( "PCI GART memory not allocated!\n" ); 391 dev->dev_private = (void *)dev_priv; 392 r128_do_cleanup_cce( dev ); 393 return -EINVAL; 394 } 395 396 dev_priv->usec_timeout = init->usec_timeout; 397 if ( dev_priv->usec_timeout < 1 || 398 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) { 399 DRM_DEBUG( "TIMEOUT problem!\n" ); 400 dev->dev_private = (void *)dev_priv; 401 r128_do_cleanup_cce( dev ); 402 return -EINVAL; 403 } 404 405 dev_priv->cce_mode = init->cce_mode; 406 407 /* GH: Simple idle check. 408 */ 409 atomic_set( &dev_priv->idle_count, 0 ); 410 411 /* We don't support anything other than bus-mastering ring mode, 412 * but the ring can be in either AGP or PCI space for the ring 413 * read pointer. 414 */ 415 if ( ( init->cce_mode != R128_PM4_192BM ) && 416 ( init->cce_mode != R128_PM4_128BM_64INDBM ) && 417 ( init->cce_mode != R128_PM4_64BM_128INDBM ) && 418 ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) { 419 DRM_DEBUG( "Bad cce_mode!\n" ); 420 dev->dev_private = (void *)dev_priv; 421 r128_do_cleanup_cce( dev ); 422 return -EINVAL; 423 } 424 425 switch ( init->cce_mode ) { 426 case R128_PM4_NONPM4: 427 dev_priv->cce_fifo_size = 0; 428 break; 429 case R128_PM4_192PIO: 430 case R128_PM4_192BM: 431 dev_priv->cce_fifo_size = 192; 432 break; 433 case R128_PM4_128PIO_64INDBM: 434 case R128_PM4_128BM_64INDBM: 435 dev_priv->cce_fifo_size = 128; 436 break; 437 case R128_PM4_64PIO_128INDBM: 438 case R128_PM4_64BM_128INDBM: 439 case R128_PM4_64PIO_64VCBM_64INDBM: 440 case R128_PM4_64BM_64VCBM_64INDBM: 441 case R128_PM4_64PIO_64VCPIO_64INDPIO: 442 dev_priv->cce_fifo_size = 64; 443 break; 444 } 445 446 switch ( init->fb_bpp ) { 447 case 16: 448 dev_priv->color_fmt = R128_DATATYPE_RGB565; 449 break; 450 case 32: 451 default: 452 dev_priv->color_fmt = R128_DATATYPE_ARGB8888; 453 break; 454 } 455 dev_priv->front_offset = init->front_offset; 456 dev_priv->front_pitch = init->front_pitch; 457 dev_priv->back_offset = init->back_offset; 458 dev_priv->back_pitch = init->back_pitch; 459 460 switch ( init->depth_bpp ) { 461 case 16: 462 dev_priv->depth_fmt = R128_DATATYPE_RGB565; 463 break; 464 case 24: 465 case 32: 466 default: 467 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888; 468 break; 469 } 470 dev_priv->depth_offset = init->depth_offset; 471 dev_priv->depth_pitch = init->depth_pitch; 472 dev_priv->span_offset = init->span_offset; 473 474 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) | 475 (dev_priv->front_offset >> 5)); 476 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) | 477 (dev_priv->back_offset >> 5)); 478 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | 479 (dev_priv->depth_offset >> 5) | 480 R128_DST_TILE); 481 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | 482 (dev_priv->span_offset >> 5)); 483 484 list_for_each(list, &dev->maplist->head) { 485 drm_map_list_t *r_list = (drm_map_list_t *)list; 486 if( r_list->map && 487 r_list->map->type == _DRM_SHM && 488 r_list->map->flags & _DRM_CONTAINS_LOCK ) { 489 dev_priv->sarea = r_list->map; 490 break; 491 } 492 } 493 if(!dev_priv->sarea) { 494 DRM_ERROR("could not find sarea!\n"); 495 dev->dev_private = (void *)dev_priv; 496 r128_do_cleanup_cce( dev ); 497 return -EINVAL; 498 } 499 500 DRM_FIND_MAP( dev_priv->fb, init->fb_offset ); 501 if(!dev_priv->fb) { 502 DRM_ERROR("could not find framebuffer!\n"); 503 dev->dev_private = (void *)dev_priv; 504 r128_do_cleanup_cce( dev ); 505 return -EINVAL; 506 } 507 DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset ); 508 if(!dev_priv->mmio) { 509 DRM_ERROR("could not find mmio region!\n"); 510 dev->dev_private = (void *)dev_priv; 511 r128_do_cleanup_cce( dev ); 512 return -EINVAL; 513 } 514 DRM_FIND_MAP( dev_priv->cce_ring, init->ring_offset ); 515 if(!dev_priv->cce_ring) { 516 DRM_ERROR("could not find cce ring region!\n"); 517 dev->dev_private = (void *)dev_priv; 518 r128_do_cleanup_cce( dev ); 519 return -EINVAL; 520 } 521 DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset ); 522 if(!dev_priv->ring_rptr) { 523 DRM_ERROR("could not find ring read pointer!\n"); 524 dev->dev_private = (void *)dev_priv; 525 r128_do_cleanup_cce( dev ); 526 return -EINVAL; 527 } 528 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset ); 529 if(!dev_priv->buffers) { 530 DRM_ERROR("could not find dma buffer region!\n"); 531 dev->dev_private = (void *)dev_priv; 532 r128_do_cleanup_cce( dev ); 533 return -EINVAL; 534 } 535 536 if ( !dev_priv->is_pci ) { 537 DRM_FIND_MAP( dev_priv->agp_textures, 538 init->agp_textures_offset ); 539 if(!dev_priv->agp_textures) { 540 DRM_ERROR("could not find agp texture region!\n"); 541 dev->dev_private = (void *)dev_priv; 542 r128_do_cleanup_cce( dev ); 543 return -EINVAL; 544 } 545 } 546 547 dev_priv->sarea_priv = 548 (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle + 549 init->sarea_priv_offset); 550 551 if ( !dev_priv->is_pci ) { 552 DRM_IOREMAP( dev_priv->cce_ring ); 553 DRM_IOREMAP( dev_priv->ring_rptr ); 554 DRM_IOREMAP( dev_priv->buffers ); 555 if(!dev_priv->cce_ring->handle || 556 !dev_priv->ring_rptr->handle || 557 !dev_priv->buffers->handle) { 558 DRM_ERROR("Could not ioremap agp regions!\n"); 559 dev->dev_private = (void *)dev_priv; 560 r128_do_cleanup_cce( dev ); 561 return -ENOMEM; 562 } 563 } else { 564 dev_priv->cce_ring->handle = 565 (void *)dev_priv->cce_ring->offset; 566 dev_priv->ring_rptr->handle = 567 (void *)dev_priv->ring_rptr->offset; 568 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset; 569 } 570 571#if __REALLY_HAVE_AGP 572 if ( !dev_priv->is_pci ) 573 dev_priv->cce_buffers_offset = dev->agp->base; 574 else 575#endif 576 dev_priv->cce_buffers_offset = dev->sg->handle; 577 578 dev_priv->ring.head = ((__volatile__ u32 *) 579 dev_priv->ring_rptr->handle); 580 581 dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle; 582 dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle 583 + init->ring_size / sizeof(u32)); 584 dev_priv->ring.size = init->ring_size; 585 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 ); 586 587 dev_priv->ring.tail_mask = 588 (dev_priv->ring.size / sizeof(u32)) - 1; 589 590 dev_priv->ring.high_mark = 128; 591 592 dev_priv->sarea_priv->last_frame = 0; 593 R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); 594 595 dev_priv->sarea_priv->last_dispatch = 0; 596 R128_WRITE( R128_LAST_DISPATCH_REG, 597 dev_priv->sarea_priv->last_dispatch ); 598 599 if ( dev_priv->is_pci ) { 600 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart, 601 &dev_priv->bus_pci_gart) ) { 602 DRM_ERROR( "failed to init PCI GART!\n" ); 603 dev->dev_private = (void *)dev_priv; 604 r128_do_cleanup_cce( dev ); 605 return -ENOMEM; 606 } 607 R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart ); 608 } 609 610 r128_cce_init_ring_buffer( dev, dev_priv ); 611 r128_cce_load_microcode( dev_priv ); 612 613 dev->dev_private = (void *)dev_priv; 614 615 r128_do_engine_reset( dev ); 616 617 return 0; 618} 619 620int r128_do_cleanup_cce( drm_device_t *dev ) 621{ 622 if ( dev->dev_private ) { 623 drm_r128_private_t *dev_priv = dev->dev_private; 624 625 if ( !dev_priv->is_pci ) { 626 DRM_IOREMAPFREE( dev_priv->cce_ring ); 627 DRM_IOREMAPFREE( dev_priv->ring_rptr ); 628 DRM_IOREMAPFREE( dev_priv->buffers ); 629 } else { 630 if (!DRM(ati_pcigart_cleanup)( dev, 631 dev_priv->phys_pci_gart, 632 dev_priv->bus_pci_gart )) 633 DRM_ERROR( "failed to cleanup PCI GART!\n" ); 634 } 635 636 DRM(free)( dev->dev_private, sizeof(drm_r128_private_t), 637 DRM_MEM_DRIVER ); 638 dev->dev_private = NULL; 639 } 640 641 return 0; 642} 643 644int r128_cce_init( struct inode *inode, struct file *filp, 645 unsigned int cmd, unsigned long arg ) 646{ 647 drm_file_t *priv = filp->private_data; 648 drm_device_t *dev = priv->dev; 649 drm_r128_init_t init; 650 651 DRM_DEBUG( "%s\n", __FUNCTION__ ); 652 653 if ( copy_from_user( &init, (drm_r128_init_t *)arg, sizeof(init) ) ) 654 return -EFAULT; 655 656 switch ( init.func ) { 657 case R128_INIT_CCE: 658 return r128_do_init_cce( dev, &init ); 659 case R128_CLEANUP_CCE: 660 return r128_do_cleanup_cce( dev ); 661 } 662 663 return -EINVAL; 664} 665 666int r128_cce_start( struct inode *inode, struct file *filp, 667 unsigned int cmd, unsigned long arg ) 668{ 669 drm_file_t *priv = filp->private_data; 670 drm_device_t *dev = priv->dev; 671 drm_r128_private_t *dev_priv = dev->dev_private; 672 DRM_DEBUG( "%s\n", __FUNCTION__ ); 673 674 LOCK_TEST_WITH_RETURN( dev ); 675 676 if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) { 677 DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ ); 678 return 0; 679 } 680 681 r128_do_cce_start( dev_priv ); 682 683 return 0; 684} 685 686/* Stop the CCE. The engine must have been idled before calling this 687 * routine. 688 */ 689int r128_cce_stop( struct inode *inode, struct file *filp, 690 unsigned int cmd, unsigned long arg ) 691{ 692 drm_file_t *priv = filp->private_data; 693 drm_device_t *dev = priv->dev; 694 drm_r128_private_t *dev_priv = dev->dev_private; 695 drm_r128_cce_stop_t stop; 696 int ret; 697 DRM_DEBUG( "%s\n", __FUNCTION__ ); 698 699 LOCK_TEST_WITH_RETURN( dev ); 700 701 if ( copy_from_user( &stop, (drm_r128_init_t *)arg, sizeof(stop) ) ) 702 return -EFAULT; 703 704 /* Flush any pending CCE commands. This ensures any outstanding 705 * commands are exectuted by the engine before we turn it off. 706 */ 707 if ( stop.flush ) { 708 r128_do_cce_flush( dev_priv ); 709 } 710 711 /* If we fail to make the engine go idle, we return an error 712 * code so that the DRM ioctl wrapper can try again. 713 */ 714 if ( stop.idle ) { 715 ret = r128_do_cce_idle( dev_priv ); 716 if ( ret < 0 ) return ret; 717 } 718 719 /* Finally, we can turn off the CCE. If the engine isn't idle, 720 * we will get some dropped triangles as they won't be fully 721 * rendered before the CCE is shut down. 722 */ 723 r128_do_cce_stop( dev_priv ); 724 725 /* Reset the engine */ 726 r128_do_engine_reset( dev ); 727 728 return 0; 729} 730 731/* Just reset the CCE ring. Called as part of an X Server engine reset. 732 */ 733int r128_cce_reset( struct inode *inode, struct file *filp, 734 unsigned int cmd, unsigned long arg ) 735{ 736 drm_file_t *priv = filp->private_data; 737 drm_device_t *dev = priv->dev; 738 drm_r128_private_t *dev_priv = dev->dev_private; 739 DRM_DEBUG( "%s\n", __FUNCTION__ ); 740 741 LOCK_TEST_WITH_RETURN( dev ); 742 743 if ( !dev_priv ) { 744 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); 745 return -EINVAL; 746 } 747 748 r128_do_cce_reset( dev_priv ); 749 750 /* The CCE is no longer running after an engine reset */ 751 dev_priv->cce_running = 0; 752 753 return 0; 754} 755 756int r128_cce_idle( struct inode *inode, struct file *filp, 757 unsigned int cmd, unsigned long arg ) 758{ 759 drm_file_t *priv = filp->private_data; 760 drm_device_t *dev = priv->dev; 761 drm_r128_private_t *dev_priv = dev->dev_private; 762 DRM_DEBUG( "%s\n", __FUNCTION__ ); 763 764 LOCK_TEST_WITH_RETURN( dev ); 765 766 if ( dev_priv->cce_running ) { 767 r128_do_cce_flush( dev_priv ); 768 } 769 770 return r128_do_cce_idle( dev_priv ); 771} 772 773int r128_engine_reset( struct inode *inode, struct file *filp, 774 unsigned int cmd, unsigned long arg ) 775{ 776 drm_file_t *priv = filp->private_data; 777 drm_device_t *dev = priv->dev; 778 DRM_DEBUG( "%s\n", __FUNCTION__ ); 779 780 LOCK_TEST_WITH_RETURN( dev ); 781 782 return r128_do_engine_reset( dev ); 783} 784 785 786/* ================================================================ 787 * Fullscreen mode 788 */ 789 790static int r128_do_init_pageflip( drm_device_t *dev ) 791{ 792 drm_r128_private_t *dev_priv = dev->dev_private; 793 DRM_DEBUG( "%s\n", __FUNCTION__ ); 794 795 dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET ); 796 dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL ); 797 798 R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset ); 799 R128_WRITE( R128_CRTC_OFFSET_CNTL, 800 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL ); 801 802 dev_priv->page_flipping = 1; 803 dev_priv->current_page = 0; 804 805 return 0; 806} 807 808int r128_do_cleanup_pageflip( drm_device_t *dev ) 809{ 810 drm_r128_private_t *dev_priv = dev->dev_private; 811 DRM_DEBUG( "%s\n", __FUNCTION__ ); 812 813 R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset ); 814 R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl ); 815 816 dev_priv->page_flipping = 0; 817 dev_priv->current_page = 0; 818 819 return 0; 820} 821 822int r128_fullscreen( struct inode *inode, struct file *filp, 823 unsigned int cmd, unsigned long arg ) 824{ 825 drm_file_t *priv = filp->private_data; 826 drm_device_t *dev = priv->dev; 827 drm_r128_fullscreen_t fs; 828 829 LOCK_TEST_WITH_RETURN( dev ); 830 831 if ( copy_from_user( &fs, (drm_r128_fullscreen_t *)arg, sizeof(fs) ) ) 832 return -EFAULT; 833 834 switch ( fs.func ) { 835 case R128_INIT_FULLSCREEN: 836 return r128_do_init_pageflip( dev ); 837 case R128_CLEANUP_FULLSCREEN: 838 return r128_do_cleanup_pageflip( dev ); 839 } 840 841 return -EINVAL; 842} 843 844 845/* ================================================================ 846 * Freelist management 847 */ 848#define R128_BUFFER_USED 0xffffffff 849#define R128_BUFFER_FREE 0 850 851 852drm_buf_t *r128_freelist_get( drm_device_t *dev ) 853{ 854 drm_device_dma_t *dma = dev->dma; 855 drm_r128_private_t *dev_priv = dev->dev_private; 856 drm_r128_buf_priv_t *buf_priv; 857 drm_buf_t *buf; 858 int i, t; 859 860 861 for ( i = 0 ; i < dma->buf_count ; i++ ) { 862 buf = dma->buflist[i]; 863 buf_priv = buf->dev_private; 864 if ( buf->pid == 0 ) 865 return buf; 866 } 867 868 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { 869 u32 done_age = R128_READ( R128_LAST_DISPATCH_REG ); 870 871 for ( i = 0 ; i < dma->buf_count ; i++ ) { 872 buf = dma->buflist[i]; 873 buf_priv = buf->dev_private; 874 if ( buf->pending && buf_priv->age <= done_age ) { 875 /* The buffer has been processed, so it 876 * can now be used. 877 */ 878 buf->pending = 0; 879 return buf; 880 } 881 } 882 udelay( 1 ); 883 } 884 885 DRM_ERROR( "returning NULL!\n" ); 886 return NULL; 887} 888 889void r128_freelist_reset( drm_device_t *dev ) 890{ 891 drm_device_dma_t *dma = dev->dma; 892 int i; 893 894 for ( i = 0 ; i < dma->buf_count ; i++ ) { 895 drm_buf_t *buf = dma->buflist[i]; 896 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 897 buf_priv->age = 0; 898 } 899} 900 901 902/* ================================================================ 903 * CCE command submission 904 */ 905 906int r128_wait_ring( drm_r128_private_t *dev_priv, int n ) 907{ 908 drm_r128_ring_buffer_t *ring = &dev_priv->ring; 909 int i; 910 911 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 912 r128_update_ring_snapshot( ring ); 913 if ( ring->space >= n ) 914 return 0; 915 udelay( 1 ); 916 } 917 918 DRM_ERROR( "failed!\n" ); 919 return -EBUSY; 920} 921 922static int r128_cce_get_buffers( drm_device_t *dev, drm_dma_t *d ) 923{ 924 int i; 925 drm_buf_t *buf; 926 927 for ( i = d->granted_count ; i < d->request_count ; i++ ) { 928 buf = r128_freelist_get( dev ); 929 if ( !buf ) return -EAGAIN; 930 931 buf->pid = current->pid; 932 933 if ( copy_to_user( &d->request_indices[i], &buf->idx, 934 sizeof(buf->idx) ) ) 935 return -EFAULT; 936 if ( copy_to_user( &d->request_sizes[i], &buf->total, 937 sizeof(buf->total) ) ) 938 return -EFAULT; 939 940 d->granted_count++; 941 } 942 return 0; 943} 944 945int r128_cce_buffers( struct inode *inode, struct file *filp, 946 unsigned int cmd, unsigned long arg ) 947{ 948 drm_file_t *priv = filp->private_data; 949 drm_device_t *dev = priv->dev; 950 drm_device_dma_t *dma = dev->dma; 951 int ret = 0; 952 drm_dma_t d; 953 954 LOCK_TEST_WITH_RETURN( dev ); 955 956 if ( copy_from_user( &d, (drm_dma_t *) arg, sizeof(d) ) ) 957 return -EFAULT; 958 959 /* Please don't send us buffers. 960 */ 961 if ( d.send_count != 0 ) { 962 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", 963 current->pid, d.send_count ); 964 return -EINVAL; 965 } 966 967 /* We'll send you buffers. 968 */ 969 if ( d.request_count < 0 || d.request_count > dma->buf_count ) { 970 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", 971 current->pid, d.request_count, dma->buf_count ); 972 return -EINVAL; 973 } 974 975 d.granted_count = 0; 976 977 if ( d.request_count ) { 978 ret = r128_cce_get_buffers( dev, &d ); 979 } 980 981 if ( copy_to_user( (drm_dma_t *) arg, &d, sizeof(d) ) ) 982 return -EFAULT; 983 984 return ret; 985} 986