1/* 2 Madge Horizon ATM Adapter driver. 3 Copyright (C) 1995-1999 Madge Networks Ltd. 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian 20 system and in the file COPYING in the Linux kernel source. 21*/ 22 23/* 24 IMPORTANT NOTE: Madge Networks no longer makes the adapters 25 supported by this driver and makes no commitment to maintain it. 26*/ 27 28/* too many macros - change to inline functions */ 29 30#ifndef DRIVER_ATM_HORIZON_H 31#define DRIVER_ATM_HORIZON_H 32 33#include <linux/config.h> 34#include <linux/version.h> 35 36#ifdef CONFIG_ATM_HORIZON_DEBUG 37#define DEBUG_HORIZON 38#endif 39 40#define DEV_LABEL "hrz" 41 42#ifndef PCI_VENDOR_ID_MADGE 43#define PCI_VENDOR_ID_MADGE 0x10B6 44#endif 45#ifndef PCI_DEVICE_ID_MADGE_HORIZON 46#define PCI_DEVICE_ID_MADGE_HORIZON 0x1000 47#endif 48 49// diagnostic output 50 51#define PRINTK(severity,format,args...) \ 52 printk(severity DEV_LABEL ": " format "\n" , ## args) 53 54#ifdef DEBUG_HORIZON 55 56#define DBG_ERR 0x0001 57#define DBG_WARN 0x0002 58#define DBG_INFO 0x0004 59#define DBG_VCC 0x0008 60#define DBG_QOS 0x0010 61#define DBG_TX 0x0020 62#define DBG_RX 0x0040 63#define DBG_SKB 0x0080 64#define DBG_IRQ 0x0100 65#define DBG_FLOW 0x0200 66#define DBG_BUS 0x0400 67#define DBG_REGS 0x0800 68#define DBG_DATA 0x1000 69#define DBG_MASK 0x1fff 70 71/* the ## prevents the annoying double expansion of the macro arguments */ 72/* KERN_INFO is used since KERN_DEBUG often does not make it to the console */ 73#define PRINTDB(bits,format,args...) \ 74 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 ) 75#define PRINTDM(bits,format,args...) \ 76 ( (debug & (bits)) ? printk (format , ## args) : 1 ) 77#define PRINTDE(bits,format,args...) \ 78 ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 ) 79#define PRINTD(bits,format,args...) \ 80 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 ) 81 82#else 83 84#define PRINTD(bits,format,args...) 85#define PRINTDB(bits,format,args...) 86#define PRINTDM(bits,format,args...) 87#define PRINTDE(bits,format,args...) 88 89#endif 90 91#define PRINTDD(sec,fmt,args...) 92#define PRINTDDB(sec,fmt,args...) 93#define PRINTDDM(sec,fmt,args...) 94#define PRINTDDE(sec,fmt,args...) 95 96// fixed constants 97 98#define SPARE_BUFFER_POOL_SIZE MAX_VCS 99#define HRZ_MAX_VPI 4 100#define MIN_PCI_LATENCY 48 // 24 IS TOO SMALL 101 102/* Horizon specific bits */ 103/* Register offsets */ 104 105#define HRZ_IO_EXTENT 0x80 106 107#define DATA_PORT_OFF 0x00 108#define TX_CHANNEL_PORT_OFF 0x04 109#define TX_DESCRIPTOR_PORT_OFF 0x08 110#define MEMORY_PORT_OFF 0x0C 111#define MEM_WR_ADDR_REG_OFF 0x14 112#define MEM_RD_ADDR_REG_OFF 0x18 113#define CONTROL_0_REG 0x1C 114#define INT_SOURCE_REG_OFF 0x20 115#define INT_ENABLE_REG_OFF 0x24 116#define MASTER_RX_ADDR_REG_OFF 0x28 117#define MASTER_RX_COUNT_REG_OFF 0x2C 118#define MASTER_TX_ADDR_REG_OFF 0x30 119#define MASTER_TX_COUNT_REG_OFF 0x34 120#define TX_DESCRIPTOR_REG_OFF 0x38 121#define TX_CHANNEL_CONFIG_COMMAND_OFF 0x40 122#define TX_CHANNEL_CONFIG_DATA_OFF 0x44 123#define TX_FREE_BUFFER_COUNT_OFF 0x48 124#define RX_FREE_BUFFER_COUNT_OFF 0x4C 125#define TX_CONFIG_OFF 0x50 126#define TX_STATUS_OFF 0x54 127#define RX_CONFIG_OFF 0x58 128#define RX_LINE_CONFIG_OFF 0x5C 129#define RX_QUEUE_RD_PTR_OFF 0x60 130#define RX_QUEUE_WR_PTR_OFF 0x64 131#define MAX_AAL5_CELL_COUNT_OFF 0x68 132#define RX_CHANNEL_PORT_OFF 0x6C 133#define TX_CELL_COUNT_OFF 0x70 134#define RX_CELL_COUNT_OFF 0x74 135#define HEC_ERROR_COUNT_OFF 0x78 136#define UNASSIGNED_CELL_COUNT_OFF 0x7C 137 138/* Register bit definitions */ 139 140/* Control 0 register */ 141 142#define SEEPROM_DO 0x00000001 143#define SEEPROM_DI 0x00000002 144#define SEEPROM_SK 0x00000004 145#define SEEPROM_CS 0x00000008 146#define DEBUG_BIT_0 0x00000010 147#define DEBUG_BIT_1 0x00000020 148#define DEBUG_BIT_2 0x00000040 149// RESERVED 0x00000080 150#define DEBUG_BIT_0_OE 0x00000100 151#define DEBUG_BIT_1_OE 0x00000200 152#define DEBUG_BIT_2_OE 0x00000400 153// RESERVED 0x00000800 154#define DEBUG_BIT_0_STATE 0x00001000 155#define DEBUG_BIT_1_STATE 0x00002000 156#define DEBUG_BIT_2_STATE 0x00004000 157// RESERVED 0x00008000 158#define GENERAL_BIT_0 0x00010000 159#define GENERAL_BIT_1 0x00020000 160#define GENERAL_BIT_2 0x00040000 161#define GENERAL_BIT_3 0x00080000 162#define RESET_HORIZON 0x00100000 163#define RESET_ATM 0x00200000 164#define RESET_RX 0x00400000 165#define RESET_TX 0x00800000 166#define RESET_HOST 0x01000000 167// RESERVED 0x02000000 168#define TARGET_RETRY_DISABLE 0x04000000 169#define ATM_LAYER_SELECT 0x08000000 170#define ATM_LAYER_STATUS 0x10000000 171// RESERVED 0xE0000000 172 173/* Interrupt source and enable registers */ 174 175#define RX_DATA_AV 0x00000001 176#define RX_DISABLED 0x00000002 177#define TIMING_MARKER 0x00000004 178#define FORCED 0x00000008 179#define RX_BUS_MASTER_COMPLETE 0x00000010 180#define TX_BUS_MASTER_COMPLETE 0x00000020 181#define ABR_TX_CELL_COUNT_INT 0x00000040 182#define DEBUG_INT 0x00000080 183// RESERVED 0xFFFFFF00 184 185/* PIO and Bus Mastering */ 186 187#define MAX_PIO_COUNT 0x000000ff // 255 - make tunable? 188// 8188 is a hard limit for bus mastering 189#define MAX_TRANSFER_COUNT 0x00001ffc // 8188 190#define MASTER_TX_AUTO_APPEND_DESC 0x80000000 191 192/* TX channel config command port */ 193 194#define PCR_TIMER_ACCESS 0x0000 195#define SCR_TIMER_ACCESS 0x0001 196#define BUCKET_CAPACITY_ACCESS 0x0002 197#define BUCKET_FULLNESS_ACCESS 0x0003 198#define RATE_TYPE_ACCESS 0x0004 199// UNUSED 0x00F8 200#define TX_CHANNEL_CONFIG_MULT 0x0100 201// UNUSED 0xF800 202#define BUCKET_MAX_SIZE 0x003f 203 204/* TX channel config data port */ 205 206#define CLOCK_SELECT_SHIFT 4 207#define CLOCK_DISABLE 0x00ff 208 209#define IDLE_RATE_TYPE 0x0 210#define ABR_RATE_TYPE 0x1 211#define VBR_RATE_TYPE 0x2 212#define CBR_RATE_TYPE 0x3 213 214/* TX config register */ 215 216#define DRVR_DRVRBAR_ENABLE 0x0001 217#define TXCLK_MUX_SELECT_RCLK 0x0002 218#define TRANSMIT_TIMING_MARKER 0x0004 219#define LOOPBACK_TIMING_MARKER 0x0008 220#define TX_TEST_MODE_16MHz 0x0000 221#define TX_TEST_MODE_8MHz 0x0010 222#define TX_TEST_MODE_5_33MHz 0x0020 223#define TX_TEST_MODE_4MHz 0x0030 224#define TX_TEST_MODE_3_2MHz 0x0040 225#define TX_TEST_MODE_2_66MHz 0x0050 226#define TX_TEST_MODE_2_29MHz 0x0060 227#define TX_NORMAL_OPERATION 0x0070 228#define ABR_ROUND_ROBIN 0x0080 229 230/* TX status register */ 231 232#define IDLE_CHANNELS_MASK 0x00FF 233#define ABR_CELL_COUNT_REACHED_MULT 0x0100 234#define ABR_CELL_COUNT_REACHED_MASK 0xFF 235 236/* RX config register */ 237 238#define NON_USER_CELLS_IN_ONE_CHANNEL 0x0008 239#define RX_ENABLE 0x0010 240#define IGNORE_UNUSED_VPI_VCI_BITS_SET 0x0000 241#define NON_USER_UNUSED_VPI_VCI_BITS_SET 0x0020 242#define DISCARD_UNUSED_VPI_VCI_BITS_SET 0x0040 243 244/* RX line config register */ 245 246#define SIGNAL_LOSS 0x0001 247#define FREQUENCY_DETECT_ERROR 0x0002 248#define LOCK_DETECT_ERROR 0x0004 249#define SELECT_INTERNAL_LOOPBACK 0x0008 250#define LOCK_DETECT_ENABLE 0x0010 251#define FREQUENCY_DETECT_ENABLE 0x0020 252#define USER_FRAQ 0x0040 253#define GXTALOUT_SELECT_DIV4 0x0080 254#define GXTALOUT_SELECT_NO_GATING 0x0100 255#define TIMING_MARKER_RECEIVED 0x0200 256 257/* RX channel port */ 258 259#define RX_CHANNEL_MASK 0x03FF 260// UNUSED 0x3C00 261#define FLUSH_CHANNEL 0x4000 262#define RX_CHANNEL_UPDATE_IN_PROGRESS 0x8000 263 264/* Receive queue entry */ 265 266#define RX_Q_ENTRY_LENGTH_MASK 0x0000FFFF 267#define RX_Q_ENTRY_CHANNEL_SHIFT 16 268#define SIMONS_DODGEY_MARKER 0x08000000 269#define RX_CONGESTION_EXPERIENCED 0x10000000 270#define RX_CRC_10_OK 0x20000000 271#define RX_CRC_32_OK 0x40000000 272#define RX_COMPLETE_FRAME 0x80000000 273 274/* Offsets and constants for use with the buffer memory */ 275 276/* Buffer pointers and channel types */ 277 278#define BUFFER_PTR_MASK 0x0000FFFF 279#define RX_INT_THRESHOLD_MULT 0x00010000 280#define RX_INT_THRESHOLD_MASK 0x07FF 281#define INT_EVERY_N_CELLS 0x08000000 282#define CONGESTION_EXPERIENCED 0x10000000 283#define FIRST_CELL_OF_AAL5_FRAME 0x20000000 284#define CHANNEL_TYPE_AAL5 0x00000000 285#define CHANNEL_TYPE_RAW_CELLS 0x40000000 286#define CHANNEL_TYPE_AAL3_4 0x80000000 287 288/* Buffer status stuff */ 289 290#define BUFF_STATUS_MASK 0x00030000 291#define BUFF_STATUS_EMPTY 0x00000000 292#define BUFF_STATUS_CELL_AV 0x00010000 293#define BUFF_STATUS_LAST_CELL_AV 0x00020000 294 295/* Transmit channel stuff */ 296 297/* Receive channel stuff */ 298 299#define RX_CHANNEL_DISABLED 0x00000000 300#define RX_CHANNEL_IDLE 0x00000001 301 302/* General things */ 303 304#define INITIAL_CRC 0xFFFFFFFF 305 306// A Horizon u32, a byte! Really nasty. Horizon pointers are (32 bit) 307// word addresses and so standard C pointer operations break (as they 308// assume byte addresses); so we pretend that Horizon words (and word 309// pointers) are bytes (and byte pointers) for the purposes of having 310// a memory map that works. 311 312typedef u8 HDW; 313 314typedef struct cell_buf { 315 HDW payload[12]; 316 HDW next; 317 HDW cell_count; // AAL5 rx bufs 318 HDW res; 319 union { 320 HDW partial_crc; // AAL5 rx bufs 321 HDW cell_header; // RAW bufs 322 } u; 323} cell_buf; 324 325typedef struct tx_ch_desc { 326 HDW rd_buf_type; 327 HDW wr_buf_type; 328 HDW partial_crc; 329 HDW cell_header; 330} tx_ch_desc; 331 332typedef struct rx_ch_desc { 333 HDW wr_buf_type; 334 HDW rd_buf_type; 335} rx_ch_desc; 336 337typedef struct rx_q_entry { 338 HDW entry; 339} rx_q_entry; 340 341#define TX_CHANS 8 342#define RX_CHANS 1024 343#define RX_QS 1024 344#define MAX_VCS RX_CHANS 345 346/* Horizon buffer memory map */ 347 348// TX Channel Descriptors 2 349// TX Initial Buffers 8 // TX_CHANS 350#define BUFN1_SIZE 118 // (126 - TX_CHANS) 351// RX/TX Start/End Buffers 4 352#define BUFN2_SIZE 124 353// RX Queue Entries 64 354#define BUFN3_SIZE 192 355// RX Channel Descriptors 128 356#define BUFN4_SIZE 1408 357// TOTAL cell_buff chunks 2048 358 359// cell_buf bufs[2048]; 360// HDW dws[32768]; 361 362typedef struct MEMMAP { 363 tx_ch_desc tx_descs[TX_CHANS]; // 8 * 4 = 32 , 0x0020 364 cell_buf inittxbufs[TX_CHANS]; // these are really 365 cell_buf bufn1[BUFN1_SIZE]; // part of this pool 366 cell_buf txfreebufstart; 367 cell_buf txfreebufend; 368 cell_buf rxfreebufstart; 369 cell_buf rxfreebufend; // 8+118+1+1+1+1+124 = 254 370 cell_buf bufn2[BUFN2_SIZE]; // 16 * 254 = 4064 , 0x1000 371 rx_q_entry rx_q_entries[RX_QS]; // 1 * 1024 = 1024 , 0x1400 372 cell_buf bufn3[BUFN3_SIZE]; // 16 * 192 = 3072 , 0x2000 373 rx_ch_desc rx_descs[MAX_VCS]; // 2 * 1024 = 2048 , 0x2800 374 cell_buf bufn4[BUFN4_SIZE]; // 16 * 1408 = 22528 , 0x8000 375} MEMMAP; 376 377#define memmap ((MEMMAP *)0) 378 379/* end horizon specific bits */ 380 381typedef enum { 382 aal0, 383 aal34, 384 aal5 385} hrz_aal; 386 387typedef enum { 388 tx_busy, 389 rx_busy, 390 ultra 391} hrz_flags; 392 393// a single struct pointed to by atm_vcc->dev_data 394 395typedef struct { 396 unsigned int tx_rate; 397 unsigned int rx_rate; 398 u16 channel; 399 u16 tx_xbr_bits; 400 u16 tx_pcr_bits; 401 hrz_aal aal; 402} hrz_vcc; 403 404struct hrz_dev { 405 406 u32 iobase; 407 u32 * membase; 408 409 struct sk_buff * rx_skb; // skb being RXed 410 unsigned int rx_bytes; // bytes remaining to RX within region 411 void * rx_addr; // addr to send bytes to (for PIO) 412 unsigned int rx_channel; // channel that the skb is going out on 413 414 struct sk_buff * tx_skb; // skb being TXed 415 unsigned int tx_bytes; // bytes remaining to TX within region 416 void * tx_addr; // addr to send bytes from (for PIO) 417 struct iovec * tx_iovec; // remaining regions 418 unsigned int tx_regions; // number of remaining regions 419 420 spinlock_t mem_lock; 421#if LINUX_VERSION_CODE >= 0x20303 422 wait_queue_head_t tx_queue; 423#else 424 struct wait_queue * tx_queue; 425#endif 426 427 u8 irq; 428 u8 flags; 429 u8 tx_last; 430 u8 tx_idle; 431 432 rx_q_entry * rx_q_reset; 433 rx_q_entry * rx_q_entry; 434 rx_q_entry * rx_q_wrap; 435 436 struct atm_dev * atm_dev; 437 438 u32 last_vc; 439 440 int noof_spare_buffers; 441 u16 spare_buffers[SPARE_BUFFER_POOL_SIZE]; 442 443 u16 tx_channel_record[TX_CHANS]; 444 445 // this is what we follow when we get incoming data 446 u32 txer[MAX_VCS/32]; 447 struct atm_vcc * rxer[MAX_VCS]; 448 449 // cell rate allocation 450 spinlock_t rate_lock; 451 unsigned int rx_avail; 452 unsigned int tx_avail; 453 454 // dev stats 455 unsigned long tx_cell_count; 456 unsigned long rx_cell_count; 457 unsigned long hec_error_count; 458 unsigned long unassigned_cell_count; 459 460 struct pci_dev * pci_dev; 461 struct hrz_dev * prev; 462}; 463 464typedef struct hrz_dev hrz_dev; 465 466/* macros for use later */ 467 468#define BUF_PTR(cbptr) ((cbptr) - (cell_buf *) 0) 469 470#define INTERESTING_INTERRUPTS \ 471 (RX_DATA_AV | RX_DISABLED | TX_BUS_MASTER_COMPLETE | RX_BUS_MASTER_COMPLETE) 472 473// 190 cells by default (192 TX buffers - 2 elbow room, see docs) 474#define TX_AAL5_LIMIT (190*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER) // 9112 475 476// Have enough RX buffers (unless we allow other buffer splits) 477#define RX_AAL5_LIMIT ATM_MAX_AAL5_PDU 478 479/* multi-statement macro protector */ 480#define DW(x) do{ x } while(0) 481 482#define HRZ_DEV(atm_dev) ((hrz_dev *) (atm_dev)->dev_data) 483#define HRZ_VCC(atm_vcc) ((hrz_vcc *) (atm_vcc)->dev_data) 484 485/* Turn the LEDs on and off */ 486// The LEDs bits are upside down in that setting the bit in the debug 487// register will turn the appropriate LED off. 488 489#define YELLOW_LED DEBUG_BIT_0 490#define GREEN_LED DEBUG_BIT_1 491#define YELLOW_LED_OE DEBUG_BIT_0_OE 492#define GREEN_LED_OE DEBUG_BIT_1_OE 493 494#define GREEN_LED_OFF(dev) \ 495 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED) 496#define GREEN_LED_ON(dev) \ 497 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED) 498#define YELLOW_LED_OFF(dev) \ 499 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED) 500#define YELLOW_LED_ON(dev) \ 501 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED) 502 503typedef enum { 504 round_up, 505 round_down, 506 round_nearest 507} rounding; 508 509#endif /* DRIVER_ATM_HORIZON_H */ 510