1/* 2 * Low-Level PCI Support for the SH7751 3 * 4 * Dustin McIntire (dustin@sensoria.com) 5 * Derived from arch/i386/kernel/pci-*.c which bore the message: 6 * (c) 1999--2000 Martin Mares <mj@ucw.cz> 7 * 8 * May be copied or modified under the terms of the GNU General Public 9 * License. See linux/COPYING for more information. 10 * 11*/ 12 13#include <linux/config.h> 14#include <linux/types.h> 15#include <linux/kernel.h> 16#include <linux/init.h> 17#include <linux/pci.h> 18#include <linux/sched.h> 19#include <linux/ioport.h> 20#include <linux/errno.h> 21#include <linux/irq.h> 22 23#include <asm/machvec.h> 24#include <asm/io.h> 25#include <asm/pci-sh7751.h> 26 27struct pci_ops *pci_check_direct(void); 28void pcibios_resource_survey(void); 29static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin); 30static int pcibios_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin); 31 32unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1; 33int pcibios_last_bus = -1; 34struct pci_bus *pci_root_bus; 35struct pci_ops *pci_root_ops; 36 37/* 38 * Direct access to PCI hardware... 39 */ 40 41#ifdef CONFIG_PCI_DIRECT 42 43 44#define CONFIG_CMD(dev, where) (0x80000000 | (dev->bus->number << 16) | (dev->devfn << 8) | (where & ~3)) 45 46#define PCI_REG(reg) (SH7751_PCIREG_BASE+reg) 47 48/* 49 * Functions for accessing PCI configuration space with type 1 accesses 50 */ 51static int pci_conf1_read_config_byte(struct pci_dev *dev, int where, u8 *value) 52{ 53 u32 word; 54 unsigned long flags; 55 56 /* PCIPDR may only be accessed as 32 bit words, 57 * so we must do byte alignment by hand 58 */ 59 save_and_cli(flags); 60 outl(CONFIG_CMD(dev,where), PCI_REG(SH7751_PCIPAR)); 61 word = inl(PCI_REG(SH7751_PCIPDR)); 62 restore_flags(flags); 63 switch (where & 0x3) { 64 case 3: 65 *value = (u8)(word >> 24); 66 break; 67 case 2: 68 *value = (u8)(word >> 16); 69 break; 70 case 1: 71 *value = (u8)(word >> 8); 72 break; 73 default: 74 *value = (u8)word; 75 break; 76 } 77 PCIDBG(4,"pci_conf1_read_config_byte@0x%08x=0x%x\n", 78 CONFIG_CMD(dev,where),*value); 79 return PCIBIOS_SUCCESSFUL; 80} 81 82static int pci_conf1_read_config_word(struct pci_dev *dev, int where, u16 *value) 83{ 84 u32 word; 85 unsigned long flags; 86 87 /* PCIPDR may only be accessed as 32 bit words, 88 * so we must do word alignment by hand 89 */ 90 save_and_cli(flags); 91 outl(CONFIG_CMD(dev,where), PCI_REG(SH7751_PCIPAR)); 92 word = inl(PCI_REG(SH7751_PCIPDR)); 93 restore_flags(flags); 94 switch (where & 0x3) { 95 case 3: 96 // This should never happen... 97 printk(KERN_ERR "PCI BIOS: read_config_word: Illegal u16 alignment"); 98 return PCIBIOS_BAD_REGISTER_NUMBER; 99 case 2: 100 *value = (u16)(word >> 16); 101 break; 102 case 1: 103 *value = (u16)(word >> 8); 104 break; 105 default: 106 *value = (u16)word; 107 break; 108 } 109 PCIDBG(4,"pci_conf1_read_config_word@0x%08x=0x%x\n", 110 CONFIG_CMD(dev,where),*value); 111 return PCIBIOS_SUCCESSFUL; 112} 113 114static int pci_conf1_read_config_dword(struct pci_dev *dev, int where, u32 *value) 115{ 116 unsigned long flags; 117 118 save_and_cli(flags); 119 outl(CONFIG_CMD(dev,where), PCI_REG(SH7751_PCIPAR)); 120 *value = inl(PCI_REG(SH7751_PCIPDR)); 121 restore_flags(flags); 122 PCIDBG(4,"pci_conf1_read_config_dword@0x%08x=0x%x\n", 123 CONFIG_CMD(dev,where),*value); 124 return PCIBIOS_SUCCESSFUL; 125} 126 127static int pci_conf1_write_config_byte(struct pci_dev *dev, int where, u8 value) 128{ 129 u32 word; 130 u32 shift = (where & 3) * 8; 131 u32 mask = ((1 << 8) - 1) << shift; // create the byte mask 132 unsigned long flags; 133 134 /* Since SH7751 only does 32bit access we'll have to do a 135 * read,mask,write operation 136 */ 137 save_and_cli(flags); 138 outl(CONFIG_CMD(dev,where), PCI_REG(SH7751_PCIPAR)); 139 word = inl(PCI_REG(SH7751_PCIPDR)) ; 140 word &= ~mask; 141 word |= value << shift; 142 143 outl(word, PCI_REG(SH7751_PCIPDR)); 144 restore_flags(flags); 145 PCIDBG(4,"pci_conf1_write_config_byte@0x%08x=0x%x\n", 146 CONFIG_CMD(dev,where),word); 147 return PCIBIOS_SUCCESSFUL; 148} 149 150static int pci_conf1_write_config_word(struct pci_dev *dev, int where, u16 value) 151{ 152 u32 word; 153 u32 shift = (where & 3) * 8; 154 u32 mask = ((1 << 16) - 1) << shift; // create the word mask 155 unsigned long flags; 156 157 /* Since SH7751 only does 32bit access we'll have to do a 158 * read,mask,write operation. We'll allow an odd byte offset, 159 * though it should be illegal. 160 */ 161 if (shift == 24) 162 return PCIBIOS_BAD_REGISTER_NUMBER; 163 save_and_cli(flags); 164 outl(CONFIG_CMD(dev,where), PCI_REG(SH7751_PCIPAR)); 165 word = inl(PCI_REG(SH7751_PCIPDR)) ; 166 word &= ~mask; 167 word |= value << shift; 168 169 outl(value, PCI_REG(SH7751_PCIPDR)); 170 restore_flags(flags); 171 PCIDBG(4,"pci_conf1_write_config_word@0x%08x=0x%x\n", 172 CONFIG_CMD(dev,where),word); 173 return PCIBIOS_SUCCESSFUL; 174} 175 176static int pci_conf1_write_config_dword(struct pci_dev *dev, int where, u32 value) 177{ 178 unsigned long flags; 179 180 save_and_cli(flags); 181 outl(CONFIG_CMD(dev,where), PCI_REG(SH7751_PCIPAR)); 182 outl(value, PCI_REG(SH7751_PCIPDR)); 183 restore_flags(flags); 184 PCIDBG(4,"pci_conf1_write_config_dword@0x%08x=0x%x\n", 185 CONFIG_CMD(dev,where),value); 186 return PCIBIOS_SUCCESSFUL; 187} 188 189#undef CONFIG_CMD 190 191static struct pci_ops pci_direct_conf1 = { 192 pci_conf1_read_config_byte, 193 pci_conf1_read_config_word, 194 pci_conf1_read_config_dword, 195 pci_conf1_write_config_byte, 196 pci_conf1_write_config_word, 197 pci_conf1_write_config_dword 198}; 199 200struct pci_ops * __init pci_check_direct(void) 201{ 202 unsigned int tmp, id; 203 204 /* check for SH7751 hardware */ 205 id = (SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID; 206 if(inl(SH7751_PCIREG_BASE+SH7751_PCICONF0) != id) { 207 PCIDBG(2,"PCI: This is not an SH7751\n"); 208 return NULL; 209 } 210 /* 211 * Check if configuration works. 212 */ 213 if (pci_probe & PCI_PROBE_CONF1) { 214 tmp = inl (PCI_REG(SH7751_PCIPAR)); 215 outl (0x80000000, PCI_REG(SH7751_PCIPAR)); 216 if (inl (PCI_REG(SH7751_PCIPAR)) == 0x80000000) { 217 outl (tmp, PCI_REG(SH7751_PCIPAR)); 218 printk(KERN_INFO "PCI: Using configuration type 1\n"); 219 request_region(PCI_REG(SH7751_PCIPAR), 8, "PCI conf1"); 220 return &pci_direct_conf1; 221 } 222 outl (tmp, PCI_REG(SH7751_PCIPAR)); 223 } 224 225 PCIDBG(2,"PCI: pci_check_direct failed\n"); 226 return NULL; 227} 228 229#endif 230 231/* 232 * BIOS32 and PCI BIOS handling. 233 * 234 * The BIOS version of the pci functions is not yet implemented but it is left 235 * in for completeness. Currently an error will be generated at compile time. 236 */ 237 238#ifdef CONFIG_PCI_BIOS 239 240#error PCI BIOS is not yet supported on SH7751 241 242#endif /* CONFIG_PCI_BIOS */ 243 244/***************************************************************************************/ 245 246/* 247 * Handle bus scanning and fixups .... 248 */ 249 250 251/* 252 * Discover remaining PCI buses in case there are peer host bridges. 253 * We use the number of last PCI bus provided by the PCI BIOS. 254 */ 255static void __init pcibios_fixup_peer_bridges(void) 256{ 257 int n; 258 struct pci_bus bus; 259 struct pci_dev dev; 260 u16 l; 261 262 if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff) 263 return; 264 PCIDBG(2,"PCI: Peer bridge fixup\n"); 265 for (n=0; n <= pcibios_last_bus; n++) { 266 if (pci_bus_exists(&pci_root_buses, n)) 267 continue; 268 bus.number = n; 269 bus.ops = pci_root_ops; 270 dev.bus = &bus; 271 for(dev.devfn=0; dev.devfn<256; dev.devfn += 8) 272 if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) && 273 l != 0x0000 && l != 0xffff) { 274 PCIDBG(3,"Found device at %02x:%02x [%04x]\n", n, dev.devfn, l); 275 printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n); 276 pci_scan_bus(n, pci_root_ops, NULL); 277 break; 278 } 279 } 280} 281 282 283static void __init pci_fixup_ide_bases(struct pci_dev *d) 284{ 285 int i; 286 287 /* 288 * PCI IDE controllers use non-standard I/O port decoding, respect it. 289 */ 290 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE) 291 return; 292 PCIDBG(3,"PCI: IDE base address fixup for %s\n", d->slot_name); 293 for(i=0; i<4; i++) { 294 struct resource *r = &d->resource[i]; 295 if ((r->start & ~0x80) == 0x374) { 296 r->start |= 2; 297 r->end = r->start; 298 } 299 } 300} 301 302 303/* Add future fixups here... */ 304struct pci_fixup pcibios_fixups[] = { 305 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases }, 306 { 0 } 307}; 308 309void __init pcibios_fixup_pbus_ranges(struct pci_bus *b, 310 struct pbus_set_ranges_data *range) 311{ 312 /* No fixups needed */ 313} 314 315/* 316 * Called after each bus is probed, but before its children 317 * are examined. 318 */ 319 320void __init pcibios_fixup_bus(struct pci_bus *b) 321{ 322 pci_read_bridge_bases(b); 323} 324 325/* 326 * Initialization. Try all known PCI access methods. Note that we support 327 * using both PCI BIOS and direct access: in such cases, we use I/O ports 328 * to access config space. 329 * 330 * Note that the platform specific initialization (BSC registers, and memory 331 * space mapping) will be called via the machine vectors (sh_mv.mv_pci_init()) if it 332 * exitst and via the platform defined function pcibios_init_platform(). 333 * See pci_bigsur.c for implementation; 334 * 335 * The BIOS version of the pci functions is not yet implemented but it is left 336 * in for completeness. Currently an error will be genereated at compile time. 337 */ 338 339void __init pcibios_init(void) 340{ 341 struct pci_ops *bios = NULL; 342 struct pci_ops *dir = NULL; 343 344 PCIDBG(1,"PCI: Starting intialization.\n"); 345#ifdef CONFIG_PCI_BIOS 346 if ((pci_probe & PCI_PROBE_BIOS) && ((bios = pci_find_bios()))) { 347 pci_probe |= PCI_BIOS_SORT; 348 pci_bios_present = 1; 349 } 350#endif 351#ifdef CONFIG_PCI_DIRECT 352 if (pci_probe & PCI_PROBE_CONF1 ) 353 dir = pci_check_direct(); 354#endif 355 if (dir) { 356 pci_root_ops = dir; 357 if(!pcibios_init_platform()) 358 PCIDBG(1,"PCI: Initialization failed\n"); 359 if (sh_mv.mv_init_pci != NULL) 360 sh_mv.mv_init_pci(); 361 } 362 else if (bios) 363 pci_root_ops = bios; 364 else { 365 PCIDBG(1,"PCI: No PCI bus detected\n"); 366 return; 367 } 368 369 PCIDBG(1,"PCI: Probing PCI hardware\n"); 370 pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL); 371 //pci_assign_unassigned_resources(); 372 pci_fixup_irqs(pcibios_swizzle, pcibios_lookup_irq); 373 pcibios_fixup_peer_bridges(); 374 pcibios_resource_survey(); 375 376#ifdef CONFIG_PCI_BIOS 377 if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT)) 378 pcibios_sort(); 379#endif 380} 381 382char * __init pcibios_setup(char *str) 383{ 384 if (!strcmp(str, "off")) { 385 pci_probe = 0; 386 return NULL; 387 } 388#ifdef CONFIG_PCI_BIOS 389 else if (!strcmp(str, "bios")) { 390 pci_probe = PCI_PROBE_BIOS; 391 return NULL; 392 } else if (!strcmp(str, "nobios")) { 393 pci_probe &= ~PCI_PROBE_BIOS; 394 return NULL; 395 } else if (!strcmp(str, "nosort")) { 396 pci_probe |= PCI_NO_SORT; 397 return NULL; 398 } else if (!strcmp(str, "biosirq")) { 399 pci_probe |= PCI_BIOS_IRQ_SCAN; 400 return NULL; 401 } 402#endif 403#ifdef CONFIG_PCI_DIRECT 404 else if (!strcmp(str, "conf1")) { 405 pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS; 406 return NULL; 407 } 408#endif 409 else if (!strcmp(str, "rom")) { 410 pci_probe |= PCI_ASSIGN_ROMS; 411 return NULL; 412 } else if (!strncmp(str, "lastbus=", 8)) { 413 pcibios_last_bus = simple_strtol(str+8, NULL, 0); 414 return NULL; 415 } 416 return str; 417} 418 419/* 420 * Allocate the bridge and device resources 421 */ 422 423static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) 424{ 425 struct list_head *ln; 426 struct pci_bus *bus; 427 struct pci_dev *dev; 428 int idx; 429 struct resource *r, *pr; 430 431 PCIDBG(2,"PCI: pcibios_allocate_bus_reasources called\n" ); 432 /* Depth-First Search on bus tree */ 433 for (ln=bus_list->next; ln != bus_list; ln=ln->next) { 434 bus = pci_bus_b(ln); 435 if ((dev = bus->self)) { 436 for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) { 437 r = &dev->resource[idx]; 438 if (!r->start) 439 continue; 440 pr = pci_find_parent_resource(dev, r); 441 if (!pr || request_resource(pr, r) < 0) 442 printk(KERN_ERR "PCI: Cannot allocate resource region %d of bridge %s\n", idx, dev->slot_name); 443 } 444 } 445 pcibios_allocate_bus_resources(&bus->children); 446 } 447} 448 449static void __init pcibios_allocate_resources(int pass) 450{ 451 struct pci_dev *dev; 452 int idx, disabled; 453 u16 command; 454 struct resource *r, *pr; 455 456 PCIDBG(2,"PCI: pcibios_allocate_resources pass %d called\n", pass); 457 pci_for_each_dev(dev) { 458 pci_read_config_word(dev, PCI_COMMAND, &command); 459 for(idx = 0; idx < 6; idx++) { 460 r = &dev->resource[idx]; 461 if (r->parent) /* Already allocated */ 462 continue; 463 if (!r->start) /* Address not assigned at all */ 464 continue; 465 if (r->flags & IORESOURCE_IO) 466 disabled = !(command & PCI_COMMAND_IO); 467 else 468 disabled = !(command & PCI_COMMAND_MEMORY); 469 if (pass == disabled) { 470 PCIDBG(3,"PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n", 471 r->start, r->end, r->flags, disabled, pass); 472 pr = pci_find_parent_resource(dev, r); 473 if (!pr || request_resource(pr, r) < 0) { 474 printk(KERN_ERR "PCI: Cannot allocate resource region %d of device %s\n", idx, dev->slot_name); 475 /* We'll assign a new address later */ 476 r->end -= r->start; 477 r->start = 0; 478 } 479 } 480 } 481 if (!pass) { 482 r = &dev->resource[PCI_ROM_RESOURCE]; 483 if (r->flags & PCI_ROM_ADDRESS_ENABLE) { 484 /* Turn the ROM off, leave the resource region, but keep it unregistered. */ 485 u32 reg; 486 PCIDBG(3,"PCI: Switching off ROM of %s\n", dev->slot_name); 487 r->flags &= ~PCI_ROM_ADDRESS_ENABLE; 488 pci_read_config_dword(dev, dev->rom_base_reg, ®); 489 pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE); 490 } 491 } 492 } 493} 494 495static void __init pcibios_assign_resources(void) 496{ 497 struct pci_dev *dev; 498 int idx; 499 struct resource *r; 500 501 PCIDBG(2,"PCI: pcibios_assign_resources called\n"); 502 pci_for_each_dev(dev) { 503 int class = dev->class >> 8; 504 505 /* Don't touch classless devices and host bridges */ 506 if (!class || class == PCI_CLASS_BRIDGE_HOST) 507 continue; 508 509 for(idx=0; idx<6; idx++) { 510 r = &dev->resource[idx]; 511 512 /* 513 * Don't touch IDE controllers and I/O ports of video cards! 514 */ 515 if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) || 516 (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO))) 517 continue; 518 519 /* 520 * We shall assign a new address to this resource, either because 521 * the BIOS forgot to do so or because we have decided the old 522 * address was unusable for some reason. 523 */ 524 if (!r->start && r->end) 525 pci_assign_resource(dev, idx); 526 } 527 528 if (pci_probe & PCI_ASSIGN_ROMS) { 529 r = &dev->resource[PCI_ROM_RESOURCE]; 530 r->end -= r->start; 531 r->start = 0; 532 if (r->end) 533 pci_assign_resource(dev, PCI_ROM_RESOURCE); 534 } 535 } 536} 537 538void __init pcibios_resource_survey(void) 539{ 540 PCIDBG(1,"PCI: Allocating resources\n"); 541 pcibios_allocate_bus_resources(&pci_root_buses); 542 pcibios_allocate_resources(0); 543 pcibios_allocate_resources(1); 544 pcibios_assign_resources(); 545} 546 547 548/***************************************************************************************/ 549/* 550 * IRQ functions 551 */ 552static u8 __init pcibios_swizzle(struct pci_dev *dev, u8 *pin) 553{ 554 /* no swizzling */ 555 return PCI_SLOT(dev->devfn); 556} 557 558static int pcibios_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin) 559{ 560 int irq = -1; 561 562 /* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */ 563 irq = pcibios_map_platform_irq(slot,pin); 564 if( irq < 0 ) { 565 PCIDBG(3,"PCI: Error mapping IRQ on device %s\n", dev->name); 566 return irq; 567 } 568 569 PCIDBG(2,"Setting IRQ for slot %s to %d\n", dev->slot_name, irq); 570 571 return irq; 572} 573