1/*
2 * BK Id: %F% %I% %G% %U% %#%
3 */
4/*
5 * SMP support for power macintosh.
6 *
7 * We support both the old "powersurge" SMP architecture
8 * and the current Core99 (G4 PowerMac) machines.
9 *
10 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
11 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
12 *
13 * Support for DayStar quad CPU cards
14 * Copyright (C) XLR8, Inc. 1994-2000
15 *
16 *  This program is free software; you can redistribute it and/or
17 *  modify it under the terms of the GNU General Public License
18 *  as published by the Free Software Foundation; either version
19 *  2 of the License, or (at your option) any later version.
20 */
21#include <linux/config.h>
22#include <linux/kernel.h>
23#include <linux/sched.h>
24#include <linux/smp.h>
25#include <linux/smp_lock.h>
26#include <linux/interrupt.h>
27#include <linux/kernel_stat.h>
28#include <linux/delay.h>
29#define __KERNEL_SYSCALLS__
30#include <linux/unistd.h>
31#include <linux/init.h>
32#include <linux/spinlock.h>
33#include <linux/stringify.h>
34
35#include <asm/ptrace.h>
36#include <asm/atomic.h>
37#include <asm/irq.h>
38#include <asm/page.h>
39#include <asm/pgtable.h>
40#include <asm/hardirq.h>
41#include <asm/softirq.h>
42#include <asm/sections.h>
43#include <asm/io.h>
44#include <asm/prom.h>
45#include <asm/smp.h>
46#include <asm/residual.h>
47#include <asm/machdep.h>
48#include <asm/pmac_feature.h>
49#include <asm/time.h>
50#include <asm/open_pic.h>
51#include <asm/processor.h>
52
53/*
54 * Powersurge (old powermac SMP) support.
55 */
56
57extern void __secondary_start_psurge(void);
58extern void __secondary_start_psurge2(void);	/* Temporary horrible hack */
59extern void __secondary_start_psurge3(void);	/* Temporary horrible hack */
60
61/* Addresses for powersurge registers */
62#define HAMMERHEAD_BASE		0xf8000000
63#define HHEAD_CONFIG		0x90
64#define HHEAD_SEC_INTR		0xc0
65
66/* register for interrupting the primary processor on the powersurge */
67/* N.B. this is actually the ethernet ROM! */
68#define PSURGE_PRI_INTR		0xf3019000
69
70/* register for storing the start address for the secondary processor */
71/* N.B. this is the PCI config space address register for the 1st bridge */
72#define PSURGE_START		0xf2800000
73
74/* Daystar/XLR8 4-CPU card */
75#define PSURGE_QUAD_REG_ADDR	0xf8800000
76
77#define PSURGE_QUAD_IRQ_SET	0
78#define PSURGE_QUAD_IRQ_CLR	1
79#define PSURGE_QUAD_IRQ_PRIMARY	2
80#define PSURGE_QUAD_CKSTOP_CTL	3
81#define PSURGE_QUAD_PRIMARY_ARB	4
82#define PSURGE_QUAD_BOARD_ID	6
83#define PSURGE_QUAD_WHICH_CPU	7
84#define PSURGE_QUAD_CKSTOP_RDBK	8
85#define PSURGE_QUAD_RESET_CTL	11
86
87#define PSURGE_QUAD_OUT(r, v)	(out_8(quad_base + ((r) << 4) + 4, (v)))
88#define PSURGE_QUAD_IN(r)	(in_8(quad_base + ((r) << 4) + 4) & 0x0f)
89#define PSURGE_QUAD_BIS(r, v)	(PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
90#define PSURGE_QUAD_BIC(r, v)	(PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
91
92/* virtual addresses for the above */
93static volatile u8 *hhead_base;
94static volatile u8 *quad_base;
95static volatile u32 *psurge_pri_intr;
96static volatile u8 *psurge_sec_intr;
97static volatile u32 *psurge_start;
98
99/* what sort of powersurge board we have */
100static int psurge_type;
101
102/* values for psurge_type */
103#define PSURGE_DUAL		0
104#define PSURGE_QUAD_OKEE	1
105#define PSURGE_QUAD_COTTON	2
106#define PSURGE_QUAD_ICEGRASS	3
107
108volatile static long int core99_l2_cache;
109volatile static long int core99_l3_cache;
110
111static void __init
112core99_init_caches(void)
113{
114	int cpu = smp_processor_id();
115
116	if (!(cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR))
117		return;
118
119	if (cpu == 0){
120		core99_l2_cache = _get_L2CR();
121		printk("CPU0: L2CR is %lx\n", core99_l2_cache);
122	} else {
123		printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
124		_set_L2CR(0);
125		_set_L2CR(core99_l2_cache);
126		printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
127	}
128
129	if (!(cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR))
130		return;
131
132	if (cpu == 0){
133		core99_l3_cache = _get_L3CR();
134		printk("CPU0: L3CR is %lx\n", core99_l3_cache);
135	} else {
136		printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
137		_set_L3CR(0);
138		_set_L3CR(core99_l3_cache);
139		printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
140	}
141}
142
143/* Some CPU registers have to be saved from the first CPU and
144 * applied to others. Note that we override what is setup by
145 * the cputable intentionally.
146 */
147
148#define	reg_hid0	0
149#define	reg_hid1	1
150#define	reg_msscr0	2
151#define	reg_msssr0	3
152#define	reg_ictrl	4
153#define	reg_ldstcr	5
154#define	reg_ldstdb	6
155#define	reg_count	7
156
157#define stringify __stringify
158
159static unsigned long cpu_regs[reg_count];
160
161static void __pmac
162cpu_setup_grab(void)
163{
164	unsigned int pvers = mfspr(SPRN_PVR)>>16;
165
166	/* Read cache setting of CPU 0 */
167	core99_init_caches();
168
169	/* 7400/7410/7450 */
170	if (pvers == 0x8000 || pvers == 0x000c || pvers == 0x800c) {
171		cpu_regs[reg_hid0] = mfspr(SPRN_HID0);
172		cpu_regs[reg_msscr0] = mfspr(SPRN_MSSCR0);
173		cpu_regs[reg_msssr0] = mfspr(SPRN_MSSSR0);
174	}
175	/* 7450 only */
176	if (pvers == 0x8000) {
177		cpu_regs[reg_hid1] = mfspr(SPRN_HID1);
178		cpu_regs[reg_ictrl] = mfspr(SPRN_ICTRL);
179		cpu_regs[reg_ldstcr] = mfspr(SPRN_LDSTCR);
180		cpu_regs[reg_ldstdb] = mfspr(SPRN_LDSTDB);
181	}
182	flush_dcache_range((unsigned long)cpu_regs, (unsigned long)&cpu_regs[reg_count]);
183}
184
185static void __pmac
186cpu_setup_apply(int cpu_nr)
187{
188	unsigned int pvers = mfspr(SPRN_PVR)>>16;
189
190	/* Apply cache setting from CPU 0 */
191	core99_init_caches();
192
193	/* 7400/7410/7450 */
194	if (pvers == 0x8000 || pvers == 0x000c || pvers == 0x800c) {
195		unsigned long tmp;
196		__asm__ __volatile__ (
197			"lwz	%0,4*"stringify(reg_hid0)"(%1)\n"
198			"sync\n"
199			"mtspr	"stringify(SPRN_HID0)", %0\n"
200			"isync;sync\n"
201			"lwz	%0, 4*"stringify(reg_msscr0)"(%1)\n"
202			"sync\n"
203			"mtspr	"stringify(SPRN_MSSCR0)", %0\n"
204			"isync;sync\n"
205//			"lwz	%0, "stringify(reg_msssr0)"(%1)\n"
206//			"sync\n"
207//			"mtspr	"stringify(SPRN_MSSSR0)", %0\n"
208//			"isync;sync\n"
209		: "=&r" (tmp) : "r" (cpu_regs));
210	}
211	/* 7410 only */
212	if (pvers == 0x800c) {
213		unsigned long tmp;
214		__asm__ __volatile__ (
215			"li	%0, 0\n"
216			"sync\n"
217			"mtspr	"stringify(SPRN_L2CR2)", %0\n"
218			"isync;sync\n"
219		: "=&r" (tmp));
220	}
221	/* 7450 only */
222	if (pvers == 0x8000) {
223		unsigned long tmp;
224		__asm__ __volatile__ (
225			"lwz	%0, 4*"stringify(reg_hid1)"(%1)\n"
226			"sync\n"
227			"mtspr	"stringify(SPRN_HID1)", %0\n"
228			"isync;sync\n"
229			"lwz	%0, 4*"stringify(reg_ictrl)"(%1)\n"
230			"sync\n"
231			"mtspr	"stringify(SPRN_ICTRL)", %0\n"
232			"isync;sync\n"
233			"lwz	%0, 4*"stringify(reg_ldstcr)"(%1)\n"
234			"sync\n"
235			"mtspr	"stringify(SPRN_LDSTCR)", %0\n"
236			"isync;sync\n"
237			"lwz	%0, 4*"stringify(reg_ldstdb)"(%1)\n"
238			"sync\n"
239			"mtspr	"stringify(SPRN_LDSTDB)", %0\n"
240			"isync;sync\n"
241		: "=&r" (tmp) : "r" (cpu_regs));
242	}
243}
244
245/*
246 * Set and clear IPIs for powersurge.
247 */
248static inline void psurge_set_ipi(int cpu)
249{
250	if (cpu == 0)
251		in_be32(psurge_pri_intr);
252	else if (psurge_type == PSURGE_DUAL)
253		out_8(psurge_sec_intr, 0);
254	else
255		PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
256}
257
258static inline void psurge_clr_ipi(int cpu)
259{
260	if (cpu > 0) {
261		if (psurge_type == PSURGE_DUAL)
262			out_8(psurge_sec_intr, ~0);
263		else
264			PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
265	}
266}
267
268/*
269 * On powersurge (old SMP powermac architecture) we don't have
270 * separate IPIs for separate messages like openpic does.  Instead
271 * we have a bitmap for each processor, where a 1 bit means that
272 * the corresponding message is pending for that processor.
273 * Ideally each cpu's entry would be in a different cache line.
274 *  -- paulus.
275 */
276static unsigned long psurge_smp_message[NR_CPUS];
277
278void __pmac
279psurge_smp_message_recv(struct pt_regs *regs)
280{
281	int cpu = smp_processor_id();
282	int msg;
283
284	/* clear interrupt */
285	psurge_clr_ipi(cpu);
286
287	if (smp_num_cpus < 2)
288		return;
289
290	/* make sure there is a message there */
291	for (msg = 0; msg < 4; msg++)
292		if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
293			smp_message_recv(msg, regs);
294}
295
296void __pmac
297psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
298{
299	psurge_smp_message_recv(regs);
300}
301
302static void __pmac
303smp_psurge_message_pass(int target, int msg, unsigned long data, int wait)
304{
305	int i;
306
307	if (smp_num_cpus < 2)
308		return;
309
310	for (i = 0; i < smp_num_cpus; i++) {
311		if (target == MSG_ALL
312		    || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
313		    || target == i) {
314			set_bit(msg, &psurge_smp_message[i]);
315			psurge_set_ipi(i);
316		}
317	}
318}
319
320/*
321 * Determine a quad card presence. We read the board ID register, we
322 * force the data bus to change to something else, and we read it again.
323 * It it's stable, then the register probably exist (ugh !)
324 */
325static int __init psurge_quad_probe(void)
326{
327	int type;
328	unsigned int i;
329
330	type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
331	if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
332	    || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
333		return PSURGE_DUAL;
334
335	/* looks OK, try a slightly more rigorous test */
336	/* bogus is not necessarily cacheline-aligned,
337	   though I don't suppose that really matters.  -- paulus */
338	for (i = 0; i < 100; i++) {
339		volatile u32 bogus[8];
340		bogus[(0+i)%8] = 0x00000000;
341		bogus[(1+i)%8] = 0x55555555;
342		bogus[(2+i)%8] = 0xFFFFFFFF;
343		bogus[(3+i)%8] = 0xAAAAAAAA;
344		bogus[(4+i)%8] = 0x33333333;
345		bogus[(5+i)%8] = 0xCCCCCCCC;
346		bogus[(6+i)%8] = 0xCCCCCCCC;
347		bogus[(7+i)%8] = 0x33333333;
348		wmb();
349		asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
350		mb();
351		if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
352			return PSURGE_DUAL;
353	}
354	return type;
355}
356
357static void __init psurge_quad_init(void)
358{
359	int procbits;
360
361	if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
362	procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
363	if (psurge_type == PSURGE_QUAD_ICEGRASS)
364		PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
365	else
366		PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
367	mdelay(33);
368	out_8(psurge_sec_intr, ~0);
369	PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
370	PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
371	if (psurge_type != PSURGE_QUAD_ICEGRASS)
372		PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
373	PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
374	mdelay(33);
375	PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
376	mdelay(33);
377	PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
378	mdelay(33);
379}
380
381static int __init smp_psurge_probe(void)
382{
383	int i, ncpus;
384
385	/* We don't do SMP on the PPC601 -- paulus */
386	if (PVR_VER(mfspr(PVR)) == 1)
387		return 1;
388
389	/*
390	 * The powersurge cpu board can be used in the generation
391	 * of powermacs that have a socket for an upgradeable cpu card,
392	 * including the 7500, 8500, 9500, 9600.
393	 * The device tree doesn't tell you if you have 2 cpus because
394	 * OF doesn't know anything about the 2nd processor.
395	 * Instead we look for magic bits in magic registers,
396	 * in the hammerhead memory controller in the case of the
397	 * dual-cpu powersurge board.  -- paulus.
398	 */
399	if (find_devices("hammerhead") == NULL)
400		return 1;
401
402	hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
403	quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
404	psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
405
406	psurge_type = psurge_quad_probe();
407	if (psurge_type != PSURGE_DUAL) {
408		psurge_quad_init();
409		/* All released cards using this HW design have 4 CPUs */
410		ncpus = 4;
411	} else {
412		iounmap((void *) quad_base);
413		if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
414			/* not a dual-cpu card */
415			iounmap((void *) hhead_base);
416			return 1;
417		}
418		ncpus = 2;
419	}
420
421	psurge_start = ioremap(PSURGE_START, 4);
422	psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
423
424	/* this is not actually strictly necessary -- paulus. */
425	for (i = 1; i < ncpus; ++i)
426		smp_hw_index[i] = i;
427
428	if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
429
430	return ncpus;
431}
432
433static void __init smp_psurge_kick_cpu(int nr)
434{
435	void (*start)(void) = __secondary_start_psurge;
436	unsigned long a;
437
438	/* may need to flush here if secondary bats aren't setup */
439	for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
440		asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
441	asm volatile("sync");
442
443	if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
444
445	/* setup entry point of secondary processor */
446	switch (nr) {
447	case 2:
448		start = __secondary_start_psurge2;
449		break;
450	case 3:
451		start = __secondary_start_psurge3;
452		break;
453	}
454
455	out_be32(psurge_start, __pa(start));
456	mb();
457
458	psurge_set_ipi(nr);
459	udelay(10);
460	psurge_clr_ipi(nr);
461
462	if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
463}
464
465/*
466 * With the dual-cpu powersurge board, the decrementers and timebases
467 * of both cpus are frozen after the secondary cpu is started up,
468 * until we give the secondary cpu another interrupt.  This routine
469 * uses this to get the timebases synchronized.
470 *  -- paulus.
471 */
472static void __init psurge_dual_sync_tb(int cpu_nr)
473{
474	static volatile int sec_tb_reset = 0;
475	int t;
476
477	set_dec(tb_ticks_per_jiffy);
478	set_tb(0, 0);
479	last_jiffy_stamp(cpu_nr) = 0;
480
481	if (cpu_nr > 0) {
482		mb();
483		sec_tb_reset = 1;
484		return;
485	}
486
487	/* wait for the secondary to have reset its TB before proceeding */
488	for (t = 10000000; t > 0 && !sec_tb_reset; --t)
489		;
490
491	/* now interrupt the secondary, starting both TBs */
492	psurge_set_ipi(1);
493
494	smp_tb_synchronized = 1;
495}
496
497static void __init
498smp_psurge_setup_cpu(int cpu_nr)
499{
500
501	if (cpu_nr == 0) {
502		if (smp_num_cpus < 2)
503			return;
504		/* reset the entry point so if we get another intr we won't
505		 * try to startup again */
506		out_be32(psurge_start, 0x100);
507		if (request_irq(30, psurge_primary_intr, 0, "primary IPI", 0))
508			printk(KERN_ERR "Couldn't get primary IPI interrupt");
509	}
510
511	if (psurge_type == PSURGE_DUAL)
512		psurge_dual_sync_tb(cpu_nr);
513}
514
515static int __init
516smp_core99_probe(void)
517{
518	struct device_node *cpus;
519	int i, ncpus = 1;
520	extern int powersave_nap;
521
522	if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
523	cpus = find_type_devices("cpu");
524	if (cpus)
525		while ((cpus = cpus->next) != NULL)
526			++ncpus;
527	printk("smp_core99_probe: found %d cpus\n", ncpus);
528	if (ncpus > 1) {
529		openpic_request_IPIs();
530		for (i = 1; i < ncpus; ++i)
531			smp_hw_index[i] = i;
532		powersave_nap = 0;
533		cpu_setup_grab();
534	}
535
536	return ncpus;
537}
538
539static void __init
540smp_core99_kick_cpu(int nr)
541{
542	unsigned long save_vector, new_vector;
543	unsigned long flags;
544
545	volatile unsigned long *vector
546		 = ((volatile unsigned long *)(KERNELBASE+0x100));
547	if (nr < 1 || nr > 3)
548		return;
549	if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
550
551	local_irq_save(flags);
552	local_irq_disable();
553
554	/* Save reset vector */
555	save_vector = *vector;
556
557	/* Setup fake reset vector that does
558	 *   b __secondary_start_psurge - KERNELBASE
559	 */
560	switch(nr) {
561		case 1:
562			new_vector = (unsigned long)__secondary_start_psurge;
563			break;
564		case 2:
565			new_vector = (unsigned long)__secondary_start_psurge2;
566			break;
567		case 3:
568			new_vector = (unsigned long)__secondary_start_psurge3;
569			break;
570	}
571	*vector = 0x48000002 + new_vector - KERNELBASE;
572
573	/* flush data cache and inval instruction cache */
574	flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
575
576	/* Put some life in our friend */
577	pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
578
579	mdelay(1);
580
581	/* Restore our exception vector */
582	*vector = save_vector;
583	flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
584
585	local_irq_restore(flags);
586	if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
587}
588
589static void __init
590smp_core99_setup_cpu(int cpu_nr)
591{
592	/* Setup some registers */
593	if (cpu_nr != 0)
594		cpu_setup_apply(cpu_nr);
595
596	/* Setup openpic */
597	do_openpic_setup_cpu();
598
599	/* Setup L2/L3 */
600	if (cpu_nr == 0)
601		if (ppc_md.progress) ppc_md.progress("core99_setup_cpu 0 done", 0x349);
602}
603
604/* PowerSurge-style Macs */
605struct smp_ops_t psurge_smp_ops __pmacdata = {
606	smp_psurge_message_pass,
607	smp_psurge_probe,
608	smp_psurge_kick_cpu,
609	smp_psurge_setup_cpu,
610};
611
612/* Core99 Macs (dual G4s) */
613struct smp_ops_t core99_smp_ops __pmacdata = {
614	smp_openpic_message_pass,
615	smp_core99_probe,
616	smp_core99_kick_cpu,
617	smp_core99_setup_cpu,
618};
619