1/* 2 * BK Id: %F% %I% %G% %U% %#% 3 */ 4/* 5 * Common pmac/prep/chrp pci routines. -- Cort 6 */ 7 8#include <linux/config.h> 9#include <linux/kernel.h> 10#include <linux/pci.h> 11#include <linux/delay.h> 12#include <linux/string.h> 13#include <linux/init.h> 14#include <linux/capability.h> 15#include <linux/sched.h> 16#include <linux/errno.h> 17#include <linux/bootmem.h> 18 19#include <asm/processor.h> 20#include <asm/io.h> 21#include <asm/prom.h> 22#include <asm/sections.h> 23#include <asm/pci-bridge.h> 24#include <asm/byteorder.h> 25#include <asm/irq.h> 26#include <asm/uaccess.h> 27 28#undef DEBUG 29 30#ifdef DEBUG 31#define DBG(x...) printk(x) 32#else 33#define DBG(x...) 34#endif 35 36unsigned long isa_io_base = 0; 37unsigned long isa_mem_base = 0; 38unsigned long pci_dram_offset = 0; 39 40void pcibios_make_OF_bus_map(void); 41 42static void pcibios_fixup_resources(struct pci_dev* dev); 43static void fixup_broken_pcnet32(struct pci_dev* dev); 44static void fixup_rev1_53c810(struct pci_dev* dev); 45static void fixup_cpc710_pci64(struct pci_dev* dev); 46#ifdef CONFIG_ALL_PPC 47static void pcibios_fixup_cardbus(struct pci_dev* dev); 48static u8* pci_to_OF_bus_map; 49#endif 50 51/* By default, we don't re-assign bus numbers. We do this only on 52 * some pmacs 53 */ 54int pci_assign_all_busses; 55 56struct pci_controller* hose_head; 57struct pci_controller** hose_tail = &hose_head; 58 59static int pci_bus_count; 60 61struct pci_fixup pcibios_fixups[] = { 62 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32 }, 63 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810 }, 64 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64}, 65 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources }, 66#ifdef CONFIG_ALL_PPC 67 /* We should add per-machine fixup support in xxx_setup.c or xxx_pci.c */ 68 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_TI, PCI_ANY_ID, pcibios_fixup_cardbus }, 69#endif /* CONFIG_ALL_PPC */ 70 { 0 } 71}; 72 73static void 74fixup_rev1_53c810(struct pci_dev* dev) 75{ 76 /* rev 1 ncr53c810 chips don't set the class at all which means 77 * they don't get their resources remapped. Fix that here. 78 */ 79 80 if ((dev->class == PCI_CLASS_NOT_DEFINED)) { 81 printk("NCR 53c810 rev 1 detected, setting PCI class.\n"); 82 dev->class = PCI_CLASS_STORAGE_SCSI; 83 } 84} 85 86static void 87fixup_broken_pcnet32(struct pci_dev* dev) 88{ 89 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { 90 dev->vendor = PCI_VENDOR_ID_AMD; 91 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); 92 pci_name_device(dev); 93 } 94} 95 96static void 97fixup_cpc710_pci64(struct pci_dev* dev) 98{ 99 /* Hide the PCI64 BARs from the kernel as their content doesn't 100 * fit well in the resource management 101 */ 102 dev->resource[0].start = dev->resource[0].end = 0; 103 dev->resource[0].flags = 0; 104 dev->resource[1].start = dev->resource[1].end = 0; 105 dev->resource[1].flags = 0; 106} 107 108void 109pcibios_update_resource(struct pci_dev *dev, struct resource *root, 110 struct resource *res, int resource) 111{ 112 u32 new, check; 113 int reg; 114 struct pci_controller* hose = dev->sysdata; 115 unsigned long io_offset; 116 117 new = res->start; 118 if (hose && res->flags & IORESOURCE_IO) { 119 io_offset = (unsigned long)hose->io_base_virt - isa_io_base; 120 new -= io_offset; 121 } 122 if (hose && res->flags & IORESOURCE_MEM) 123 new -= hose->pci_mem_offset; 124 new |= (res->flags & PCI_REGION_FLAG_MASK); 125 if (resource < 6) { 126 reg = PCI_BASE_ADDRESS_0 + 4*resource; 127 } else if (resource == PCI_ROM_RESOURCE) { 128 res->flags |= PCI_ROM_ADDRESS_ENABLE; 129 reg = dev->rom_base_reg; 130 } else { 131 /* Somebody might have asked allocation of a non-standard resource */ 132 return; 133 } 134 135 pci_write_config_dword(dev, reg, new); 136 pci_read_config_dword(dev, reg, &check); 137 if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) { 138 printk(KERN_ERR "PCI: Error while updating region " 139 "%s/%d (%08x != %08x)\n", dev->slot_name, resource, 140 new, check); 141 } 142} 143 144static void 145pcibios_fixup_resources(struct pci_dev *dev) 146{ 147 struct pci_controller* hose = (struct pci_controller *)dev->sysdata; 148 int i; 149 unsigned long offset; 150 151 if (!hose) { 152 printk(KERN_ERR "No hose for PCI dev %s!\n", dev->slot_name); 153 return; 154 } 155 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 156 struct resource *res = dev->resource + i; 157 if (!res->start || !res->flags) 158 continue; 159 if (res->end == 0xffffffff) { 160 DBG("PCI:%s Resource %d [%08lx-%08lx] is unassigned\n", 161 dev->slot_name, i, res->start, res->end); 162 res->end -= res->start; 163 res->start = 0; 164 continue; 165 } 166 offset = 0; 167 if (res->flags & IORESOURCE_MEM) { 168 offset = hose->pci_mem_offset; 169 } else if (res->flags & IORESOURCE_IO) { 170 offset = (unsigned long) hose->io_base_virt 171 - isa_io_base; 172 } 173 if (offset != 0) { 174 res->start += offset; 175 res->end += offset; 176#ifdef DEBUG 177 printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n", 178 i, res->flags, dev->slot_name, 179 res->start - offset, res->start); 180#endif 181 } 182 } 183 184 /* Call machine specific resource fixup */ 185 if (ppc_md.pcibios_fixup_resources) 186 ppc_md.pcibios_fixup_resources(dev); 187} 188 189#ifdef CONFIG_ALL_PPC 190static void 191pcibios_fixup_cardbus(struct pci_dev* dev) 192{ 193 if (_machine != _MACH_Pmac) 194 return; 195 /* 196 * Fix the interrupt routing on the various cardbus bridges 197 * used on powerbooks 198 */ 199 if (dev->vendor != PCI_VENDOR_ID_TI) 200 return; 201 if (dev->device == PCI_DEVICE_ID_TI_1130 || 202 dev->device == PCI_DEVICE_ID_TI_1131) { 203 u8 val; 204 /* Enable PCI interrupt */ 205 if (pci_read_config_byte(dev, 0x91, &val) == 0) 206 pci_write_config_byte(dev, 0x91, val | 0x30); 207 /* Disable ISA interrupt mode */ 208 if (pci_read_config_byte(dev, 0x92, &val) == 0) 209 pci_write_config_byte(dev, 0x92, val & ~0x06); 210 } 211 if (dev->device == PCI_DEVICE_ID_TI_1210 || 212 dev->device == PCI_DEVICE_ID_TI_1211 || 213 dev->device == PCI_DEVICE_ID_TI_1410) { 214 u8 val; 215 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA 216 signal out the MFUNC0 pin */ 217 if (pci_read_config_byte(dev, 0x8c, &val) == 0) 218 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); 219 /* Disable ISA interrupt mode */ 220 if (pci_read_config_byte(dev, 0x92, &val) == 0) 221 pci_write_config_byte(dev, 0x92, val & ~0x06); 222 } 223} 224#endif /* CONFIG_ALL_PPC */ 225 226/* 227 * We need to avoid collisions with `mirrored' VGA ports 228 * and other strange ISA hardware, so we always want the 229 * addresses to be allocated in the 0x000-0x0ff region 230 * modulo 0x400. 231 * 232 * Why? Because some silly external IO cards only decode 233 * the low 10 bits of the IO address. The 0x00-0xff region 234 * is reserved for motherboard devices that decode all 16 235 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 236 * but we want to try to avoid allocating at 0x2900-0x2bff 237 * which might have be mirrored at 0x0100-0x03ff.. 238 */ 239void 240pcibios_align_resource(void *data, struct resource *res, unsigned long size, 241 unsigned long align) 242{ 243 struct pci_dev *dev = data; 244 245 if (res->flags & IORESOURCE_IO) { 246 unsigned long start = res->start; 247 248 if (size > 0x100) { 249 printk(KERN_ERR "PCI: I/O Region %s/%d too large" 250 " (%ld bytes)\n", dev->slot_name, 251 dev->resource - res, size); 252 } 253 254 if (start & 0x300) { 255 start = (start + 0x3ff) & ~0x3ff; 256 res->start = start; 257 } 258 } 259} 260 261 262/* 263 * Handle resources of PCI devices. If the world were perfect, we could 264 * just allocate all the resource regions and do nothing more. It isn't. 265 * On the other hand, we cannot just re-allocate all devices, as it would 266 * require us to know lots of host bridge internals. So we attempt to 267 * keep as much of the original configuration as possible, but tweak it 268 * when it's found to be wrong. 269 * 270 * Known BIOS problems we have to work around: 271 * - I/O or memory regions not configured 272 * - regions configured, but not enabled in the command register 273 * - bogus I/O addresses above 64K used 274 * - expansion ROMs left enabled (this may sound harmless, but given 275 * the fact the PCI specs explicitly allow address decoders to be 276 * shared between expansion ROMs and other resource regions, it's 277 * at least dangerous) 278 * 279 * Our solution: 280 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 281 * This gives us fixed barriers on where we can allocate. 282 * (2) Allocate resources for all enabled devices. If there is 283 * a collision, just mark the resource as unallocated. Also 284 * disable expansion ROMs during this step. 285 * (3) Try to allocate resources for disabled devices. If the 286 * resources were assigned correctly, everything goes well, 287 * if they weren't, they won't disturb allocation of other 288 * resources. 289 * (4) Assign new addresses to resources which were either 290 * not configured at all or misconfigured. If explicitly 291 * requested by the user, configure expansion ROM address 292 * as well. 293 */ 294 295static void __init 296pcibios_allocate_bus_resources(struct list_head *bus_list) 297{ 298 struct list_head *ln; 299 struct pci_bus *bus; 300 int i; 301 struct resource *res, *pr; 302 303 /* Depth-First Search on bus tree */ 304 for (ln = bus_list->next; ln != bus_list; ln=ln->next) { 305 bus = pci_bus_b(ln); 306 for (i = 0; i < 4; ++i) { 307 if ((res = bus->resource[i]) == NULL || !res->flags) 308 continue; 309 if (bus->parent == NULL) 310 pr = (res->flags & IORESOURCE_IO)? 311 &ioport_resource: &iomem_resource; 312 else { 313 pr = pci_find_parent_resource(bus->self, res); 314 if (pr == res) { 315 /* this happens when the generic PCI 316 * code (wrongly) decides that this 317 * bridge is transparent -- paulus 318 */ 319 continue; 320 } 321 } 322 323 if (pr && request_resource(pr, res) == 0) 324 continue; 325 printk(KERN_ERR "PCI: Cannot allocate resource region " 326 "%d of PCI bridge %d\n", i, bus->number); 327 DBG("PCI: resource is %lx..%lx (%lx), parent %p\n", 328 res->start, res->end, res->flags, pr); 329 } 330 pcibios_allocate_bus_resources(&bus->children); 331 } 332} 333 334static inline void alloc_resource(struct pci_dev *dev, int idx) 335{ 336 struct resource *pr, *r = &dev->resource[idx]; 337 338 DBG("PCI:%s: Resource %d: %08lx-%08lx (f=%lx)\n", 339 dev->slot_name, idx, r->start, r->end, r->flags); 340 pr = pci_find_parent_resource(dev, r); 341 if (!pr || request_resource(pr, r) < 0) { 342 printk(KERN_ERR "PCI: Cannot allocate resource region %d" 343 " of device %s\n", idx, dev->slot_name); 344 if (pr) 345 DBG("PCI: parent is %p: %08lx-%08lx (f=%lx)\n", 346 pr, pr->start, pr->end, pr->flags); 347 /* We'll assign a new address later */ 348 r->end -= r->start; 349 r->start = 0; 350 } 351} 352 353static void __init 354pcibios_allocate_resources(int pass) 355{ 356 struct pci_dev *dev; 357 int idx, disabled; 358 u16 command; 359 struct resource *r; 360 361 pci_for_each_dev(dev) { 362 pci_read_config_word(dev, PCI_COMMAND, &command); 363 for (idx = 0; idx < 6; idx++) { 364 r = &dev->resource[idx]; 365 if (r->parent) /* Already allocated */ 366 continue; 367 if (!r->start) /* Not assigned at all */ 368 continue; 369 if (r->flags & IORESOURCE_IO) 370 disabled = !(command & PCI_COMMAND_IO); 371 else 372 disabled = !(command & PCI_COMMAND_MEMORY); 373 if (pass == disabled) 374 alloc_resource(dev, idx); 375 } 376 if (pass) 377 continue; 378 r = &dev->resource[PCI_ROM_RESOURCE]; 379 if (r->flags & PCI_ROM_ADDRESS_ENABLE) { 380 /* Turn the ROM off, leave the resource region, but keep it unregistered. */ 381 u32 reg; 382 DBG("PCI: Switching off ROM of %s\n", dev->slot_name); 383 r->flags &= ~PCI_ROM_ADDRESS_ENABLE; 384 pci_read_config_dword(dev, dev->rom_base_reg, ®); 385 pci_write_config_dword(dev, dev->rom_base_reg, 386 reg & ~PCI_ROM_ADDRESS_ENABLE); 387 } 388 } 389} 390 391static void __init 392pcibios_assign_resources(void) 393{ 394 struct pci_dev *dev; 395 int idx; 396 struct resource *r; 397 398 pci_for_each_dev(dev) { 399 int class = dev->class >> 8; 400 401 /* Don't touch classless devices and host bridges */ 402 if (!class || class == PCI_CLASS_BRIDGE_HOST) 403 continue; 404 405 for (idx = 0; idx < 6; idx++) { 406 r = &dev->resource[idx]; 407 408 /* 409 * We shall assign a new address to this resource, 410 * either because the BIOS (sic) forgot to do so 411 * or because we have decided the old address was 412 * unusable for some reason. 413 */ 414 if (!r->start && r->end && 415 (!ppc_md.pcibios_enable_device_hook || 416 !ppc_md.pcibios_enable_device_hook(dev, 1))) 417 pci_assign_resource(dev, idx); 418 } 419 420 } 421} 422 423 424int 425pcibios_enable_resources(struct pci_dev *dev) 426{ 427 u16 cmd, old_cmd; 428 int idx; 429 struct resource *r; 430 431 pci_read_config_word(dev, PCI_COMMAND, &cmd); 432 old_cmd = cmd; 433 for(idx=0; idx<6; idx++) { 434 r = &dev->resource[idx]; 435 if (!r->start && r->end) { 436 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name); 437 return -EINVAL; 438 } 439 if (r->flags & IORESOURCE_IO) 440 cmd |= PCI_COMMAND_IO; 441 if (r->flags & IORESOURCE_MEM) 442 cmd |= PCI_COMMAND_MEMORY; 443 } 444 if (dev->resource[PCI_ROM_RESOURCE].start) 445 cmd |= PCI_COMMAND_MEMORY; 446 if (cmd != old_cmd) { 447 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd); 448 pci_write_config_word(dev, PCI_COMMAND, cmd); 449 } 450 return 0; 451} 452 453static int next_controller_index; 454 455struct pci_controller * __init 456pcibios_alloc_controller(void) 457{ 458 struct pci_controller *hose; 459 460 hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose)); 461 memset(hose, 0, sizeof(struct pci_controller)); 462 463 *hose_tail = hose; 464 hose_tail = &hose->next; 465 466 hose->index = next_controller_index++; 467 468 return hose; 469} 470 471#ifdef CONFIG_ALL_PPC 472/* 473 * Functions below are used on OpenFirmware machines. 474 */ 475static void __openfirmware 476make_one_node_map(struct device_node* node, u8 pci_bus) 477{ 478 int *bus_range; 479 int len; 480 481 if (pci_bus >= pci_bus_count) 482 return; 483 bus_range = (int *) get_property(node, "bus-range", &len); 484 if (bus_range == NULL || len < 2 * sizeof(int)) { 485 printk(KERN_WARNING "Can't get bus-range for %s\n", 486 node->full_name); 487 return; 488 } 489 pci_to_OF_bus_map[pci_bus] = bus_range[0]; 490 491 for (node=node->child; node != 0;node = node->sibling) { 492 struct pci_dev* dev; 493 unsigned int *class_code, *reg; 494 495 class_code = (unsigned int *) get_property(node, "class-code", 0); 496 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && 497 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) 498 continue; 499 reg = (unsigned int *)get_property(node, "reg", 0); 500 if (!reg) 501 continue; 502 dev = pci_find_slot(pci_bus, ((reg[0] >> 8) & 0xff)); 503 if (!dev || !dev->subordinate) 504 continue; 505 make_one_node_map(node, dev->subordinate->number); 506 } 507} 508 509void __openfirmware 510pcibios_make_OF_bus_map(void) 511{ 512 int i; 513 struct pci_controller* hose; 514 u8* of_prop_map; 515 516 pci_to_OF_bus_map = (u8*)kmalloc(pci_bus_count, GFP_KERNEL); 517 if (!pci_to_OF_bus_map) { 518 printk(KERN_ERR "Can't allocate OF bus map !\n"); 519 return; 520 } 521 522 /* We fill the bus map with invalid values, that helps 523 * debugging. 524 */ 525 for (i=0; i<pci_bus_count; i++) 526 pci_to_OF_bus_map[i] = 0xff; 527 528 /* For each hose, we begin searching bridges */ 529 for(hose=hose_head; hose; hose=hose->next) { 530 struct device_node* node; 531 node = (struct device_node *)hose->arch_data; 532 if (!node) 533 continue; 534 make_one_node_map(node, hose->first_busno); 535 } 536 of_prop_map = get_property(find_path_device("/"), "pci-OF-bus-map", 0); 537 if (of_prop_map) 538 memcpy(of_prop_map, pci_to_OF_bus_map, pci_bus_count); 539#ifdef DEBUG 540 printk("PCI->OF bus map:\n"); 541 for (i=0; i<pci_bus_count; i++) { 542 if (pci_to_OF_bus_map[i] == 0xff) 543 continue; 544 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]); 545 } 546#endif 547} 548 549typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data); 550 551static struct device_node* __openfirmware 552scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data) 553{ 554 struct device_node* sub_node; 555 556 for (; node != 0;node = node->sibling) { 557 unsigned int *class_code; 558 559 if (filter(node, data)) 560 return node; 561 562 /* For PCI<->PCI bridges or CardBus bridges, we go down 563 * Note: some OFs create a parent node "multifunc-device" as 564 * a fake root for all functions of a multi-function device, 565 * we go down them as well. 566 */ 567 class_code = (unsigned int *) get_property(node, "class-code", 0); 568 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && 569 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) && 570 strcmp(node->name, "multifunc-device")) 571 continue; 572 sub_node = scan_OF_pci_childs(node->child, filter, data); 573 if (sub_node) 574 return sub_node; 575 } 576 return NULL; 577} 578 579static int 580scan_OF_pci_childs_iterator(struct device_node* node, void* data) 581{ 582 unsigned int *reg; 583 u8* fdata = (u8*)data; 584 585 reg = (unsigned int *) get_property(node, "reg", 0); 586 if (reg && ((reg[0] >> 8) & 0xff) == fdata[1] 587 && ((reg[0] >> 16) & 0xff) == fdata[0]) 588 return 1; 589 return 0; 590} 591 592static struct device_node* __openfirmware 593scan_OF_childs_for_device(struct device_node* node, u8 bus, u8 dev_fn) 594{ 595 u8 filter_data[2] = {bus, dev_fn}; 596 597 return scan_OF_pci_childs(node, scan_OF_pci_childs_iterator, filter_data); 598} 599 600/* 601 * Scans the OF tree for a device node matching a PCI device 602 */ 603struct device_node* 604pci_device_to_OF_node(struct pci_dev *dev) 605{ 606 struct pci_controller *hose; 607 struct device_node *node; 608 int bus; 609 610 if (!have_of) 611 return NULL; 612 613 /* Lookup the hose */ 614 bus = dev->bus->number; 615 hose = pci_bus_to_hose(bus); 616 if (!hose) 617 return NULL; 618 619 /* Check it has an OF node associated */ 620 node = (struct device_node *) hose->arch_data; 621 if (!node) 622 return NULL; 623 624 /* Fixup bus number according to what OF think it is. */ 625 if (pci_to_OF_bus_map) 626 bus = pci_to_OF_bus_map[bus]; 627 if (bus == 0xff) 628 return NULL; 629 630 /* Now, lookup childs of the hose */ 631 return scan_OF_childs_for_device(node->child, bus, dev->devfn); 632} 633 634/* This routine is meant to be used early during boot, when the 635 * PCI bus numbers have not yet been assigned, and you need to 636 * issue PCI config cycles to an OF device. 637 * It could also be used to "fix" RTAS config cycles if you want 638 * to set pci_assign_all_busses to 1 and still use RTAS for PCI 639 * config cycles. 640 */ 641struct pci_controller* 642pci_find_hose_for_OF_device(struct device_node* node) 643{ 644 if (!have_of) 645 return NULL; 646 while(node) { 647 struct pci_controller* hose; 648 for (hose=hose_head;hose;hose=hose->next) 649 if (hose->arch_data == node) 650 return hose; 651 node=node->parent; 652 } 653 return NULL; 654} 655 656static int __openfirmware 657find_OF_pci_device_filter(struct device_node* node, void* data) 658{ 659 return ((void *)node == data); 660} 661 662/* 663 * Returns the PCI device matching a given OF node 664 */ 665int 666pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn) 667{ 668 unsigned int *reg; 669 struct pci_controller* hose; 670 struct pci_dev* dev; 671 672 if (!have_of) 673 return -ENODEV; 674 /* Make sure it's really a PCI device */ 675 hose = pci_find_hose_for_OF_device(node); 676 if (!hose || !hose->arch_data) 677 return -ENODEV; 678 if (!scan_OF_pci_childs(((struct device_node*)hose->arch_data)->child, 679 find_OF_pci_device_filter, (void *)node)) 680 return -ENODEV; 681 reg = (unsigned int *) get_property(node, "reg", 0); 682 if (!reg) 683 return -ENODEV; 684 *bus = (reg[0] >> 16) & 0xff; 685 *devfn = ((reg[0] >> 8) & 0xff); 686 687 /* Ok, here we need some tweak. If we have already renumbered 688 * all busses, we can't rely on the OF bus number any more. 689 * the pci_to_OF_bus_map is not enough as several PCI busses 690 * may match the same OF bus number. 691 */ 692 if (!pci_to_OF_bus_map) 693 return 0; 694 pci_for_each_dev(dev) { 695 if (pci_to_OF_bus_map[dev->bus->number] != *bus) 696 continue; 697 if (dev->devfn != *devfn) 698 continue; 699 *bus = dev->bus->number; 700 return 0; 701 } 702 return -ENODEV; 703} 704 705void __init 706pci_process_bridge_OF_ranges(struct pci_controller *hose, 707 struct device_node *dev, int primary) 708{ 709 unsigned int *ranges, *prev; 710 int rlen = 0; 711 int memno = 0; 712 struct resource *res; 713 int np, na = prom_n_addr_cells(dev); 714 np = na + 5; 715 716 /* First we try to merge ranges to fix a problem with some pmacs 717 * that can have more than 3 ranges, fortunately using contiguous 718 * addresses -- BenH 719 */ 720 ranges = (unsigned int *) get_property(dev, "ranges", &rlen); 721 prev = NULL; 722 while ((rlen -= np * sizeof(unsigned int)) >= 0) { 723 if (prev) { 724 if (prev[0] == ranges[0] && prev[1] == ranges[1] && 725 (prev[2] + prev[na+4]) == ranges[2] && 726 (prev[na+2] + prev[na+4]) == ranges[na+2]) { 727 prev[na+4] += ranges[na+4]; 728 ranges[0] = 0; 729 ranges += np; 730 continue; 731 } 732 } 733 prev = ranges; 734 ranges += np; 735 } 736 737 /* 738 * The ranges property is laid out as an array of elements, 739 * each of which comprises: 740 * cells 0 - 2: a PCI address 741 * cells 3 or 3+4: a CPU physical address 742 * (size depending on dev->n_addr_cells) 743 * cells 4+5 or 5+6: the size of the range 744 */ 745 rlen = 0; 746 hose->io_base_phys = 0; 747 ranges = (unsigned int *) get_property(dev, "ranges", &rlen); 748 while ((rlen -= np * sizeof(unsigned int)) >= 0) { 749 res = NULL; 750 switch (ranges[0] >> 24) { 751 case 1: /* I/O space */ 752 if (ranges[2] != 0) 753 break; 754 hose->io_base_phys = ranges[na+2]; 755 hose->io_base_virt = ioremap(ranges[na+2], ranges[na+4]); 756 if (primary) 757 isa_io_base = (unsigned long) hose->io_base_virt; 758 res = &hose->io_resource; 759 res->flags = IORESOURCE_IO; 760 res->start = ranges[2]; 761 break; 762 case 2: /* memory space */ 763 memno = 0; 764 if (ranges[1] == 0 && ranges[2] == 0 765 && ranges[na+4] <= (16 << 20)) { 766 /* 1st 16MB, i.e. ISA memory area */ 767 if (primary) 768 isa_mem_base = ranges[na+2]; 769 memno = 1; 770 } 771 while (memno < 3 && hose->mem_resources[memno].flags) 772 ++memno; 773 if (memno == 0) 774 hose->pci_mem_offset = ranges[na+2] - ranges[2]; 775 if (memno < 3) { 776 res = &hose->mem_resources[memno]; 777 res->flags = IORESOURCE_MEM; 778 res->start = ranges[na+2]; 779 } 780 break; 781 } 782 if (res != NULL) { 783 res->name = dev->full_name; 784 res->end = res->start + ranges[na+4] - 1; 785 res->parent = NULL; 786 res->sibling = NULL; 787 res->child = NULL; 788 } 789 ranges += np; 790 } 791} 792 793/* We create the "pci-OF-bus-map" property now so it appears in the 794 * /proc device tree 795 */ 796void __init 797pci_create_OF_bus_map(void) 798{ 799 struct property* of_prop; 800 801 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256); 802 if (of_prop && find_path_device("/")) { 803 memset(of_prop, -1, sizeof(struct property) + 256); 804 of_prop->name = "pci-OF-bus-map"; 805 of_prop->length = 256; 806 of_prop->value = (unsigned char *)&of_prop[1]; 807 prom_add_property(find_path_device("/"), of_prop); 808 } 809} 810#endif /* CONFIG_ALL_PPC */ 811 812 813/* Initialize bridges with base/limit values we have collected */ 814static void __init 815do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga) 816{ 817 struct pci_dev *bridge = bus->self; 818 struct pci_controller* hose = (struct pci_controller *)bridge->sysdata; 819 u32 l; 820 u16 w; 821 struct resource res; 822 823 res = *(bus->resource[0]); 824 825 DBG("Remapping Bus %d, bridge: %s\n", bus->number, bridge->name); 826 res.start -= ((unsigned long) hose->io_base_virt - isa_io_base); 827 res.end -= ((unsigned long) hose->io_base_virt - isa_io_base); 828 DBG(" IO window: %08lx-%08lx\n", res.start, res.end); 829 830 /* Set up the top and bottom of the PCI I/O segment for this bus. */ 831 pci_read_config_dword(bridge, PCI_IO_BASE, &l); 832 l &= 0xffff000f; 833 l |= (res.start >> 8) & 0x00f0; 834 l |= res.end & 0xf000; 835 pci_write_config_dword(bridge, PCI_IO_BASE, l); 836 837 if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 838 l = (res.start >> 16) | (res.end & 0xffff0000); 839 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l); 840 } 841 842 pci_read_config_word(bridge, PCI_COMMAND, &w); 843 w |= PCI_COMMAND_IO; 844 pci_write_config_word(bridge, PCI_COMMAND, w); 845 846} 847 848/* This function is pretty basic and actually quite broken for the 849 * general case, it's enough for us right now though. It's supposed 850 * to tell us if we need to open an IO range at all or not and what 851 * size. 852 */ 853static int __init 854check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga) 855{ 856 struct list_head *ln; 857 int i; 858 int rc = 0; 859 860#define push_end(res, size) do { unsigned long __sz = (size) ; \ 861 res->end = ((res->end + __sz) / (__sz + 1)) * (__sz + 1) + __sz; \ 862 } while (0) 863 864 for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) { 865 struct pci_dev *dev = pci_dev_b(ln); 866 u16 class = dev->class >> 8; 867 868 if (class == PCI_CLASS_DISPLAY_VGA || class == PCI_CLASS_NOT_DEFINED_VGA) 869 *found_vga = 1; 870 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate) 871 rc |= check_for_io_childs(dev->subordinate, res, found_vga); 872 if (class == PCI_CLASS_BRIDGE_CARDBUS) 873 push_end(res, 0xfff); 874 875 for (i=0; i<PCI_NUM_RESOURCES; i++) { 876 struct resource *r; 877 unsigned long r_size; 878 879 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI && i >= PCI_BRIDGE_RESOURCES) 880 continue; 881 r = &dev->resource[i]; 882 r_size = r->end - r->start; 883 if (r_size < 0xfff) 884 r_size = 0xfff; 885 if (r->flags & IORESOURCE_IO && (r_size) != 0) { 886 rc = 1; 887 push_end(res, r_size); 888 } 889 } 890 } 891 892 return rc; 893} 894 895/* Here we scan all P2P bridges of a given level that have a closed 896 * IO window. Note that the test for the presence of a VGA card should 897 * be improved to take into account already configured P2P bridges, 898 * currently, we don't see them and might end up configuring 2 bridges 899 * with VGA pass through enabled 900 */ 901static void __init 902do_fixup_p2p_level(struct pci_bus *bus) 903{ 904 struct list_head *ln; 905 int i; 906 int has_vga = 0; 907 908 for (ln=bus->children.next; ln != &bus->children; ln=ln->next) { 909 struct pci_bus *b = pci_bus_b(ln); 910 struct pci_dev *d = b->self; 911 struct pci_controller* hose = (struct pci_controller *)d->sysdata; 912 struct resource *res = b->resource[0]; 913 unsigned long max; 914 int found_vga = 0; 915 916 res->end = 0; 917 res->start = 0x1000; 918 919 if (!list_empty(&b->devices) && res && res->flags == 0 && res != bus->resource[0] && 920 (d->class >> 8) == PCI_CLASS_BRIDGE_PCI && 921 check_for_io_childs(b, res, &found_vga)) { 922 u8 io_base_lo; 923 924 printk(KERN_INFO "Fixing up IO bus %s\n", b->name); 925 926 if (found_vga) { 927 if (has_vga) { 928 printk(KERN_WARNING "Skipping VGA, already active on bus segment\n"); 929 found_vga = 0; 930 } else 931 has_vga = 1; 932 } 933 pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo); 934 935 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) 936 max = ((unsigned long) hose->io_base_virt - isa_io_base) + 0xffffffff; 937 else 938 max = ((unsigned long) hose->io_base_virt - isa_io_base) + 0xffff; 939 940 res->flags = IORESOURCE_IO; 941 res->name = b->name; 942 943 /* Find a resource in the parent where we can allocate */ 944 for (i = 0 ; i < 4; i++) { 945 struct resource *r = bus->resource[i]; 946 if (!r) 947 continue; 948 if ((r->flags & IORESOURCE_IO) == 0) 949 continue; 950 DBG("Trying to allocate from %08lx, size %08lx from parent res %d: %08lx -> %08lx\n", 951 res->start, res->end, i, r->start, r->end); 952 953 if (allocate_resource(r, res, res->end + 1, res->start, max, res->end + 1, NULL, NULL) < 0) { 954 DBG("Failed !\n"); 955 continue; 956 } 957 do_update_p2p_io_resource(b, found_vga); 958 break; 959 } 960 } 961 do_fixup_p2p_level(b); 962 } 963} 964 965static void 966pcibios_fixup_p2p_bridges(void) 967{ 968 struct list_head *ln; 969 970 for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next) { 971 struct pci_bus *b = pci_bus_b(ln); 972 do_fixup_p2p_level(b); 973 } 974} 975 976void __init 977pcibios_init(void) 978{ 979 struct pci_controller *hose; 980 struct pci_bus *bus; 981 int next_busno, bus_offset; 982 983 printk(KERN_INFO "PCI: Probing PCI hardware\n"); 984 985 /* There is a problem with bus renumbering currently. If 986 * you have 2 sibling pci<->pci bridges, and during PCI 987 * probe, the first one gets assigned a new number equal 988 * to the old number of the second one, you'll end up 989 * probing that branch with 2 bridges racing on the bus 990 * numbers. 991 * I work around this on pmac by adding a large offset 992 * between host bridges, though a better long term solution 993 * will have to be found in the generic code. --BenH 994 */ 995#ifdef CONFIG_ALL_PPC 996 if (machine_is_compatible("MacRISC")) 997 bus_offset = 0x10; 998 else 999#endif 1000 bus_offset = 1; 1001 /* Scan all of the recorded PCI controllers. */ 1002 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { 1003 if (pci_assign_all_busses) 1004 hose->first_busno = next_busno; 1005 hose->last_busno = 0xff; 1006 bus = pci_scan_bus(hose->first_busno, hose->ops, hose); 1007 hose->last_busno = bus->subordinate; 1008 if (pci_assign_all_busses || next_busno <= hose->last_busno) 1009 next_busno = hose->last_busno + bus_offset; 1010 } 1011 pci_bus_count = next_busno; 1012 1013 /* OpenFirmware based machines need a map of OF bus 1014 * numbers vs. kernel bus numbers since we may have to 1015 * remap them. 1016 */ 1017 if (pci_assign_all_busses && have_of) 1018 pcibios_make_OF_bus_map(); 1019 1020 /* Do machine dependent PCI interrupt routing */ 1021 if (ppc_md.pci_swizzle && ppc_md.pci_map_irq) 1022 pci_fixup_irqs(ppc_md.pci_swizzle, ppc_md.pci_map_irq); 1023 1024 /* Call machine dependant fixup */ 1025 if (ppc_md.pcibios_fixup) 1026 ppc_md.pcibios_fixup(); 1027 1028 /* Allocate and assign resources */ 1029 pcibios_allocate_bus_resources(&pci_root_buses); 1030 pcibios_allocate_resources(0); 1031 pcibios_allocate_resources(1); 1032 pcibios_fixup_p2p_bridges(); 1033 pcibios_assign_resources(); 1034 1035 /* Call machine dependent post-init code */ 1036 if (ppc_md.pcibios_after_init) 1037 ppc_md.pcibios_after_init(); 1038} 1039 1040unsigned char __init 1041common_swizzle(struct pci_dev *dev, unsigned char *pinp) 1042{ 1043 struct pci_controller *hose = dev->sysdata; 1044 1045 if (dev->bus->number != hose->first_busno) { 1046 u8 pin = *pinp; 1047 do { 1048 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); 1049 /* Move up the chain of bridges. */ 1050 dev = dev->bus->self; 1051 } while (dev->bus->self); 1052 *pinp = pin; 1053 1054 /* The slot is the idsel of the last bridge. */ 1055 } 1056 return PCI_SLOT(dev->devfn); 1057} 1058 1059void __init 1060pcibios_fixup_pbus_ranges(struct pci_bus * bus, struct pbus_set_ranges_data * ranges) 1061{ 1062 ranges->io_start -= bus->resource[0]->start; 1063 ranges->io_end -= bus->resource[0]->start; 1064 ranges->mem_start -= bus->resource[1]->start; 1065 ranges->mem_end -= bus->resource[1]->start; 1066} 1067 1068unsigned long resource_fixup(struct pci_dev * dev, struct resource * res, 1069 unsigned long start, unsigned long size) 1070{ 1071 return start; 1072} 1073 1074void __init pcibios_fixup_bus(struct pci_bus *bus) 1075{ 1076 struct pci_controller *hose = (struct pci_controller *) bus->sysdata; 1077 unsigned long io_offset; 1078 struct resource *res; 1079 int i; 1080 1081 io_offset = (unsigned long)hose->io_base_virt - isa_io_base; 1082 if (bus->parent == NULL) { 1083 /* This is a host bridge - fill in its resources */ 1084 hose->bus = bus; 1085 1086 bus->resource[0] = res = &hose->io_resource; 1087 if (!res->flags) { 1088 if (io_offset) 1089 printk(KERN_ERR "I/O resource not set for host" 1090 " bridge %d\n", hose->index); 1091 res->start = 0; 1092 res->end = IO_SPACE_LIMIT; 1093 res->flags = IORESOURCE_IO; 1094 } 1095 res->start += io_offset; 1096 res->end += io_offset; 1097 1098 for (i = 0; i < 3; ++i) { 1099 res = &hose->mem_resources[i]; 1100 if (!res->flags) { 1101 if (i > 0) 1102 continue; 1103 printk(KERN_ERR "Memory resource not set for " 1104 "host bridge %d\n", hose->index); 1105 res->start = hose->pci_mem_offset; 1106 res->end = ~0U; 1107 res->flags = IORESOURCE_MEM; 1108 } 1109 bus->resource[i+1] = res; 1110 } 1111 } else { 1112 /* This is a subordinate bridge */ 1113 pci_read_bridge_bases(bus); 1114 1115 for (i = 0; i < 4; ++i) { 1116 if ((res = bus->resource[i]) == NULL) 1117 continue; 1118 if (!res->flags) 1119 continue; 1120 if (io_offset && (res->flags & IORESOURCE_IO)) { 1121 res->start += io_offset; 1122 res->end += io_offset; 1123 } else if (hose->pci_mem_offset 1124 && (res->flags & IORESOURCE_MEM)) { 1125 res->start += hose->pci_mem_offset; 1126 res->end += hose->pci_mem_offset; 1127 } 1128 } 1129 } 1130 1131 if (ppc_md.pcibios_fixup_bus) 1132 ppc_md.pcibios_fixup_bus(bus); 1133} 1134 1135char __init *pcibios_setup(char *str) 1136{ 1137 return str; 1138} 1139 1140/* the next one is stolen from the alpha port... */ 1141void __init 1142pcibios_update_irq(struct pci_dev *dev, int irq) 1143{ 1144 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 1145} 1146 1147int pcibios_enable_device(struct pci_dev *dev, int mask) 1148{ 1149 u16 cmd, old_cmd; 1150 int idx; 1151 struct resource *r; 1152 1153 if (ppc_md.pcibios_enable_device_hook) 1154 if (ppc_md.pcibios_enable_device_hook(dev, 0)) 1155 return -EINVAL; 1156 1157 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1158 old_cmd = cmd; 1159 for (idx=0; idx<6; idx++) { 1160 if(!(mask & (1<<idx))) 1161 continue; 1162 1163 r = &dev->resource[idx]; 1164 if (!r->start && r->end) { 1165 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name); 1166 return -EINVAL; 1167 } 1168 if (r->flags & IORESOURCE_IO) 1169 cmd |= PCI_COMMAND_IO; 1170 if (r->flags & IORESOURCE_MEM) 1171 cmd |= PCI_COMMAND_MEMORY; 1172 } 1173 if (cmd != old_cmd) { 1174 printk("PCI: Enabling device %s (%04x -> %04x)\n", 1175 dev->slot_name, old_cmd, cmd); 1176 pci_write_config_word(dev, PCI_COMMAND, cmd); 1177 } 1178 return 0; 1179} 1180 1181struct pci_controller* 1182pci_bus_to_hose(int bus) 1183{ 1184 struct pci_controller* hose = hose_head; 1185 1186 for (; hose; hose = hose->next) 1187 if (bus >= hose->first_busno && bus <= hose->last_busno) 1188 return hose; 1189 return NULL; 1190} 1191 1192void* 1193pci_bus_io_base(unsigned int bus) 1194{ 1195 struct pci_controller *hose; 1196 1197 hose = pci_bus_to_hose(bus); 1198 if (!hose) 1199 return NULL; 1200 return hose->io_base_virt; 1201} 1202 1203unsigned long 1204pci_bus_io_base_phys(unsigned int bus) 1205{ 1206 struct pci_controller *hose; 1207 1208 hose = pci_bus_to_hose(bus); 1209 if (!hose) 1210 return 0; 1211 return hose->io_base_phys; 1212} 1213 1214unsigned long 1215pci_bus_mem_base_phys(unsigned int bus) 1216{ 1217 struct pci_controller *hose; 1218 1219 hose = pci_bus_to_hose(bus); 1220 if (!hose) 1221 return 0; 1222 return hose->pci_mem_offset; 1223} 1224 1225unsigned long 1226pci_resource_to_bus(struct pci_dev *pdev, struct resource *res) 1227{ 1228 /* Hack alert again ! See comments in chrp_pci.c 1229 */ 1230 struct pci_controller* hose = 1231 (struct pci_controller *)pdev->sysdata; 1232 if (hose && res->flags & IORESOURCE_MEM) 1233 return res->start - hose->pci_mem_offset; 1234 /* We may want to do something with IOs here... */ 1235 return res->start; 1236} 1237 1238/* 1239 * Return the index of the PCI controller for device pdev. 1240 */ 1241int pci_controller_num(struct pci_dev *dev) 1242{ 1243 struct pci_controller *hose = (struct pci_controller *) dev->sysdata; 1244 1245 return hose->index; 1246} 1247 1248/* 1249 * Platform support for /proc/bus/pci/X/Y mmap()s, 1250 * modelled on the sparc64 implementation by Dave Miller. 1251 * -- paulus. 1252 */ 1253 1254static __inline__ int 1255__pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma, 1256 enum pci_mmap_state mmap_state) 1257{ 1258 struct pci_controller *hose = (struct pci_controller *) dev->sysdata; 1259 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 1260 unsigned long io_offset = 0; 1261 int i, res_bit; 1262 1263 if (hose == 0) 1264 return -EINVAL; /* should never happen */ 1265 1266 /* If memory, add on the PCI bridge address offset */ 1267 if (mmap_state == pci_mmap_mem) { 1268 offset += hose->pci_mem_offset; 1269 res_bit = IORESOURCE_MEM; 1270 } else { 1271 io_offset = (unsigned long)hose->io_base_virt - isa_io_base; 1272 offset += io_offset; 1273 res_bit = IORESOURCE_IO; 1274 } 1275 1276 /* 1277 * Check that the offset requested corresponds to one of the 1278 * resources of the device. 1279 */ 1280 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 1281 struct resource *rp = &dev->resource[i]; 1282 int flags = rp->flags; 1283 1284 /* treat ROM as memory (should be already) */ 1285 if (i == PCI_ROM_RESOURCE) 1286 flags |= IORESOURCE_MEM; 1287 1288 /* Active and same type? */ 1289 if ((flags & res_bit) == 0) 1290 continue; 1291 1292 /* In the range of this resource? */ 1293 if (offset < (rp->start & PAGE_MASK) || offset > rp->end) 1294 continue; 1295 1296 /* found it! construct the final physical address */ 1297 if (mmap_state == pci_mmap_io) 1298 offset += hose->io_base_phys - io_offset; 1299 1300 vma->vm_pgoff = offset >> PAGE_SHIFT; 1301 return 0; 1302 } 1303 1304 return -EINVAL; 1305} 1306 1307/* 1308 * Set vm_flags of VMA, as appropriate for this architecture, for a pci device 1309 * mapping. 1310 */ 1311static __inline__ void 1312__pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, 1313 enum pci_mmap_state mmap_state) 1314{ 1315 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO; 1316} 1317 1318/* 1319 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 1320 * device mapping. 1321 */ 1322static __inline__ void 1323__pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, 1324 enum pci_mmap_state mmap_state, int write_combine) 1325{ 1326 int prot = pgprot_val(vma->vm_page_prot); 1327 1328 prot |= _PAGE_NO_CACHE; 1329 if (!write_combine) 1330 prot |= _PAGE_GUARDED; 1331 vma->vm_page_prot = __pgprot(prot); 1332} 1333 1334/* 1335 * Perform the actual remap of the pages for a PCI device mapping, as 1336 * appropriate for this architecture. The region in the process to map 1337 * is described by vm_start and vm_end members of VMA, the base physical 1338 * address is found in vm_pgoff. 1339 * The pci device structure is provided so that architectures may make mapping 1340 * decisions on a per-device or per-bus basis. 1341 * 1342 * Returns a negative error code on failure, zero on success. 1343 */ 1344int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 1345 enum pci_mmap_state mmap_state, 1346 int write_combine) 1347{ 1348 int ret; 1349 1350 ret = __pci_mmap_make_offset(dev, vma, mmap_state); 1351 if (ret < 0) 1352 return ret; 1353 1354 __pci_mmap_set_flags(dev, vma, mmap_state); 1355 __pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine); 1356 1357 ret = remap_page_range(vma->vm_start, vma->vm_pgoff << PAGE_SHIFT, 1358 vma->vm_end - vma->vm_start, vma->vm_page_prot); 1359 1360 return ret; 1361} 1362 1363/* Obsolete functions. Should be removed once the symbios driver 1364 * is fixed 1365 */ 1366unsigned long 1367phys_to_bus(unsigned long pa) 1368{ 1369 struct pci_controller *hose; 1370 int i; 1371 1372 for (hose = hose_head; hose; hose = hose->next) { 1373 for (i = 0; i < 3; ++i) { 1374 if (pa >= hose->mem_resources[i].start 1375 && pa <= hose->mem_resources[i].end) { 1376 if (i == 0) 1377 pa -= hose->pci_mem_offset; 1378 return pa; 1379 } 1380 } 1381 } 1382 /* hmmm, didn't find it */ 1383 return 0; 1384} 1385 1386unsigned long 1387pci_phys_to_bus(unsigned long pa, int busnr) 1388{ 1389 struct pci_controller* hose = pci_bus_to_hose(busnr); 1390 if (!hose) 1391 return pa; 1392 return pa - hose->pci_mem_offset; 1393} 1394 1395unsigned long 1396pci_bus_to_phys(unsigned int ba, int busnr) 1397{ 1398 struct pci_controller* hose = pci_bus_to_hose(busnr); 1399 if (!hose) 1400 return ba; 1401 return ba + hose->pci_mem_offset; 1402} 1403 1404/* Provide information on locations of various I/O regions in physical 1405 * memory. Do this on a per-card basis so that we choose the right 1406 * root bridge. 1407 * Note that the returned IO or memory base is a physical address 1408 */ 1409 1410long 1411sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) 1412{ 1413 struct pci_controller* hose = pci_bus_to_hose(bus); 1414 long result = -EOPNOTSUPP; 1415 1416 if (!hose) 1417 return -ENODEV; 1418 1419 switch (which) { 1420 case IOBASE_BRIDGE_NUMBER: 1421 return (long)hose->first_busno; 1422 case IOBASE_MEMORY: 1423 return (long)hose->pci_mem_offset; 1424 case IOBASE_IO: 1425 return (long)hose->io_base_phys; 1426 case IOBASE_ISA_IO: 1427 return (long)isa_io_base; 1428 case IOBASE_ISA_MEM: 1429 return (long)isa_mem_base; 1430 } 1431 1432 return result; 1433} 1434 1435void __init 1436pci_init_resource(struct resource *res, unsigned long start, unsigned long end, 1437 int flags, char *name) 1438{ 1439 res->start = start; 1440 res->end = end; 1441 res->flags = flags; 1442 res->name = name; 1443 res->parent = NULL; 1444 res->sibling = NULL; 1445 res->child = NULL; 1446} 1447 1448/* 1449 * Null PCI config access functions, for the case when we can't 1450 * find a hose. 1451 */ 1452#define NULL_PCI_OP(rw, size, type) \ 1453static int \ 1454null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1455{ \ 1456 return PCIBIOS_DEVICE_NOT_FOUND; \ 1457} 1458 1459NULL_PCI_OP(read, byte, u8 *) 1460NULL_PCI_OP(read, word, u16 *) 1461NULL_PCI_OP(read, dword, u32 *) 1462NULL_PCI_OP(write, byte, u8) 1463NULL_PCI_OP(write, word, u16) 1464NULL_PCI_OP(write, dword, u32) 1465 1466static struct pci_ops null_pci_ops = 1467{ 1468 null_read_config_byte, 1469 null_read_config_word, 1470 null_read_config_dword, 1471 null_write_config_byte, 1472 null_write_config_word, 1473 null_write_config_dword 1474}; 1475 1476/* 1477 * These functions are used early on before PCI scanning is done 1478 * and all of the pci_dev and pci_bus structures have been created. 1479 */ 1480static struct pci_dev * 1481fake_pci_dev(struct pci_controller *hose, int busnr, int devfn) 1482{ 1483 static struct pci_dev dev; 1484 static struct pci_bus bus; 1485 1486 if (hose == 0) { 1487 hose = pci_bus_to_hose(busnr); 1488 if (hose == 0) 1489 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1490 } 1491 dev.bus = &bus; 1492 dev.sysdata = hose; 1493 dev.devfn = devfn; 1494 bus.number = busnr; 1495 bus.ops = hose? hose->ops: &null_pci_ops; 1496 return &dev; 1497} 1498 1499#define EARLY_PCI_OP(rw, size, type) \ 1500int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1501 int devfn, int offset, type value) \ 1502{ \ 1503 return pci_##rw##_config_##size(fake_pci_dev(hose, bus, devfn), \ 1504 offset, value); \ 1505} 1506 1507EARLY_PCI_OP(read, byte, u8 *) 1508EARLY_PCI_OP(read, word, u16 *) 1509EARLY_PCI_OP(read, dword, u32 *) 1510EARLY_PCI_OP(write, byte, u8) 1511EARLY_PCI_OP(write, word, u16) 1512EARLY_PCI_OP(write, dword, u32) 1513