1/* 2 * BK Id: %F% %I% %G% %U% %#% 3 */ 4/* 5 * arch/ppc/kernel/cputable.c 6 * 7 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 15#include <linux/config.h> 16#include <linux/string.h> 17#include <linux/sched.h> 18#include <linux/threads.h> 19#include <linux/init.h> 20#include <asm/cputable.h> 21 22struct cpu_spec* cur_cpu_spec[NR_CPUS]; 23 24extern void __setup_cpu_601(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 25extern void __setup_cpu_603(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 26extern void __setup_cpu_604(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 27extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 28extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 29extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 30extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 31extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 32extern void __setup_cpu_7450(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 33extern void __setup_cpu_7455(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 34extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 35extern void __setup_cpu_power4(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 36extern void __setup_cpu_8xx(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 37extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 38 39#define CLASSIC_PPC (!defined(CONFIG_8xx) && \ 40 !defined(CONFIG_4xx) && !defined(CONFIG_POWER3) && \ 41 !defined(CONFIG_POWER4) && !defined(CONFIG_PPC_ISERIES)) 42 43/* This table only contains "desktop" CPUs, it need to be filled with embedded 44 * ones as well... 45 */ 46#define COMMON_PPC (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \ 47 PPC_FEATURE_HAS_MMU) 48 49/* We only set the altivec features if the kernel was compiled with altivec 50 * support 51 */ 52#ifdef CONFIG_ALTIVEC 53#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 54#else 55#define CPU_FTR_ALTIVEC_COMP 0 56#endif 57 58struct cpu_spec cpu_specs[] = { 59#if CLASSIC_PPC 60 { /* 601 */ 61 0xffff0000, 0x00010000, "601", 62 CPU_FTR_601 | CPU_FTR_HPTE_TABLE, 63 COMMON_PPC | PPC_FEATURE_601_INSTR | PPC_FEATURE_UNIFIED_CACHE, 64 32, 32, 65 __setup_cpu_601 66 }, 67 { /* 603 */ 68 0xffff0000, 0x00030000, "603", 69 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 70 CPU_FTR_CAN_NAP, 71 COMMON_PPC, 72 32, 32, 73 __setup_cpu_603 74 }, 75 { /* 603e */ 76 0xffff0000, 0x00060000, "603e", 77 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 78 CPU_FTR_CAN_NAP, 79 COMMON_PPC, 80 32, 32, 81 __setup_cpu_603 82 }, 83 { /* 603ev */ 84 0xffff0000, 0x00070000, "603ev", 85 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 86 CPU_FTR_CAN_NAP, 87 COMMON_PPC, 88 32, 32, 89 __setup_cpu_603 90 }, 91 { /* 604 */ 92 0xffff0000, 0x00040000, "604", 93 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | 94 CPU_FTR_HPTE_TABLE, 95 COMMON_PPC, 96 32, 32, 97 __setup_cpu_604 98 }, 99 { /* 604e */ 100 0xfffff000, 0x00090000, "604e", 101 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | 102 CPU_FTR_HPTE_TABLE, 103 COMMON_PPC, 104 32, 32, 105 __setup_cpu_604 106 }, 107 { /* 604r */ 108 0xffff0000, 0x00090000, "604r", 109 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | 110 CPU_FTR_HPTE_TABLE, 111 COMMON_PPC, 112 32, 32, 113 __setup_cpu_604 114 }, 115 { /* 604ev */ 116 0xffff0000, 0x000a0000, "604ev", 117 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | 118 CPU_FTR_HPTE_TABLE, 119 COMMON_PPC, 120 32, 32, 121 __setup_cpu_604 122 }, 123 { /* 740/750 (0x4202, don't support TAU ?) */ 124 0xffffffff, 0x00084202, "740/750", 125 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 126 CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP, 127 COMMON_PPC, 128 32, 32, 129 __setup_cpu_750 130 }, 131 { /* 745/755 */ 132 0xfffff000, 0x00083000, "745/755", 133 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 134 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP, 135 COMMON_PPC, 136 32, 32, 137 __setup_cpu_750 138 }, 139 { /* 750CX */ 140 0xffffff00, 0x00082200, "750CX", 141 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 142 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP, 143 COMMON_PPC, 144 32, 32, 145 __setup_cpu_750cx 146 }, 147 { /* 750FX (All revs for now) */ 148 0xffff0000, 0x70000000, "750FX", 149 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 150 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP | 151 CPU_FTR_DUAL_PLL_750FX, 152 COMMON_PPC, 153 32, 32, 154 __setup_cpu_750fx 155 }, 156 { /* 740/750 (L2CR bit need fixup for 740) */ 157 0xffff0000, 0x00080000, "740/750", 158 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 159 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP, 160 COMMON_PPC, 161 32, 32, 162 __setup_cpu_750 163 }, 164 { /* 7400 rev 1.1 ? (no TAU) */ 165 0xffffffff, 0x000c1101, "7400 (1.1)", 166 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 167 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | 168 CPU_FTR_CAN_NAP, 169 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 170 32, 32, 171 __setup_cpu_7400 172 }, 173 { /* 7400 */ 174 0xffff0000, 0x000c0000, "7400", 175 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 176 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | 177 CPU_FTR_CAN_NAP, 178 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 179 32, 32, 180 __setup_cpu_7400 181 }, 182 { /* 7410 */ 183 0xffff0000, 0x800c0000, "7410", 184 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 185 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | 186 CPU_FTR_CAN_NAP, 187 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 188 32, 32, 189 __setup_cpu_7410 190 }, 191 { /* 7450 2.0 - no doze/nap */ 192 0xffffffff, 0x80000200, "7450", 193 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 194 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 195 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450, 196 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 197 32, 32, 198 __setup_cpu_7450 199 }, 200 { /* 7450 2.1 */ 201 0xffffffff, 0x80000201, "7450", 202 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP | 203 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 204 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | 205 CPU_FTR_L3_DISABLE_NAP, 206 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 207 32, 32, 208 __setup_cpu_7450 209 }, 210 { /* 7450 2.3 and newer */ 211 0xffff0000, 0x80000000, "7450", 212 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP | 213 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 214 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR, 215 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 216 32, 32, 217 __setup_cpu_7450 218 }, 219 { /* 7455 rev 1.x */ 220 0xffffff00, 0x80010100, "7455", 221 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 222 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 223 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450, 224 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 225 32, 32, 226 __setup_cpu_7455 227 }, 228 { /* 7455 rev 2.0 */ 229 0xffffffff, 0x80010200, "7455", 230 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP | 231 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 232 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | 233 CPU_FTR_L3_DISABLE_NAP, 234 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 235 32, 32, 236 __setup_cpu_7455 237 }, 238 { /* 7455 others */ 239 0xffff0000, 0x80010000, "7455", 240 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP | 241 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 242 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR, 243 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 244 32, 32, 245 __setup_cpu_7455 246 }, 247 { /* 82xx (8240, 8245, 8260 are all 603e cores) */ 248 0x7fff0000, 0x00810000, "82xx", 249 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB, 250 COMMON_PPC, 251 32, 32, 252 __setup_cpu_603 253 }, 254 { /* default match, we assume split I/D cache & TB (non-601)... */ 255 0x00000000, 0x00000000, "(generic PPC)", 256 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, 257 COMMON_PPC, 258 32, 32, 259 __setup_cpu_generic 260 }, 261#endif /* CLASSIC_PPC */ 262#ifdef CONFIG_PPC64BRIDGE 263 { /* Power3 */ 264 0xffff0000, 0x00400000, "Power3 (630)", 265 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, 266 COMMON_PPC | PPC_FEATURE_64, 267 128, 128, 268 __setup_cpu_power3 269 }, 270 { /* Power3+ */ 271 0xffff0000, 0x00410000, "Power3 (630+)", 272 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, 273 COMMON_PPC | PPC_FEATURE_64, 274 128, 128, 275 __setup_cpu_power3 276 }, 277 { /* I-star */ 278 0xffff0000, 0x00360000, "I-star", 279 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, 280 COMMON_PPC | PPC_FEATURE_64, 281 128, 128, 282 __setup_cpu_power3 283 }, 284 { /* S-star */ 285 0xffff0000, 0x00370000, "S-star", 286 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, 287 COMMON_PPC | PPC_FEATURE_64, 288 128, 128, 289 __setup_cpu_power3 290 }, 291#endif /* CONFIG_PPC64BRIDGE */ 292#ifdef CONFIG_POWER4 293 { /* Power4 */ 294 0xffff0000, 0x00350000, "Power4", 295 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, 296 COMMON_PPC | PPC_FEATURE_64, 297 128, 128, 298 __setup_cpu_power4 299 }, 300#endif /* CONFIG_POWER4 */ 301#ifdef CONFIG_8xx 302 { /* 8xx */ 303 0xffff0000, 0x00500000, "8xx", 304 /* CPU_FTR_CAN_DOZE is possible, if the 8xx code is there.... */ 305 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 306 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 307 16, 16, 308 __setup_cpu_8xx /* Empty */ 309 }, 310#endif /* CONFIG_8xx */ 311#ifdef CONFIG_4xx 312 { /* 403GC */ 313 0xffffff00, 0x00200200, "403GC", 314 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 315 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 316 16, 16, 317 0, /*__setup_cpu_403 */ 318 }, 319 { /* 403GCX */ 320 0xffffff00, 0x00201400, "403GCX", 321 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 322 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 323 16, 16, 324 0, /*__setup_cpu_403 */ 325 }, 326 { /* 403G ?? */ 327 0xffff0000, 0x00200000, "403G ??", 328 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 329 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 330 16, 16, 331 0, /*__setup_cpu_403 */ 332 }, 333 { /* 405GP */ 334 0xffff0000, 0x40110000, "405GP", 335 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 336 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 337 32, 32, 338 0, /*__setup_cpu_405 */ 339 }, 340 { /* STB 03xxx */ 341 0xffff0000, 0x40130000, "STB03xxx", 342 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 343 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 344 32, 32, 345 0, /*__setup_cpu_405 */ 346 }, 347#endif /* CONFIG_4xx */ 348#if !CLASSIC_PPC 349 { /* default match */ 350 0x00000000, 0x00000000, "(generic PPC)", 351 0, 352 PPC_FEATURE_32, 353 32, 32, 354 0, 355 } 356#endif /* !CLASSIC_PPC */ 357}; 358