1/*
2 * SNI RM200 PCI specific interrupt handler code.
3 *
4 * Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000, 01 by Ralf Baechle
5 */
6#include <asm/asm.h>
7#include <asm/mipsregs.h>
8#include <asm/regdef.h>
9#include <asm/sni.h>
10#include <asm/stackframe.h>
11
12/*
13 * The PCI ASIC has the nasty property that it may delay writes if it is busy.
14 * As a consequence from writes that have not graduated when we exit from the
15 * interrupt handler we might catch a spurious interrupt.  To avoid this we
16 * force the PCI ASIC to graduate all writes by executing a read from the
17 * PCI bus.
18 */
19		.set	noreorder
20		.set	noat
21		.align	5
22		NESTED(sni_rm200_pci_handle_int, PT_SIZE, sp)
23		SAVE_ALL
24		CLI
25		.set	at
26
27		/* Blinken light ...  */
28		lb	t0, led_cache
29		addiu	t0, 1
30		sb	t0, led_cache
31		sb	t0, PCIMT_CSLED			# write only register
32		.data
33led_cache:	.byte	0
34		.text
35
36		mfc0	t0, CP0_STATUS
37		mfc0	t1, CP0_CAUSE
38		and	t0, t1
39
40		 andi	t1, t0, 0x4a00			# hardware interrupt 1
41		bnez	t1, _hwint134
42		 andi	t1, t0, 0x1000			# hardware interrupt 2
43		bnez	t1, _hwint2
44		 andi	t1, t0, 0x8000			# hardware interrupt 5
45		bnez	t1, _hwint5
46		 andi	t1, t0, 0x0400			# hardware interrupt 0
47		bnez	t1, _hwint0
48		 nop
49
50		j	ret_from_irq			# spurious interrupt
51		 nop
52
53 ##############################################################################
54
55/* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
56   button interrupts.  */
57_hwint0:	jal	pciasic_hwint0
58		 move	a1, sp
59
60/*
61 * hwint 1 deals with EISA and SCSI interrupts,
62 * hwint 3 should deal with the PCI A - D interrupts,
63 * hwint 4 is used for only the onboard PCnet 32.
64 */
65_hwint134:	jal	pciasic_hwint134
66
67
68/* This interrupt was used for the com1 console on the first prototypes.  */
69_hwint2:	jal	pciasic_hwint2
70
71/* hwint5 is the r4k count / compare interrupt  */
72_hwint5:	jal	pciasic_hwint5
73
74		END(sni_rm200_pci_handle_int)
75