1/* 2 * Copyright 2001 MontaVista Software Inc. 3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 4 * 5 * Modified to be mips generic, ppopov@mvista.com 6 * arch/mips/kernl/pci.c 7 * Common MIPS PCI routines. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15/* 16 * This file contains common PCI routines meant to be shared for 17 * all MIPS machines. 18 * 19 * Strategies: 20 * 21 * . We rely on pci_auto.c file to assign PCI resources (MEM and IO) 22 * TODO: this shold be optional for some machines where they do have 23 * a real "pcibios" that does resource assignment. 24 * 25 * . We then use pci_scan_bus() to "discover" all the resources for 26 * later use by Linux. 27 * 28 * . We finally reply on a board supplied function, pcibios_fixup_irq(), to 29 * to assign the interrupts. We may use setup-irq.c under drivers/pci 30 * later. 31 * 32 * . Specifically, we will *NOT* use pci_assign_unassigned_resources(), 33 * because we assume all PCI devices should have the resources correctly 34 * assigned and recorded. 35 * 36 * Limitations: 37 * 38 * . We "collapse" all IO and MEM spaces in sub-buses under a top-level bus 39 * into a contiguous range. 40 * 41 * . In the case of Memory space, the rnage is 1:1 mapping with CPU physical 42 * address space. 43 * 44 * . In the case of IO space, it starts from 0, and the beginning address 45 * is mapped to KSEG0ADDR(mips_io_port) in the CPU physical address. 46 * 47 * . These are the current MIPS limitations (by ioremap, etc). In the 48 * future, we may remove them. 49 * 50 * Credits: 51 * Most of the code are derived from the pci routines from PPC and Alpha, 52 * which were mostly writtne by 53 * Cort Dougan, cort@fsmlabs.com 54 * Matt Porter, mporter@mvista.com 55 * Dave Rusling david.rusling@reo.mts.dec.com 56 * David Mosberger davidm@cs.arizona.edu 57 */ 58#include <linux/config.h> 59#include <linux/kernel.h> 60#include <linux/init.h> 61#include <linux/types.h> 62#include <linux/pci.h> 63 64#include <asm/pci_channel.h> 65 66extern void pcibios_fixup(void); 67extern void pcibios_fixup_irqs(void); 68 69struct pci_fixup pcibios_fixups[] = { 70 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources }, 71 { 0 } 72}; 73 74extern int pciauto_assign_resources(int busno, struct pci_channel * hose); 75 76void __init pcibios_init(void) 77{ 78 struct pci_channel *p; 79 struct pci_bus *bus; 80 int busno; 81 82#ifdef CONFIG_PCI_AUTO 83 /* assign resources */ 84 busno=0; 85 for (p= mips_pci_channels; p->pci_ops != NULL; p++) { 86 busno = pciauto_assign_resources(busno, p) + 1; 87 } 88#endif 89 90 /* scan the buses */ 91 busno = 0; 92 for (p= mips_pci_channels; p->pci_ops != NULL; p++) { 93 bus = pci_scan_bus(busno, p->pci_ops, p); 94 busno = bus->subordinate+1; 95 } 96 97 /* machine dependent fixups */ 98 pcibios_fixup(); 99 /* fixup irqs (board specific routines) */ 100 pcibios_fixup_irqs(); 101} 102 103int pcibios_enable_device(struct pci_dev *dev, int mask) 104{ 105 /* pciauto_assign_resources() will enable all devices found */ 106 return 0; 107} 108 109unsigned long __init pci_bridge_check_io(struct pci_dev *bridge) 110{ 111 u16 io; 112 113 pci_read_config_word(bridge, PCI_IO_BASE, &io); 114 if (!io) { 115 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); 116 pci_read_config_word(bridge, PCI_IO_BASE, &io); 117 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 118 } 119 if (io) 120 return IORESOURCE_IO; 121 printk(KERN_WARNING "PCI: bridge %s does not support I/O forwarding!\n", 122 bridge->name); 123 return 0; 124} 125 126void __init pcibios_fixup_bus(struct pci_bus *bus) 127{ 128 /* Propogate hose info into the subordinate devices. */ 129 130 struct pci_channel *hose = bus->sysdata; 131 struct pci_dev *dev = bus->self; 132 133 if (!dev) { 134 /* Root bus */ 135 bus->resource[0] = hose->io_resource; 136 bus->resource[1] = hose->mem_resource; 137 } else { 138 /* This is a bridge. Do not care how it's initialized, 139 just link its resources to the bus ones */ 140 int i; 141 142 for(i=0; i<3; i++) { 143 bus->resource[i] = 144 &dev->resource[PCI_BRIDGE_RESOURCES+i]; 145 bus->resource[i]->name = bus->name; 146 } 147 bus->resource[0]->flags |= pci_bridge_check_io(dev); 148 bus->resource[1]->flags |= IORESOURCE_MEM; 149 /* For now, propogate hose limits to the bus; 150 we'll adjust them later. */ 151 bus->resource[0]->end = hose->io_resource->end; 152 bus->resource[1]->end = hose->mem_resource->end; 153 /* Turn off downstream PF memory address range by default */ 154 bus->resource[2]->start = 1024*1024; 155 bus->resource[2]->end = bus->resource[2]->start - 1; 156 } 157} 158 159char *pcibios_setup(char *str) 160{ 161 return str; 162} 163 164void 165pcibios_align_resource(void *data, struct resource *res, unsigned long size, 166 unsigned long align) 167{ 168 /* this should not be called */ 169} 170 171void 172pcibios_update_resource(struct pci_dev *dev, struct resource *root, 173 struct resource *res, int resource) 174{ 175 /* this should not be called */ 176} 177