1/* 2 * 3 * BRIEF MODULE DESCRIPTION 4 * Galileo EV96100 setup. 5 * 6 * Copyright 2000 MontaVista Software Inc. 7 * Author: MontaVista Software, Inc. 8 * ppopov@mvista.com or source@mvista.com 9 * 10 * This file was derived from Carsten Langgaard's 11 * arch/mips/mips-boards/atlas/atlas_setup.c. 12 * 13 * Carsten Langgaard, carstenl@mips.com 14 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 15 * 16 * This program is free software; you can redistribute it and/or modify it 17 * under the terms of the GNU General Public License as published by the 18 * Free Software Foundation; either version 2 of the License, or (at your 19 * option) any later version. 20 * 21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * You should have received a copy of the GNU General Public License along 33 * with this program; if not, write to the Free Software Foundation, Inc., 34 * 675 Mass Ave, Cambridge, MA 02139, USA. 35 */ 36#include <linux/config.h> 37#include <linux/init.h> 38#include <linux/sched.h> 39#include <linux/ioport.h> 40#include <linux/mc146818rtc.h> 41#include <linux/string.h> 42#include <linux/ctype.h> 43#include <linux/pci.h> 44 45#include <asm/cpu.h> 46#include <asm/bootinfo.h> 47#include <asm/mipsregs.h> 48#include <asm/irq.h> 49#include <asm/delay.h> 50#include <asm/gt64120.h> 51#include <asm/galileo-boards/ev96100.h> 52#include <asm/galileo-boards/ev96100int.h> 53 54 55#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE) 56extern void console_setup(char *, int *); 57char serial_console[20]; 58#endif 59 60extern char * __init prom_getcmdline(void); 61 62extern void mips_reboot_setup(void); 63extern struct rtc_ops no_rtc_ops; 64extern struct resource ioport_resource; 65 66unsigned char mac_0_1[12]; 67 68void __init bus_error_init(void) 69{ 70} 71 72void __init ev96100_setup(void) 73{ 74 unsigned int config = read_c0_config(); 75 unsigned int status = read_c0_status(); 76 unsigned int info = read_c0_info(); 77 u32 tmp; 78 79 char *argptr; 80 81 clear_c0_status(ST0_FR); 82 83 if (config & 0x8) { 84 printk("Secondary cache is enabled\n"); 85 } 86 else { 87 printk("Secondary cache is disabled\n"); 88 } 89 90 if (status & (1<<27)) { 91 printk("User-mode cache ops enabled\n"); 92 } 93 else { 94 printk("User-mode cache ops disabled\n"); 95 } 96 97 printk("CP0 info reg: %x\n", (unsigned)info); 98 if (info & (1<<28)) { 99 printk("burst mode Scache RAMS\n"); 100 } 101 else { 102 printk("pipelined Scache RAMS\n"); 103 } 104 105 if ((info & (0x3<<26)) >> 26 == 0) { 106 printk("67 percent drive strength\n"); 107 } 108 else if ((info & (0x3<<26)) >> 26 == 1) { 109 printk("50 percent drive strength\n"); 110 } 111 else if ((info & (0x3<<26)) >> 26 == 2) { 112 printk("100 percent drive strength\n"); 113 } 114 else if ((info & (0x3<<26)) >> 26 == 3) { 115 printk("83 percent drive strength\n"); 116 } 117 118 119 if ((info & (0x3<<23)) >> 23 == 0) { 120 printk("Write Protocol: R4000 compatible\n"); 121 } 122 else if ((info & (0x3<<23)) >> 23 == 1) { 123 printk("Write Protocol: Reserved\n"); 124 } 125 else if ((info & (0x3<<23)) >> 23 == 2) { 126 printk("Write Protocol: Pipelined\n"); 127 } 128 else if ((info & (0x3<<23)) >> 23 == 3) { 129 printk("Write Protocol: Write re-issue\n"); 130 } 131 132 if (info & 0x1) { 133 printk("Atomic Enable is set\n"); 134 } 135 136 argptr = prom_getcmdline(); 137#ifdef CONFIG_SERIAL_CONSOLE 138 if (strstr(argptr, "console=") == NULL) { 139 argptr = prom_getcmdline(); 140 strcat(argptr, " console=ttyS0,115200"); 141 } 142#endif 143 144 rtc_ops = &no_rtc_ops; 145 mips_reboot_setup(); 146 set_io_port_base(KSEG1); 147 ioport_resource.start = GT_PCI_IO_BASE; 148 ioport_resource.end = GT_PCI_IO_BASE + 0x01ffffff; 149 150#ifdef CONFIG_BLK_DEV_INITRD 151 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); 152#endif 153 154 155 /* 156 * setup gt controller master bit so we can do config cycles 157 */ 158 159 /* Clear cause register bits */ 160 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | 161 GT_INTRCAUSE_TARABORT0_BIT)); 162 /* Setup address */ 163 GT_WRITE(GT_PCI0_CFGADDR_OFS, 164 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | 165 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | 166 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | 167 GT_PCI0_CFGADDR_CONFIGEN_BIT); 168 169 udelay(2); 170 tmp = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS)); 171 172 tmp |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 173 PCI_COMMAND_MASTER | PCI_COMMAND_SERR); 174 GT_WRITE(GT_PCI0_CFGADDR_OFS, 175 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | 176 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | 177 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | 178 GT_PCI0_CFGADDR_CONFIGEN_BIT); 179 udelay(2); 180 *(volatile u32 *)(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS) = cpu_to_le32(tmp); 181 182 /* Setup address */ 183 GT_WRITE(GT_PCI0_CFGADDR_OFS, 184 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | 185 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | 186 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | 187 GT_PCI0_CFGADDR_CONFIGEN_BIT); 188 189 udelay(2); 190 tmp = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS)); 191} 192 193unsigned short get_gt_devid() 194{ 195 u32 gt_devid; 196 197 /* Figure out if this is a gt96100 or gt96100A */ 198 GT_WRITE(GT_PCI0_CFGADDR_OFS, 199 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | 200 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | 201 ((PCI_VENDOR_ID / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | 202 GT_PCI0_CFGADDR_CONFIGEN_BIT); 203 204 udelay(4); 205 gt_devid = le32_to_cpu(*(volatile u32 *) 206 (MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS)); 207 return (unsigned short)(gt_devid>>16); 208} 209