1/* 2 * BRIEF MODULE DESCRIPTION 3 * Au1000 interrupt routines. 4 * 5 * Copyright 2001 MontaVista Software Inc. 6 * Author: MontaVista Software, Inc. 7 * ppopov@mvista.com or source@mvista.com 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, write to the Free Software Foundation, Inc., 27 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 */ 29#include <linux/errno.h> 30#include <linux/init.h> 31#include <linux/kernel_stat.h> 32#include <linux/module.h> 33#include <linux/signal.h> 34#include <linux/sched.h> 35#include <linux/types.h> 36#include <linux/interrupt.h> 37#include <linux/ioport.h> 38#include <linux/timex.h> 39#include <linux/slab.h> 40#include <linux/random.h> 41#include <linux/delay.h> 42 43#include <asm/bitops.h> 44#include <asm/bootinfo.h> 45#include <asm/io.h> 46#include <asm/mipsregs.h> 47#include <asm/system.h> 48#include <asm/au1000.h> 49 50#if defined(CONFIG_MIPS_PB1000) 51#include <asm/pb1000.h> 52#elif defined(CONFIG_MIPS_PB1500) 53#include <asm/pb1500.h> 54#elif defined(CONFIG_MIPS_PB1100) 55#include <asm/pb1100.h> 56#elif defined(CONFIG_MIPS_DB1000) 57#include <asm/db1x00.h> 58#elif defined(CONFIG_MIPS_DB1100) 59#include <asm/db1x00.h> 60#elif defined(CONFIG_MIPS_DB1500) 61#include <asm/db1x00.h> 62#else 63#error unsupported Alchemy board 64#endif 65 66#undef DEBUG_IRQ 67#ifdef DEBUG_IRQ 68/* note: prints function name for you */ 69#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args) 70#else 71#define DPRINTK(fmt, args...) 72#endif 73 74#define EXT_INTC0_REQ0 2 /* IP 2 */ 75#define EXT_INTC0_REQ1 3 /* IP 3 */ 76#define EXT_INTC1_REQ0 4 /* IP 4 */ 77#define EXT_INTC1_REQ1 5 /* IP 5 */ 78#define MIPS_TIMER_IP 7 /* IP 7 */ 79 80#ifdef CONFIG_REMOTE_DEBUG 81extern void breakpoint(void); 82#endif 83 84extern asmlinkage void au1000_IRQ(void); 85extern void set_debug_traps(void); 86extern irq_cpustat_t irq_stat [NR_CPUS]; 87unsigned int local_bh_count[NR_CPUS]; 88unsigned int local_irq_count[NR_CPUS]; 89 90static void setup_local_irq(unsigned int irq, int type, int int_req); 91static unsigned int startup_irq(unsigned int irq); 92static void end_irq(unsigned int irq_nr); 93static inline void mask_and_ack_level_irq(unsigned int irq_nr); 94static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr); 95static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr); 96inline void local_enable_irq(unsigned int irq_nr); 97inline void local_disable_irq(unsigned int irq_nr); 98 99extern unsigned int do_IRQ(int irq, struct pt_regs *regs); 100extern void __init init_generic_irq(void); 101 102#ifdef CONFIG_PM 103extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs); 104#endif 105 106static spinlock_t irq_lock = SPIN_LOCK_UNLOCKED; 107 108static void setup_local_irq(unsigned int irq_nr, int type, int int_req) 109{ 110 if (irq_nr > AU1000_MAX_INTR) return; 111 /* Config2[n], Config1[n], Config0[n] */ 112 if (irq_nr > AU1000_LAST_INTC0_INT) { 113 switch (type) { 114 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 115 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 116 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 117 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 118 break; 119 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 120 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 121 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 122 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 123 break; 124 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 125 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 126 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 127 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 128 break; 129 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 130 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 131 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 132 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 133 break; 134 case INTC_INT_DISABLED: /* 0:0:0 */ 135 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 136 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 137 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 138 break; 139 default: /* disable the interrupt */ 140 printk("unexpected int type %d (irq %d)\n", type, irq_nr); 141 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 142 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 143 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 144 return; 145 } 146 if (int_req) /* assign to interrupt request 1 */ 147 au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR); 148 else /* assign to interrupt request 0 */ 149 au_writel(1<<(irq_nr-32), IC1_ASSIGNSET); 150 au_writel(1<<(irq_nr-32), IC1_SRCSET); 151 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 152 au_writel(1<<(irq_nr-32), IC1_WAKECLR); 153 } 154 else { 155 switch (type) { 156 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 157 au_writel(1<<irq_nr, IC0_CFG2CLR); 158 au_writel(1<<irq_nr, IC0_CFG1CLR); 159 au_writel(1<<irq_nr, IC0_CFG0SET); 160 break; 161 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 162 au_writel(1<<irq_nr, IC0_CFG2CLR); 163 au_writel(1<<irq_nr, IC0_CFG1SET); 164 au_writel(1<<irq_nr, IC0_CFG0CLR); 165 break; 166 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 167 au_writel(1<<irq_nr, IC0_CFG2SET); 168 au_writel(1<<irq_nr, IC0_CFG1CLR); 169 au_writel(1<<irq_nr, IC0_CFG0SET); 170 break; 171 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 172 au_writel(1<<irq_nr, IC0_CFG2SET); 173 au_writel(1<<irq_nr, IC0_CFG1SET); 174 au_writel(1<<irq_nr, IC0_CFG0CLR); 175 break; 176 case INTC_INT_DISABLED: /* 0:0:0 */ 177 au_writel(1<<irq_nr, IC0_CFG0CLR); 178 au_writel(1<<irq_nr, IC0_CFG1CLR); 179 au_writel(1<<irq_nr, IC0_CFG2CLR); 180 break; 181 default: /* disable the interrupt */ 182 printk("unexpected int type %d (irq %d)\n", type, irq_nr); 183 au_writel(1<<irq_nr, IC0_CFG0CLR); 184 au_writel(1<<irq_nr, IC0_CFG1CLR); 185 au_writel(1<<irq_nr, IC0_CFG2CLR); 186 return; 187 } 188 if (int_req) /* assign to interrupt request 1 */ 189 au_writel(1<<irq_nr, IC0_ASSIGNCLR); 190 else /* assign to interrupt request 0 */ 191 au_writel(1<<irq_nr, IC0_ASSIGNSET); 192 au_writel(1<<irq_nr, IC0_SRCSET); 193 au_writel(1<<irq_nr, IC0_MASKCLR); 194 au_writel(1<<irq_nr, IC0_WAKECLR); 195 } 196 au_sync(); 197} 198 199 200static unsigned int startup_irq(unsigned int irq_nr) 201{ 202 local_enable_irq(irq_nr); 203 return 0; 204} 205 206 207static void shutdown_irq(unsigned int irq_nr) 208{ 209 local_disable_irq(irq_nr); 210 return; 211} 212 213 214inline void local_enable_irq(unsigned int irq_nr) 215{ 216 if (irq_nr > AU1000_LAST_INTC0_INT) { 217 au_writel(1<<(irq_nr-32), IC1_MASKSET); 218 au_writel(1<<(irq_nr-32), IC1_WAKESET); 219 } 220 else { 221 au_writel(1<<irq_nr, IC0_MASKSET); 222 au_writel(1<<irq_nr, IC0_WAKESET); 223 } 224 au_sync(); 225} 226 227 228inline void local_disable_irq(unsigned int irq_nr) 229{ 230 if (irq_nr > AU1000_LAST_INTC0_INT) { 231 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 232 au_writel(1<<(irq_nr-32), IC1_WAKECLR); 233 } 234 else { 235 au_writel(1<<irq_nr, IC0_MASKCLR); 236 au_writel(1<<irq_nr, IC0_WAKECLR); 237 } 238 au_sync(); 239} 240 241 242static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr) 243{ 244 if (irq_nr > AU1000_LAST_INTC0_INT) { 245 au_writel(1<<(irq_nr-32), IC1_RISINGCLR); 246 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 247 } 248 else { 249 au_writel(1<<irq_nr, IC0_RISINGCLR); 250 au_writel(1<<irq_nr, IC0_MASKCLR); 251 } 252 au_sync(); 253} 254 255 256static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr) 257{ 258 if (irq_nr > AU1000_LAST_INTC0_INT) { 259 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR); 260 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 261 } 262 else { 263 au_writel(1<<irq_nr, IC0_FALLINGCLR); 264 au_writel(1<<irq_nr, IC0_MASKCLR); 265 } 266 au_sync(); 267} 268 269 270static inline void mask_and_ack_level_irq(unsigned int irq_nr) 271{ 272 273 local_disable_irq(irq_nr); 274 au_sync(); 275#if defined(CONFIG_MIPS_PB1000) 276 if (irq_nr == AU1000_GPIO_15) { 277 au_writel(0x8000, PB1000_MDR); /* ack int */ 278 au_sync(); 279 } 280#endif 281 return; 282} 283 284 285static void end_irq(unsigned int irq_nr) 286{ 287 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { 288 local_enable_irq(irq_nr); 289 } 290 else { 291 printk("warning: end_irq %d did not enable (%x)\n", 292 irq_nr, irq_desc[irq_nr].status); 293 } 294#if defined(CONFIG_MIPS_PB1000) 295 if (irq_nr == AU1000_GPIO_15) { 296 au_writel(0x4000, PB1000_MDR); /* enable int */ 297 au_sync(); 298 } 299#endif 300} 301 302unsigned long save_local_and_disable(int controller) 303{ 304 int i; 305 unsigned long flags, mask; 306 307 spin_lock_irqsave(&irq_lock, flags); 308 if (controller) { 309 mask = au_readl(IC1_MASKSET); 310 for (i=32; i<64; i++) { 311 local_disable_irq(i); 312 } 313 } 314 else { 315 mask = au_readl(IC0_MASKSET); 316 for (i=0; i<32; i++) { 317 local_disable_irq(i); 318 } 319 } 320 spin_unlock_irqrestore(&irq_lock, flags); 321 322 return mask; 323} 324 325void restore_local_and_enable(int controller, unsigned long mask) 326{ 327 int i; 328 unsigned long flags, new_mask; 329 330 spin_lock_irqsave(&irq_lock, flags); 331 for (i=0; i<32; i++) { 332 if (mask & (1<<i)) { 333 if (controller) 334 local_enable_irq(i+32); 335 else 336 local_enable_irq(i); 337 } 338 } 339 if (controller) 340 new_mask = au_readl(IC1_MASKSET); 341 else 342 new_mask = au_readl(IC0_MASKSET); 343 344 spin_unlock_irqrestore(&irq_lock, flags); 345} 346 347 348static struct hw_interrupt_type rise_edge_irq_type = { 349 "Au1000 Rise Edge", 350 startup_irq, 351 shutdown_irq, 352 local_enable_irq, 353 local_disable_irq, 354 mask_and_ack_rise_edge_irq, 355 end_irq, 356 NULL 357}; 358 359/* 360static struct hw_interrupt_type fall_edge_irq_type = { 361 "Au1000 Fall Edge", 362 startup_irq, 363 shutdown_irq, 364 local_enable_irq, 365 local_disable_irq, 366 mask_and_ack_fall_edge_irq, 367 end_irq, 368 NULL 369}; 370*/ 371 372static struct hw_interrupt_type level_irq_type = { 373 "Au1000 Level", 374 startup_irq, 375 shutdown_irq, 376 local_enable_irq, 377 local_disable_irq, 378 mask_and_ack_level_irq, 379 end_irq, 380 NULL 381}; 382 383#ifdef CONFIG_PM 384void startup_match20_interrupt(void) 385{ 386 local_enable_irq(AU1000_TOY_MATCH2_INT); 387} 388#endif 389 390 391void __init init_IRQ(void) 392{ 393 int i; 394 unsigned long cp0_status; 395 396 cp0_status = read_c0_status(); 397 memset(irq_desc, 0, sizeof(irq_desc)); 398 set_except_vector(0, au1000_IRQ); 399 400 init_generic_irq(); 401 402 for (i = 0; i <= AU1000_MAX_INTR; i++) { 403 switch (i) { 404 case AU1000_UART0_INT: 405 case AU1000_UART3_INT: 406#ifdef CONFIG_MIPS_PB1000 407 case AU1000_UART1_INT: 408 case AU1000_UART2_INT: 409 410 case AU1000_SSI0_INT: 411 case AU1000_SSI1_INT: 412#endif 413 414#ifdef CONFIG_MIPS_PB1100 415 case AU1000_UART1_INT: 416 417 case AU1000_SSI0_INT: 418 case AU1000_SSI1_INT: 419#endif 420 case AU1000_DMA_INT_BASE: 421 case AU1000_DMA_INT_BASE+1: 422 case AU1000_DMA_INT_BASE+2: 423 case AU1000_DMA_INT_BASE+3: 424 case AU1000_DMA_INT_BASE+4: 425 case AU1000_DMA_INT_BASE+5: 426 case AU1000_DMA_INT_BASE+6: 427 case AU1000_DMA_INT_BASE+7: 428 429 case AU1000_IRDA_TX_INT: 430 case AU1000_IRDA_RX_INT: 431 432 case AU1000_MAC0_DMA_INT: 433#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1500) 434 case AU1000_MAC1_DMA_INT: 435#endif 436#ifdef CONFIG_MIPS_PB1500 437 case AU1000_MAC1_DMA_INT: 438#endif 439 case AU1500_GPIO_204: 440 441 setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0); 442 irq_desc[i].handler = &level_irq_type; 443 break; 444 445#ifdef CONFIG_MIPS_PB1000 446 case AU1000_GPIO_15: 447#endif 448 case AU1000_USB_HOST_INT: 449#ifdef CONFIG_MIPS_PB1500 450 case AU1000_PCI_INTA: 451 case AU1000_PCI_INTB: 452 case AU1000_PCI_INTC: 453 case AU1000_PCI_INTD: 454 case AU1500_GPIO_201: 455 case AU1500_GPIO_202: 456 case AU1500_GPIO_203: 457 case AU1500_GPIO_205: 458 case AU1500_GPIO_207: 459#endif 460 461#ifdef CONFIG_MIPS_PB1100 462 case AU1000_GPIO_9: // PCMCIA Card Fully_Interted# 463 case AU1000_GPIO_10: // PCMCIA_STSCHG# 464 case AU1000_GPIO_11: // PCMCIA_IRQ# 465 case AU1000_GPIO_13: // DC_IRQ# 466 case AU1000_GPIO_23: // 2-wire SCL 467#endif 468#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) 469 case AU1000_GPIO_0: // PCMCIA Card 0 Fully_Interted# 470 case AU1000_GPIO_1: // PCMCIA Card 0 STSCHG# 471 case AU1000_GPIO_2: // PCMCIA Card 0 IRQ# 472 473 case AU1000_GPIO_3: // PCMCIA Card 1 Fully_Interted# 474 case AU1000_GPIO_4: // PCMCIA Card 1 STSCHG# 475 case AU1000_GPIO_5: // PCMCIA Card 1 IRQ# 476#endif 477 setup_local_irq(i, INTC_INT_LOW_LEVEL, 0); 478 irq_desc[i].handler = &level_irq_type; 479 break; 480 case AU1000_ACSYNC_INT: 481 case AU1000_AC97C_INT: 482 case AU1000_TOY_INT: 483 case AU1000_TOY_MATCH0_INT: 484 case AU1000_TOY_MATCH1_INT: 485 case AU1000_USB_DEV_SUS_INT: 486 case AU1000_USB_DEV_REQ_INT: 487 case AU1000_RTC_INT: 488 case AU1000_RTC_MATCH0_INT: 489 case AU1000_RTC_MATCH1_INT: 490 case AU1000_RTC_MATCH2_INT: 491 setup_local_irq(i, INTC_INT_RISE_EDGE, 0); 492 irq_desc[i].handler = &rise_edge_irq_type; 493 break; 494 495 // Careful if you change match 2 request! 496 // The interrupt handler is called directly 497 // from the low level dispatch code. 498 case AU1000_TOY_MATCH2_INT: 499 setup_local_irq(i, INTC_INT_RISE_EDGE, 1); 500 irq_desc[i].handler = &rise_edge_irq_type; 501 break; 502 default: /* active high, level interrupt */ 503 setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0); 504 irq_desc[i].handler = &level_irq_type; 505 break; 506 } 507 } 508 509 set_c0_status(ALLINTS); 510#ifdef CONFIG_REMOTE_DEBUG 511 /* If local serial I/O used for debug port, enter kgdb at once */ 512 puts("Waiting for kgdb to connect..."); 513 set_debug_traps(); 514 breakpoint(); 515#endif 516} 517 518 519/* 520 * Interrupts are nested. Even if an interrupt handler is registered 521 * as "fast", we might get another interrupt before we return from 522 * intcX_reqX_irqdispatch(). 523 */ 524 525void intc0_req0_irqdispatch(struct pt_regs *regs) 526{ 527 int irq = 0, i; 528 static unsigned long intc0_req0 = 0; 529 530 intc0_req0 |= au_readl(IC0_REQ0INT); 531 532 if (!intc0_req0) return; 533 534 /* 535 * Because of the tight timing of SETUP token to reply 536 * transactions, the USB devices-side packet complete 537 * interrupt needs the highest priority. 538 */ 539 if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) { 540 intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT); 541 do_IRQ(AU1000_USB_DEV_REQ_INT, regs); 542 return; 543 } 544 545 for (i=0; i<32; i++) { 546 if ((intc0_req0 & (1<<i))) { 547 intc0_req0 &= ~(1<<i); 548 do_IRQ(irq, regs); 549 break; 550 } 551 irq++; 552 } 553} 554 555 556void intc0_req1_irqdispatch(struct pt_regs *regs) 557{ 558 int irq = 0, i; 559 static unsigned long intc0_req1 = 0; 560 561 intc0_req1 = au_readl(IC0_REQ1INT); 562 563 if (!intc0_req1) return; 564 565 for (i=0; i<32; i++) { 566 if ((intc0_req1 & (1<<i))) { 567 intc0_req1 &= ~(1<<i); 568#ifdef CONFIG_PM 569 if (i == AU1000_TOY_MATCH2_INT) { 570 mask_and_ack_rise_edge_irq(irq); 571 counter0_irq(irq, NULL, regs); 572 local_enable_irq(irq); 573 } 574 else 575#endif 576 { 577 do_IRQ(irq, regs); 578 } 579 break; 580 } 581 irq++; 582 } 583} 584 585 586/* 587 * Interrupt Controller 1: 588 * interrupts 32 - 63 589 */ 590void intc1_req0_irqdispatch(struct pt_regs *regs) 591{ 592 int irq = 0, i; 593 static unsigned long intc1_req0 = 0; 594 595 intc1_req0 |= au_readl(IC1_REQ0INT); 596 597 if (!intc1_req0) return; 598 599#if defined(CONFIG_MIPS_PB1000) && defined(DEBUG_IRQ) 600 au_writel(1, CPLD_AUX0); /* debug led 0 */ 601#endif 602 for (i=0; i<32; i++) { 603 if ((intc1_req0 & (1<<i))) { 604 intc1_req0 &= ~(1<<i); 605#if defined(CONFIG_MIPS_PB1000) && defined(DEBUG_IRQ) 606 au_writel(2, CPLD_AUX0); /* turn on debug led 1 */ 607 do_IRQ(irq+32, regs); 608 au_writel(0, CPLD_AUX0); /* turn off debug led 1 */ 609#else 610 do_IRQ(irq+32, regs); 611#endif 612 break; 613 } 614 irq++; 615 } 616#if defined(CONFIG_MIPS_PB1000) && defined(DEBUG_IRQ) 617 au_writel(0, CPLD_AUX0); 618#endif 619} 620 621 622void intc1_req1_irqdispatch(struct pt_regs *regs) 623{ 624 int irq = 0, i; 625 static unsigned long intc1_req1 = 0; 626 627 intc1_req1 |= au_readl(IC1_REQ1INT); 628 629 if (!intc1_req1) return; 630 631 for (i=0; i<32; i++) { 632 if ((intc1_req1 & (1<<i))) { 633 intc1_req1 &= ~(1<<i); 634 do_IRQ(irq+32, regs); 635 break; 636 } 637 irq++; 638 } 639} 640