1/* $Id: ide.c,v 1.1.1.1 2008/10/15 03:26:01 james26_jang Exp $ 2 * 3 * Etrax specific IDE functions, like init and PIO-mode setting etc. 4 * Almost the entire ide.c is used for the rest of the Etrax ATA driver. 5 * Copyright (c) 2000, 2001, 2002 Axis Communications AB 6 * 7 * Authors: Bjorn Wesen (initial version) 8 * Mikael Starvik (pio setup stuff) 9 * 10 * $Log: ide.c,v $ 11 * Revision 1.1.1.1 2008/10/15 03:26:01 james26_jang 12 * Initial. 13 * 14 * Revision 1.1.1.1 2008/07/21 09:14:22 james26_jang 15 * New UI, New QoS, New wireless driver(4.151.10.29), ipmonitor. 16 * 17 * Revision 1.1.1.1 2008/07/02 14:38:28 james26_jang 18 * 4.100.10.29, New QoS and New UI. 19 * 20 * Revision 1.1.1.1 2007/02/15 12:10:52 jiahao 21 * initial update 22 * 23 * Revision 1.1.1.1 2007/01/25 12:51:48 jiahao_jhou 24 * 25 * 26 * Revision 1.1.1.1 2003/02/03 22:37:20 mhuang 27 * LINUX_2_4 branch snapshot from linux-mips.org CVS 28 * 29 * Revision 1.24 2002/04/22 11:47:21 johana 30 * Fix according to 2.4.19-pre7. time_after/time_before and 31 * missing end of comment. 32 * The patch has a typo for ethernet.c in e100_clear_network_leds(), 33 * that is fixed here. 34 * 35 * Revision 1.23 2002/03/19 15:35:51 bjornw 36 * Cleaned up the bus-reset code a bit and made G27-reset work 37 * 38 * Revision 1.22 2002/03/19 15:23:05 bjornw 39 * Added flush_etrax_cache before starting the receiving DMA 40 * 41 * Revision 1.21 2002/03/06 15:37:56 hp 42 * * ide.c (OUT_BYTE): If timing out in the first busy-loop, do a 43 * printk, fall through and still do the write. 44 * (IN_BYTE): If timing out in the first loop, and reg indicated it's 45 * the ATA status register in the device being read, return BUSY_STAT. 46 * 47 * Revision 1.20 2002/02/22 11:47:56 bjornw 48 * Added a timeout to IN_BYTE and OUT_BYTE 49 * 50 * Revision 1.19 2001/05/09 12:53:16 johana 51 * Added #include <asm/dma.h> 52 * 53 * Revision 1.18 2001/05/09 12:37:00 johana 54 * Use DMA_NBR macros from dma.h. 55 * 56 * Revision 1.17 2001/04/23 13:36:30 matsfg 57 * Changed CONFIG_IDE_DELAY to CONFIG_ETRAX_IDE_DELAY 58 * 59 * Revision 1.16 2001/04/05 08:30:07 matsfg 60 * Corrected cse1 and csp0 reset. 61 * 62 * Revision 1.15 2001/04/04 14:34:06 bjornw 63 * Re-instated code that mysteriously disappeared during review updates. 64 * 65 * Revision 1.14 2001/04/04 13:45:12 matsfg 66 * Calls REG_SHADOW_SET for cse1 reset so only the resetbit is affected 67 * 68 * Revision 1.13 2001/04/04 13:26:40 matsfg 69 * memmapping is done in init.c 70 * 71 * Revision 1.12 2001/04/04 11:37:56 markusl 72 * Updated according to review remarks 73 * 74 * Revision 1.11 2001/03/29 12:49:14 matsfg 75 * Changed check for ata_tot_size from >= to >. 76 * Sets sw_len to 0 if size is exactly 65536. 77 * 78 * Revision 1.10 2001/03/16 09:39:30 matsfg 79 * Support for reset on port CSP0 80 * 81 * Revision 1.9 2001/03/01 13:11:18 bjornw 82 * 100 -> HZ 83 * 84 * Revision 1.8 2001/03/01 09:32:56 matsfg 85 * Moved IDE delay to a CONFIG-parameter instead 86 * 87 * Revision 1.7 2001/02/23 13:46:38 bjornw 88 * Spellling check 89 * 90 * Revision 1.6 2001/02/22 15:44:30 bjornw 91 * * Use ioremap when mapping the CSE1 memory-mapped reset-line for LX v2 92 * * sw_len for a 65536 descriptor is 0, not 65536 93 * * Express concern for G27 reset code 94 * 95 * Revision 1.5 2001/02/16 07:35:38 matsfg 96 * Now handles DMA request blocks between 64k and 128k by split into two descriptors. 97 * 98 * Revision 1.4 2001/01/10 21:14:32 bjornw 99 * Initialize hwif->ideproc, for the new way of handling ide_xxx_data 100 * 101 * Revision 1.3 2000/12/01 17:48:18 bjornw 102 * - atapi_output_bytes now uses DMA 103 * - dma_active check removed - the kernel does proper serializing and it had 104 * a race-condition anyway 105 * - ide_build_dmatable had a nameclash 106 * - re-added the RESET_DMA thingys because sometimes the interface can get 107 * stuck apparently 108 * - added ide_release_dma 109 * 110 * Revision 1.2 2000/11/29 17:31:29 bjornw 111 * 2.4 port 112 * 113 * - The "register addresses" stored in the hwif are now 32-bit fields that 114 * don't need to be shifted into correct positions in R_ATA_CTRL_DATA 115 * - PIO-mode detection temporarily disabled since ide-modes.c is not compiled 116 * - All DMA uses virt_to_phys conversions for DMA buffers and descriptor ptrs 117 * - Probably correct ide_dma_begin semantics in dmaproc now for ATAPI devices 118 * - Removed RESET_DMA when starting a new transfer - why was this necessary ? 119 * - Indentation fix 120 * 121 * 122 */ 123 124/* Regarding DMA: 125 * 126 * There are two forms of DMA - "DMA handshaking" between the interface and the drive, 127 * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's 128 * something built-in in the Etrax. However only some drives support the DMA-mode handshaking 129 * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the 130 * device can't do DMA handshaking for some stupid reason. We don't need to do that. 131 */ 132 133#undef REALLY_SLOW_IO /* most systems can safely undef this */ 134 135#include <linux/config.h> 136#include <linux/types.h> 137#include <linux/kernel.h> 138#include <linux/timer.h> 139#include <linux/mm.h> 140#include <linux/interrupt.h> 141#include <linux/delay.h> 142#include <linux/blkdev.h> 143#include <linux/hdreg.h> 144#include <linux/ide.h> 145#include <linux/init.h> 146 147#include <asm/io.h> 148#include <asm/svinto.h> 149#include <asm/dma.h> 150 151/* number of Etrax DMA descriptors */ 152#define MAX_DMA_DESCRS 64 153 154/* number of times to retry busy-flags when reading/writing IDE-registers 155 * this can't be too high because a hung harddisk might cause the watchdog 156 * to trigger (sometimes IN_BYTE and OUT_BYTE are called with irq's disabled) 157 */ 158 159#define IDE_REGISTER_TIMEOUT 300 160 161#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET 162/* address where the memory-mapped IDE reset bit lives, if used */ 163static volatile unsigned long *reset_addr; 164#endif 165 166#define LOWDB(x) 167#define D(x) 168 169void 170OUT_BYTE(unsigned char data, ide_ioreg_t reg) { 171 int timeleft; 172 LOWDB(printk("ob: data 0x%x, reg 0x%x\n", data, reg)); 173 174 /* note the lack of handling any timeouts. we stop waiting, but we don't 175 * really notify anybody. 176 */ 177 178 timeleft = IDE_REGISTER_TIMEOUT; 179 /* wait for busy flag */ 180 while(timeleft && (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy))) 181 timeleft--; 182 183 /* 184 * Fall through at a timeout, so the ongoing command will be 185 * aborted by the write below, which is expected to be a dummy 186 * command to the command register. This happens when a faulty 187 * drive times out on a command. See comment on timeout in 188 * IN_BYTE. 189 */ 190 if(!timeleft) 191 printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data); 192 193 *R_ATA_CTRL_DATA = reg | data; /* write data to the drive's register */ 194 195 timeleft = IDE_REGISTER_TIMEOUT; 196 /* wait for transmitter ready */ 197 while(timeleft && !(*R_ATA_STATUS_DATA & 198 IO_MASK(R_ATA_STATUS_DATA, tr_rdy))) 199 timeleft--; 200} 201 202unsigned char 203IN_BYTE(ide_ioreg_t reg) { 204 int status; 205 int timeleft; 206 207 timeleft = IDE_REGISTER_TIMEOUT; 208 /* wait for busy flag */ 209 while(timeleft && (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy))) 210 timeleft--; 211 212 if(!timeleft) { 213 /* 214 * If we're asked to read the status register, like for 215 * example when a command does not complete for an 216 * extended time, but the ATA interface is stuck in a 217 * busy state at the *ETRAX* ATA interface level (as has 218 * happened repeatedly with at least one bad disk), then 219 * the best thing to do is to pretend that we read 220 * "busy" in the status register, so the IDE driver will 221 * time-out, abort the ongoing command and perform a 222 * reset sequence. Note that the subsequent OUT_BYTE 223 * call will also timeout on busy, but as long as the 224 * write is still performed, everything will be fine. 225 */ 226 if ((reg & IO_MASK (R_ATA_CTRL_DATA, addr)) 227 == IO_FIELD (R_ATA_CTRL_DATA, addr, IDE_STATUS_OFFSET)) 228 return BUSY_STAT; 229 else 230 /* For other rare cases we assume 0 is good enough. */ 231 return 0; 232 } 233 234 *R_ATA_CTRL_DATA = reg | IO_STATE(R_ATA_CTRL_DATA, rw, read); /* read data */ 235 236 timeleft = IDE_REGISTER_TIMEOUT; 237 /* wait for available */ 238 while(timeleft && !((status = *R_ATA_STATUS_DATA) & 239 IO_MASK(R_ATA_STATUS_DATA, dav))) 240 timeleft--; 241 242 if(!timeleft) 243 return 0; 244 245 LOWDB(printk("inb: 0x%x from reg 0x%x\n", status & 0xff, reg)); 246 247 return (unsigned char)status; /* data was in the lower 16 bits in the status reg */ 248} 249 250/* PIO timing (in R_ATA_CONFIG) 251 * 252 * _____________________________ 253 * ADDRESS : ________/ 254 * 255 * _______________ 256 * DIOR : ____________/ \__________ 257 * 258 * _______________ 259 * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX 260 * 261 * 262 * DIOR is unbuffered while address and data is buffered. 263 * This creates two problems: 264 * 1. The DIOR pulse is to early (because it is unbuffered) 265 * 2. The rise time of DIOR is long 266 * 267 * There are at least three different plausible solutions 268 * 1. Use a pad capable of larger currents in Etrax 269 * 2. Use an external buffer 270 * 3. Make the strobe pulse longer 271 * 272 * Some of the strobe timings below are modified to compensate 273 * for this. This implies a slight performance decrease. 274 * 275 * THIS SHOULD NEVER BE CHANGED! 276 * 277 * TODO: Is this true for the latest LX boards still ? 278 */ 279 280#define ATA_DMA2_STROBE 4 281#define ATA_DMA2_HOLD 0 282#define ATA_DMA1_STROBE 4 283#define ATA_DMA1_HOLD 1 284#define ATA_DMA0_STROBE 12 285#define ATA_DMA0_HOLD 9 286#define ATA_PIO4_SETUP 1 287#define ATA_PIO4_STROBE 5 288#define ATA_PIO4_HOLD 0 289#define ATA_PIO3_SETUP 1 290#define ATA_PIO3_STROBE 5 291#define ATA_PIO3_HOLD 1 292#define ATA_PIO2_SETUP 1 293#define ATA_PIO2_STROBE 6 294#define ATA_PIO2_HOLD 2 295#define ATA_PIO1_SETUP 2 296#define ATA_PIO1_STROBE 11 297#define ATA_PIO1_HOLD 4 298#define ATA_PIO0_SETUP 4 299#define ATA_PIO0_STROBE 19 300#define ATA_PIO0_HOLD 4 301 302static int e100_dmaproc (ide_dma_action_t func, ide_drive_t *drive); 303static void e100_ideproc (ide_ide_action_t func, ide_drive_t *drive, 304 void *buffer, unsigned int length); 305 306/* 307 * good_dma_drives() lists the model names (from "hdparm -i") 308 * of drives which do not support mword2 DMA but which are 309 * known to work fine with this interface under Linux. 310 */ 311 312const char *good_dma_drives[] = {"Micropolis 2112A", 313 "CONNER CTMA 4000", 314 "CONNER CTT8000-A", 315 NULL}; 316 317static void tune_e100_ide(ide_drive_t *drive, byte pio) 318{ 319 unsigned long flags; 320 321 pio = 4; 322 /* pio = ide_get_best_pio_mode(drive, pio, 4, NULL); */ 323 324 save_flags(flags); 325 cli(); 326 327 /* set pio mode! */ 328 329 switch(pio) { 330 case 0: 331 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | 332 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) | 333 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) | 334 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO0_SETUP ) | 335 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO0_STROBE ) | 336 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO0_HOLD ) ); 337 break; 338 case 1: 339 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | 340 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) | 341 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) | 342 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO1_SETUP ) | 343 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO1_STROBE ) | 344 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO1_HOLD ) ); 345 break; 346 case 2: 347 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | 348 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) | 349 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) | 350 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO2_SETUP ) | 351 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO2_STROBE ) | 352 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO2_HOLD ) ); 353 break; 354 case 3: 355 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | 356 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) | 357 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) | 358 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO3_SETUP ) | 359 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO3_STROBE ) | 360 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO3_HOLD ) ); 361 break; 362 case 4: 363 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | 364 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) | 365 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) | 366 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO4_SETUP ) | 367 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) | 368 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO4_HOLD ) ); 369 break; 370 } 371 restore_flags(flags); 372} 373 374void __init 375init_e100_ide (void) 376{ 377 volatile unsigned int dummy; 378 int h; 379 380 printk("ide: ETRAX 100LX built-in ATA DMA controller\n"); 381 382 /* first fill in some stuff in the ide_hwifs fields */ 383 384 for(h = 0; h < MAX_HWIFS; h++) { 385 ide_hwif_t *hwif = &ide_hwifs[h]; 386 hwif->chipset = ide_etrax100; 387 hwif->tuneproc = &tune_e100_ide; 388 hwif->dmaproc = &e100_dmaproc; 389 hwif->ideproc = &e100_ideproc; 390 } 391 392 /* actually reset and configure the etrax100 ide/ata interface */ 393 394 *R_ATA_CTRL_DATA = 0; 395 *R_ATA_TRANSFER_CNT = 0; 396 *R_ATA_CONFIG = 0; 397 398 genconfig_shadow = (genconfig_shadow & 399 ~IO_MASK(R_GEN_CONFIG, dma2) & 400 ~IO_MASK(R_GEN_CONFIG, dma3) & 401 ~IO_MASK(R_GEN_CONFIG, ata)) | 402 ( IO_STATE( R_GEN_CONFIG, dma3, ata ) | 403 IO_STATE( R_GEN_CONFIG, dma2, ata ) | 404 IO_STATE( R_GEN_CONFIG, ata, select ) ); 405 406 *R_GEN_CONFIG = genconfig_shadow; 407 408 /* pull the chosen /reset-line low */ 409 410#ifdef CONFIG_ETRAX_IDE_G27_RESET 411 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, 0); 412#endif 413#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET 414 init_ioremap(); 415 REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 0); 416#endif 417#ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET 418 init_ioremap(); 419 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 0); 420#endif 421#ifdef CONFIG_ETRAX_IDE_PB7_RESET 422 port_pb_dir_shadow = port_pb_dir_shadow | 423 IO_STATE(R_PORT_PB_DIR, dir7, output); 424 *R_PORT_PB_DIR = port_pb_dir_shadow; 425 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, 1); 426#endif 427 428 /* wait some */ 429 430 udelay(25); 431 432 /* de-assert bus-reset */ 433 434#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET 435 REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 1); 436#endif 437#ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET 438 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 1); 439#endif 440#ifdef CONFIG_ETRAX_IDE_G27_RESET 441 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, 1); 442#endif 443 444 /* make a dummy read to set the ata controller in a proper state */ 445 dummy = *R_ATA_STATUS_DATA; 446 447 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | 448 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) | 449 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) | 450 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO4_SETUP ) | 451 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) | 452 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO4_HOLD ) ); 453 454 *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) | 455 IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) ); 456 457 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/ 458 459 *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) | 460 IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) | 461 IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) | 462 IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) ); 463 464 printk("ide: waiting %d seconds for drives to regain consciousness\n", 465 CONFIG_ETRAX_IDE_DELAY); 466 467 h = jiffies + (CONFIG_ETRAX_IDE_DELAY * HZ); 468 while(time_before(jiffies, h)) /* nothing */ ; 469 470 /* reset the dma channels we will use */ 471 472 RESET_DMA(ATA_TX_DMA_NBR); 473 RESET_DMA(ATA_RX_DMA_NBR); 474 WAIT_DMA(ATA_TX_DMA_NBR); 475 WAIT_DMA(ATA_RX_DMA_NBR); 476 477} 478 479static etrax_dma_descr mydescr; 480 481/* 482 * The following routines are mainly used by the ATAPI drivers. 483 * 484 * These routines will round up any request for an odd number of bytes, 485 * so if an odd bytecount is specified, be sure that there's at least one 486 * extra byte allocated for the buffer. 487 */ 488static void 489e100_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) 490{ 491 ide_ioreg_t data_reg = IDE_DATA_REG; 492 493 D(printk("atapi_input_bytes, dreg 0x%x, buffer 0x%x, count %d\n", 494 data_reg, buffer, bytecount)); 495 496 if(bytecount & 1) { 497 printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount); 498 bytecount++; /* to round off */ 499 } 500 501 /* make sure the DMA channel is available */ 502 RESET_DMA(ATA_RX_DMA_NBR); 503 WAIT_DMA(ATA_RX_DMA_NBR); 504 505 /* setup DMA descriptor */ 506 507 mydescr.sw_len = bytecount; 508 mydescr.ctrl = d_eol; 509 mydescr.buf = virt_to_phys(buffer); 510 511 /* start the dma channel */ 512 513 *R_DMA_CH3_FIRST = virt_to_phys(&mydescr); 514 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start); 515 516 /* initiate a multi word dma read using PIO handshaking */ 517 518 *R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1); 519 520 *R_ATA_CTRL_DATA = data_reg | 521 IO_STATE(R_ATA_CTRL_DATA, rw, read) | 522 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) | 523 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) | 524 IO_STATE(R_ATA_CTRL_DATA, multi, on) | 525 IO_STATE(R_ATA_CTRL_DATA, dma_size, word); 526 527 /* wait for completion */ 528 529 LED_DISK_READ(1); 530 WAIT_DMA(ATA_RX_DMA_NBR); 531 LED_DISK_READ(0); 532 533} 534 535static void 536e100_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) 537{ 538 ide_ioreg_t data_reg = IDE_DATA_REG; 539 540 D(printk("atapi_output_bytes, dreg 0x%x, buffer 0x%x, count %d\n", 541 data_reg, buffer, bytecount)); 542 543 if(bytecount & 1) { 544 printk("odd bytecount %d in atapi_out_bytes!\n", bytecount); 545 bytecount++; 546 } 547 548 /* make sure the DMA channel is available */ 549 RESET_DMA(ATA_TX_DMA_NBR); 550 WAIT_DMA(ATA_TX_DMA_NBR); 551 552 /* setup DMA descriptor */ 553 554 mydescr.sw_len = bytecount; 555 mydescr.ctrl = d_eol; 556 mydescr.buf = virt_to_phys(buffer); 557 558 /* start the dma channel */ 559 560 *R_DMA_CH2_FIRST = virt_to_phys(&mydescr); 561 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start); 562 563 /* initiate a multi word dma write using PIO handshaking */ 564 565 *R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1); 566 567 *R_ATA_CTRL_DATA = data_reg | 568 IO_STATE(R_ATA_CTRL_DATA, rw, write) | 569 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) | 570 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) | 571 IO_STATE(R_ATA_CTRL_DATA, multi, on) | 572 IO_STATE(R_ATA_CTRL_DATA, dma_size, word); 573 574 /* wait for completion */ 575 576 LED_DISK_WRITE(1); 577 WAIT_DMA(ATA_TX_DMA_NBR); 578 LED_DISK_WRITE(0); 579 580 581} 582 583/* 584 * This is used for most PIO data transfers *from* the IDE interface 585 */ 586static void 587e100_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount) 588{ 589 e100_atapi_input_bytes(drive, buffer, wcount << 2); 590} 591 592/* 593 * This is used for most PIO data transfers *to* the IDE interface 594 */ 595static void 596e100_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount) 597{ 598 e100_atapi_output_bytes(drive, buffer, wcount << 2); 599} 600 601/* 602 * The multiplexor for ide_xxxput_data and atapi calls 603 */ 604static void 605e100_ideproc (ide_ide_action_t func, ide_drive_t *drive, 606 void *buffer, unsigned int length) 607{ 608 switch (func) { 609 case ideproc_ide_input_data: 610 e100_ide_input_data(drive, buffer, length); 611 break; 612 case ideproc_ide_output_data: 613 e100_ide_input_data(drive, buffer, length); 614 break; 615 case ideproc_atapi_input_bytes: 616 e100_atapi_input_bytes(drive, buffer, length); 617 break; 618 case ideproc_atapi_output_bytes: 619 e100_atapi_output_bytes(drive, buffer, length); 620 break; 621 default: 622 printk("e100_ideproc: unsupported func %d!\n", func); 623 break; 624 } 625} 626 627/* we only have one DMA channel on the chip for ATA, so we can keep these statically */ 628static etrax_dma_descr ata_descrs[MAX_DMA_DESCRS]; 629static unsigned int ata_tot_size; 630 631/* 632 * e100_ide_build_dmatable() prepares a dma request. 633 * Returns 0 if all went okay, returns 1 otherwise. 634 */ 635static int e100_ide_build_dmatable (ide_drive_t *drive) 636{ 637 struct request *rq = HWGROUP(drive)->rq; 638 struct buffer_head *bh = rq->bh; 639 unsigned long size, addr; 640 unsigned int count = 0; 641 642 ata_tot_size = 0; 643 644 do { 645 /* 646 * Determine addr and size of next buffer area. We assume that 647 * individual virtual buffers are always composed linearly in 648 * physical memory. For example, we assume that any 8kB buffer 649 * is always composed of two adjacent physical 4kB pages rather 650 * than two possibly non-adjacent physical 4kB pages. 651 */ 652 if (bh == NULL) { /* paging and tape requests have (rq->bh == NULL) */ 653 addr = virt_to_phys (rq->buffer); 654 size = rq->nr_sectors << 9; 655 } else { 656 /* group sequential buffers into one large buffer */ 657 addr = virt_to_phys (bh->b_data); 658 size = bh->b_size; 659 while ((bh = bh->b_reqnext) != NULL) { 660 if ((addr + size) != virt_to_phys (bh->b_data)) 661 break; 662 size += bh->b_size; 663 } 664 } 665 666 /* did we run out of descriptors? */ 667 668 if(count >= MAX_DMA_DESCRS) { 669 printk("%s: too few DMA descriptors\n", drive->name); 670 return 1; 671 } 672 673 /* however, this case is more difficult - R_ATA_TRANSFER_CNT cannot be more 674 than 65536 words per transfer, so in that case we need to either 675 1) use a DMA interrupt to re-trigger R_ATA_TRANSFER_CNT and continue with 676 the descriptors, or 677 2) simply do the request here, and get dma_intr to only ide_end_request on 678 those blocks that were actually set-up for transfer. 679 */ 680 681 if(ata_tot_size + size > 131072) { 682 printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, size); 683 return 1; 684 } 685 686 /* If size > 65536 it has to be splitted into new descriptors. Since we don't handle 687 size > 131072 only one split is necessary */ 688 689 if(size > 65536) { 690 /* ok we want to do IO at addr, size bytes. set up a new descriptor entry */ 691 ata_descrs[count].sw_len = 0; /* 0 means 65536, this is a 16-bit field */ 692 ata_descrs[count].ctrl = 0; 693 ata_descrs[count].buf = addr; 694 ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]); 695 count++; 696 ata_tot_size += 65536; 697 /* size and addr should refere to not handled data */ 698 size -= 65536; 699 addr += 65536; 700 } 701 /* ok we want to do IO at addr, size bytes. set up a new descriptor entry */ 702 if(size == 65536) { 703 ata_descrs[count].sw_len = 0; /* 0 means 65536, this is a 16-bit field */ 704 } else { 705 ata_descrs[count].sw_len = size; 706 } 707 ata_descrs[count].ctrl = 0; 708 ata_descrs[count].buf = addr; 709 ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]); 710 count++; 711 ata_tot_size += size; 712 713 } while (bh != NULL); 714 715 if (count) { 716 /* set the end-of-list flag on the last descriptor */ 717 ata_descrs[count - 1].ctrl |= d_eol; 718 /* return and say all is ok */ 719 return 0; 720 } 721 722 printk("%s: empty DMA table?\n", drive->name); 723 return 1; /* let the PIO routines handle this weirdness */ 724} 725 726static int config_drive_for_dma (ide_drive_t *drive) 727{ 728 const char **list; 729 struct hd_driveid *id = drive->id; 730 731 if (id && (id->capability & 1)) { 732 /* Enable DMA on any drive that supports mword2 DMA */ 733 if ((id->field_valid & 2) && (id->dma_mword & 0x404) == 0x404) { 734 drive->using_dma = 1; 735 return 0; /* DMA enabled */ 736 } 737 738 /* Consult the list of known "good" drives */ 739 list = good_dma_drives; 740 while (*list) { 741 if (!strcmp(*list++,id->model)) { 742 drive->using_dma = 1; 743 return 0; /* DMA enabled */ 744 } 745 } 746 } 747 return 1; /* DMA not enabled */ 748} 749 750/* 751 * etrax_dma_intr() is the handler for disk read/write DMA interrupts 752 */ 753static ide_startstop_t etrax_dma_intr (ide_drive_t *drive) 754{ 755 int i, dma_stat; 756 byte stat; 757 758 LED_DISK_READ(0); 759 LED_DISK_WRITE(0); 760 761 dma_stat = HWIF(drive)->dmaproc(ide_dma_end, drive); 762 stat = GET_STAT(); /* get drive status */ 763 if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { 764 if (!dma_stat) { 765 struct request *rq; 766 rq = HWGROUP(drive)->rq; 767 for (i = rq->nr_sectors; i > 0;) { 768 i -= rq->current_nr_sectors; 769 ide_end_request(1, HWGROUP(drive)); 770 } 771 return ide_stopped; 772 } 773 printk("%s: bad DMA status\n", drive->name); 774 } 775 return ide_error(drive, "dma_intr", stat); 776} 777 778/* 779 * e100_dmaproc() initiates/aborts DMA read/write operations on a drive. 780 * 781 * The caller is assumed to have selected the drive and programmed the drive's 782 * sector address using CHS or LBA. All that remains is to prepare for DMA 783 * and then issue the actual read/write DMA/PIO command to the drive. 784 * 785 * For ATAPI devices, we just prepare for DMA and return. The caller should 786 * then issue the packet command to the drive and call us again with 787 * ide_dma_begin afterwards. 788 * 789 * Returns 0 if all went well. 790 * Returns 1 if DMA read/write could not be started, in which case 791 * the caller should revert to PIO for the current request. 792 */ 793 794static int e100_dmaproc (ide_dma_action_t func, ide_drive_t *drive) 795{ 796 static unsigned int reading; /* static to support ide_dma_begin semantics */ 797 int atapi = 0; 798 799 D(printk("e100_dmaproc func %d\n", func)); 800 801 switch (func) { 802 case ide_dma_verbose: 803 return 0; 804 case ide_dma_check: 805 return config_drive_for_dma (drive); 806 case ide_dma_off: 807 case ide_dma_off_quietly: 808 /* ok.. we don't really need to do anything I think. */ 809 return 0; 810 case ide_dma_write: 811 reading = 0; 812 break; 813 case ide_dma_read: 814 reading = 1; 815 break; 816 case ide_dma_begin: 817 /* begin DMA, used by ATAPI devices which want to issue the 818 * appropriate IDE command themselves. 819 * 820 * they have already called ide_dma_read/write to set the 821 * static reading flag, now they call ide_dma_begin to do 822 * the real stuff. we tell our code below not to issue 823 * any IDE commands itself and jump into it. 824 */ 825 atapi++; 826 goto dma_begin; 827 case ide_dma_end: /* returns 1 on error, 0 otherwise */ 828 /* TODO: check if something went wrong with the DMA */ 829 return 0; 830 831 default: 832 printk("e100_dmaproc: unsupported func %d\n", func); 833 return 1; 834 } 835 836 /* ATAPI-devices (not disks) first call ide_dma_read/write to set the direction 837 * then they call ide_dma_begin after they have issued the appropriate drive command 838 * themselves to actually start the chipset DMA. so we just return here if we're 839 * not a diskdrive. 840 */ 841 842 if (drive->media != ide_disk) 843 return 0; 844 845 dma_begin: 846 847 if(reading) { 848 849 RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */ 850 WAIT_DMA(ATA_RX_DMA_NBR); 851 852 /* set up the Etrax DMA descriptors */ 853 854 if(e100_ide_build_dmatable (drive)) 855 return 1; 856 857 if(!atapi) { 858 /* set the irq handler which will finish the request when DMA is done */ 859 860 ide_set_handler(drive, &etrax_dma_intr, WAIT_CMD, NULL); 861 862 /* issue cmd to drive */ 863 864 OUT_BYTE(WIN_READDMA, IDE_COMMAND_REG); 865 } 866 867 /* begin DMA */ 868 869 /* need to do this before RX DMA due to a chip bug 870 * it is enough to just flush the part of the cache that 871 * corresponds to the buffers we start, but since HD transfers 872 * usually are more than 8 kB, it is easier to optimize for the 873 * normal case and just flush the entire cache. its the only 874 * way to be sure! (OB movie quote) 875 */ 876 flush_etrax_cache(); 877 *R_DMA_CH3_FIRST = virt_to_phys(ata_descrs); 878 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start); 879 880 /* initiate a multi word dma read using DMA handshaking */ 881 882 *R_ATA_TRANSFER_CNT = 883 IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1); 884 885 *R_ATA_CTRL_DATA = 886 IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) | 887 IO_STATE(R_ATA_CTRL_DATA, rw, read) | 888 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) | 889 IO_STATE(R_ATA_CTRL_DATA, handsh, dma) | 890 IO_STATE(R_ATA_CTRL_DATA, multi, on) | 891 IO_STATE(R_ATA_CTRL_DATA, dma_size, word); 892 893 LED_DISK_READ(1); 894 895 D(printk("dma read of %d bytes.\n", ata_tot_size)); 896 897 } else { 898 /* writing */ 899 900 RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */ 901 WAIT_DMA(ATA_TX_DMA_NBR); 902 903 /* set up the Etrax DMA descriptors */ 904 905 if(e100_ide_build_dmatable (drive)) 906 return 1; 907 908 if(!atapi) { 909 /* set the irq handler which will finish the request when DMA is done */ 910 911 ide_set_handler(drive, &etrax_dma_intr, WAIT_CMD, NULL); 912 913 /* issue cmd to drive */ 914 915 OUT_BYTE(WIN_WRITEDMA, IDE_COMMAND_REG); 916 } 917 918 /* begin DMA */ 919 920 *R_DMA_CH2_FIRST = virt_to_phys(ata_descrs); 921 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start); 922 923 /* initiate a multi word dma write using DMA handshaking */ 924 925 *R_ATA_TRANSFER_CNT = 926 IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1); 927 928 *R_ATA_CTRL_DATA = 929 IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) | 930 IO_STATE(R_ATA_CTRL_DATA, rw, write) | 931 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) | 932 IO_STATE(R_ATA_CTRL_DATA, handsh, dma) | 933 IO_STATE(R_ATA_CTRL_DATA, multi, on) | 934 IO_STATE(R_ATA_CTRL_DATA, dma_size, word); 935 936 LED_DISK_WRITE(1); 937 938 D(printk("dma write of %d bytes.\n", ata_tot_size)); 939 } 940 941 /* DMA started successfully */ 942 return 0; 943} 944 945/* ide.c calls this, but we don't need to do anything particular */ 946 947int ide_release_dma (ide_hwif_t *hwif) 948{ 949 return 1; 950} 951