1/* 2 * linux/arch/alpha/kernel/sys_nautilus.c 3 * 4 * Copyright (C) 1995 David A Rusling 5 * Copyright (C) 1998 Richard Henderson 6 * Copyright (C) 1999 Alpha Processor, Inc., 7 * (David Daniel, Stig Telfer, Soohoon Lee) 8 * 9 * Code supporting NAUTILUS systems. 10 * 11 * 12 * NAUTILUS has the following I/O features: 13 * 14 * a) Driven by AMD 751 aka IRONGATE (northbridge): 15 * 4 PCI slots 16 * 1 AGP slot 17 * 18 * b) Driven by ALI M1543C (southbridge) 19 * 2 ISA slots 20 * 2 IDE connectors 21 * 1 dual drive capable FDD controller 22 * 2 serial ports 23 * 1 ECP/EPP/SP parallel port 24 * 2 USB ports 25 */ 26 27#include <linux/kernel.h> 28#include <linux/types.h> 29#include <linux/mm.h> 30#include <linux/sched.h> 31#include <linux/pci.h> 32#include <linux/init.h> 33#include <linux/reboot.h> 34 35#include <asm/ptrace.h> 36#include <asm/system.h> 37#include <asm/dma.h> 38#include <asm/irq.h> 39#include <asm/bitops.h> 40#include <asm/mmu_context.h> 41#include <asm/io.h> 42#include <asm/pci.h> 43#include <asm/pgtable.h> 44#include <asm/core_irongate.h> 45#include <asm/hwrpb.h> 46 47#include "proto.h" 48#include "irq_impl.h" 49#include "pci_impl.h" 50#include "machvec_impl.h" 51 52 53static void __init 54nautilus_init_irq(void) 55{ 56 if (alpha_using_srm) { 57 alpha_mv.device_interrupt = srm_device_interrupt; 58 } 59 60 init_i8259a_irqs(); 61 common_init_isa_dma(); 62} 63 64static int __init 65nautilus_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 66{ 67 /* Preserve the IRQ set up by the console. */ 68 69 u8 irq; 70 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 71 return irq; 72} 73 74void 75nautilus_kill_arch(int mode) 76{ 77 switch (mode) { 78 case LINUX_REBOOT_CMD_RESTART: 79 if (! alpha_using_srm) { 80 u8 t8; 81 pcibios_read_config_byte(0, 0x38, 0x43, &t8); 82 pcibios_write_config_byte(0, 0x38, 0x43, t8 | 0x80); 83 outb(1, 0x92); 84 outb(0, 0x92); 85 /* NOTREACHED */ 86 } 87 break; 88 89 case LINUX_REBOOT_CMD_POWER_OFF: 90 { 91 u32 pmuport; 92 pcibios_read_config_dword(0, 0x88, 0x10, &pmuport); 93 pmuport &= 0xfffe; 94 outl(0xffff, pmuport); /* clear pending events */ 95 outw(0x2000, pmuport+4); /* power off */ 96 /* NOTREACHED */ 97 } 98 break; 99 } 100} 101 102/* Machine check handler code 103 * 104 * Perform analysis of a machine check that was triggered by the EV6 105 * CPU's fault-detection mechanism. 106 */ 107 108/* IPR structures for EV6, containing the necessary data for the 109 * machine check handler to unpick the logout frame 110 */ 111 112/* I_STAT */ 113 114#define EV6__I_STAT__PAR ( 1 << 29 ) 115 116/* MM_STAT */ 117 118#define EV6__MM_STAT__DC_TAG_PERR ( 1 << 10 ) 119 120/* DC_STAT */ 121 122#define EV6__DC_STAT__SEO ( 1 << 4 ) 123#define EV6__DC_STAT__ECC_ERR_LD ( 1 << 3 ) 124#define EV6__DC_STAT__ECC_ERR_ST ( 1 << 2 ) 125#define EV6__DC_STAT__TPERR_P1 ( 1 << 1 ) 126#define EV6__DC_STAT__TPERR_P0 ( 1 ) 127 128/* C_STAT */ 129 130#define EV6__C_STAT__BC_PERR ( 0x01 ) 131#define EV6__C_STAT__DC_PERR ( 0x02 ) 132#define EV6__C_STAT__DSTREAM_MEM_ERR ( 0x03 ) 133#define EV6__C_STAT__DSTREAM_BC_ERR ( 0x04 ) 134#define EV6__C_STAT__DSTREAM_DC_ERR ( 0x05 ) 135#define EV6__C_STAT__PROBE_BC_ERR0 ( 0x06 ) 136#define EV6__C_STAT__PROBE_BC_ERR1 ( 0x07 ) 137#define EV6__C_STAT__ISTREAM_MEM_ERR ( 0x0B ) 138#define EV6__C_STAT__ISTREAM_BC_ERR ( 0x0C ) 139#define EV6__C_STAT__DSTREAM_MEM_DBL ( 0x13 ) 140#define EV6__C_STAT__DSTREAM_BC_DBL ( 0x14 ) 141#define EV6__C_STAT__ISTREAM_MEM_DBL ( 0x1B ) 142#define EV6__C_STAT__ISTREAM_BC_DBL ( 0x1C ) 143 144 145/* Take the two syndromes from the CBOX error chain and convert them 146 * into a bit number. */ 147 148/* NOTE - since I don't know of any difference between C0 and C1 I 149 just ignore C1, since in all cases I've seen so far they are 150 identical. */ 151 152static const unsigned char ev6_bit_to_syndrome[72] = 153{ 154 0xce, 0xcb, 0xd3, 0xd5, 0xd6, 0xd9, 0xda, 0xdc, /* 0 */ 155 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c, 0x31, 0x34, /* 8 */ 156 0x0e, 0x0b, 0x13, 0x15, 0x16, 0x19, 0x1a, 0x1c, /* 16 */ 157 0xe3, 0xe5, 0xe6, 0xe9, 0xea, 0xec, 0xf1, 0xf4, /* 24 */ 158 0x4f, 0x4a, 0x52, 0x54, 0x57, 0x58, 0x5b, 0x5d, /* 32 */ 159 0xa2, 0xa4, 0xa7, 0xa8, 0xab, 0xad, 0xb0, 0xb5, /* 40 */ 160 0x8f, 0x8a, 0x92, 0x94, 0x97, 0x98, 0x9b, 0x9d, /* 48 */ 161 0x62, 0x64, 0x67, 0x68, 0x6b, 0x6d, 0x70, 0x75, /* 56 */ 162 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 /* 64 */ 163}; 164 165 166static int ev6_syn2bit(unsigned long c0, unsigned long c1) 167{ 168 int bit; 169 170 for (bit = 0; bit < 72; bit++) 171 if (ev6_bit_to_syndrome[bit] == c0) return bit; 172 for (bit = 0; bit < 72; bit++) 173 if (ev6_bit_to_syndrome[bit] == c1) return bit + 64; 174 175 return -1; /* not found */ 176} 177 178 179/* Single bit ECC errors are categorized here. */ 180 181static const char *interr = ""; 182static const char *slotb = ""; 183static const char *membus = ""; 184 185static void 186ev6_crd_interp(char *interp, struct el_common_EV6_mcheck * L) 187{ 188 /* Icache data or tag parity error. */ 189 if (L->I_STAT & EV6__I_STAT__PAR) { 190 sprintf(interp, "%s: I_STAT[PAR]\n " 191 "Icache data or tag parity error", interr); 192 return; 193 } 194 195 /* Dcache tag parity error (on issue) (DFAULT). */ 196 if (L->MM_STAT & EV6__MM_STAT__DC_TAG_PERR) { 197 sprintf(interp, "%s: MM_STAT[DC_TAG_PERR]\n " 198 "Dcache tag parity error(on issue)", interr); 199 return; 200 } 201 202 /* Errors relating to D-stream set non-zero DC_STAT. 203 Mask CRD bits. */ 204 switch (L->DC_STAT & (EV6__DC_STAT__ECC_ERR_ST 205 | EV6__DC_STAT__ECC_ERR_LD)) { 206 case EV6__DC_STAT__ECC_ERR_ST: 207 /* Dcache single-bit ECC error on small store */ 208 sprintf(interp, "%s: DC_STAT[ECC_ERR_ST]\n " 209 "Dcache single-bit ECC error on small store", interr); 210 return; 211 212 case EV6__DC_STAT__ECC_ERR_LD: 213 switch (L->C_STAT) { 214 case 0: 215 /* Dcache single-bit error on speculative load */ 216 /* Bcache victim read on Dcache/Bcache miss */ 217 sprintf(interp, "%s: DC_STAT[ECC_ERR_LD] C_STAT=0\n " 218 "Dcache single-bit ECC error on speculative load", 219 slotb); 220 return; 221 222 case EV6__C_STAT__DSTREAM_DC_ERR: 223 /* Dcache single bit error on load */ 224 sprintf(interp, "%s: DC_STAT[ECC_ERR_LD] C_STAT[DSTREAM_DC_ERR]\n" 225 " Dcache single-bit ECC error on speculative load, bit %d", 226 interr, ev6_syn2bit(L->DC0_SYNDROME, L->DC1_SYNDROME)); 227 return; 228 229 case EV6__C_STAT__DSTREAM_BC_ERR: 230 /* Bcache single-bit error on Dcache fill */ 231 sprintf(interp, "%s: DC_STAT[ECC_ERR_LD] C_STAT[DSTREAM_BC_ERR]\n" 232 " Bcache single-bit error on Dcache fill, bit %d", 233 slotb, ev6_syn2bit(L->DC0_SYNDROME, L->DC1_SYNDROME)); 234 return; 235 236 case EV6__C_STAT__DSTREAM_MEM_ERR: 237 /* Memory single-bit error on Dcache fill */ 238 sprintf(interp, "%s (to Dcache): DC_STAT[ECC_ERR_LD] " 239 "C_STAT[DSTREAM_MEM_ERR]\n " 240 "Memory single-bit error on Dcache fill, " 241 "Address 0x%lX, bit %d", 242 membus, L->C_ADDR, ev6_syn2bit(L->DC0_SYNDROME, 243 L->DC1_SYNDROME)); 244 return; 245 } 246 } 247 248 /* I-stream, other misc errors go on C_STAT alone */ 249 switch (L->C_STAT) { 250 case EV6__C_STAT__ISTREAM_BC_ERR: 251 /* Bcache single-bit error on Icache fill (also MCHK) */ 252 sprintf(interp, "%s: C_STAT[ISTREAM_BC_ERR]\n " 253 "Bcache single-bit error on Icache fill, bit %d", 254 slotb, ev6_syn2bit(L->DC0_SYNDROME, L->DC1_SYNDROME)); 255 return; 256 257 case EV6__C_STAT__ISTREAM_MEM_ERR: 258 /* Memory single-bit error on Icache fill (also MCHK) */ 259 sprintf(interp, "%s : C_STATISTREAM_MEM_ERR]\n " 260 "Memory single-bit error on Icache fill " 261 "addr 0x%lX, bit %d", 262 membus, L->C_ADDR, ev6_syn2bit(L->DC0_SYNDROME, 263 L->DC1_SYNDROME)); 264 return; 265 266 case EV6__C_STAT__PROBE_BC_ERR0: 267 case EV6__C_STAT__PROBE_BC_ERR1: 268 /* Bcache single-bit error on a probe hit */ 269 sprintf(interp, "%s: C_STAT[PROBE_BC_ERR]\n " 270 "Bcache single-bit error on a probe hit, " 271 "addr 0x%lx, bit %d", 272 slotb, L->C_ADDR, ev6_syn2bit(L->DC0_SYNDROME, 273 L->DC1_SYNDROME)); 274 return; 275 } 276} 277 278static void 279ev6_mchk_interp(char *interp, struct el_common_EV6_mcheck * L) 280{ 281 /* Machine check errors described by DC_STAT */ 282 switch (L->DC_STAT) { 283 case EV6__DC_STAT__TPERR_P0: 284 case EV6__DC_STAT__TPERR_P1: 285 /* Dcache tag parity error (on retry) */ 286 sprintf(interp, "%s: DC_STAT[TPERR_P0|TPERR_P1]\n " 287 "Dcache tag parity error(on retry)", interr); 288 return; 289 290 case EV6__DC_STAT__SEO: 291 /* Dcache second error on store */ 292 sprintf(interp, "%s: DC_STAT[SEO]\n " 293 "Dcache second error during mcheck", interr); 294 return; 295 } 296 297 /* Machine check errors described by C_STAT */ 298 switch (L->C_STAT) { 299 case EV6__C_STAT__DC_PERR: 300 /* Dcache duplicate tag parity error */ 301 sprintf(interp, "%s: C_STAT[DC_PERR]\n " 302 "Dcache duplicate tag parity error at 0x%lX", 303 interr, L->C_ADDR); 304 return; 305 306 case EV6__C_STAT__BC_PERR: 307 /* Bcache tag parity error */ 308 sprintf(interp, "%s: C_STAT[BC_PERR]\n " 309 "Bcache tag parity error at 0x%lX", 310 slotb, L->C_ADDR); 311 return; 312 313 case EV6__C_STAT__ISTREAM_BC_ERR: 314 /* Bcache single-bit error on Icache fill (also CRD) */ 315 sprintf(interp, "%s: C_STAT[ISTREAM_BC_ERR]\n " 316 "Bcache single-bit error on Icache fill 0x%lX bit %d", 317 slotb, L->C_ADDR, 318 ev6_syn2bit(L->DC0_SYNDROME, L->DC1_SYNDROME)); 319 return; 320 321 322 case EV6__C_STAT__ISTREAM_MEM_ERR: 323 /* Memory single-bit error on Icache fill (also CRD) */ 324 sprintf(interp, "%s: C_STAT[ISTREAM_MEM_ERR]\n " 325 "Memory single-bit error on Icache fill 0x%lX, bit %d", 326 membus, L->C_ADDR, 327 ev6_syn2bit(L->DC0_SYNDROME, L->DC1_SYNDROME)); 328 return; 329 330 331 case EV6__C_STAT__ISTREAM_BC_DBL: 332 /* Bcache double-bit error on Icache fill */ 333 sprintf(interp, "%s: C_STAT[ISTREAM_BC_DBL]\n " 334 "Bcache double-bit error on Icache fill at 0x%lX", 335 slotb, L->C_ADDR); 336 return; 337 case EV6__C_STAT__DSTREAM_BC_DBL: 338 /* Bcache double-bit error on Dcache fill */ 339 sprintf(interp, "%s: C_STAT[DSTREAM_BC_DBL]\n " 340 "Bcache double-bit error on Dcache fill at 0x%lX", 341 slotb, L->C_ADDR); 342 return; 343 344 case EV6__C_STAT__ISTREAM_MEM_DBL: 345 /* Memory double-bit error on Icache fill */ 346 sprintf(interp, "%s: C_STAT[ISTREAM_MEM_DBL]\n " 347 "Memory double-bit error on Icache fill at 0x%lX", 348 membus, L->C_ADDR); 349 return; 350 351 case EV6__C_STAT__DSTREAM_MEM_DBL: 352 /* Memory double-bit error on Dcache fill */ 353 sprintf(interp, "%s: C_STAT[DSTREAM_MEM_DBL]\n " 354 "Memory double-bit error on Dcache fill at 0x%lX", 355 membus, L->C_ADDR); 356 return; 357 } 358} 359 360static void 361ev6_cpu_machine_check(unsigned long vector, struct el_common_EV6_mcheck *L, 362 struct pt_regs *regs) 363{ 364 char interp[80]; 365 366 /* This is verbose and looks intimidating. Should it be printed for 367 corrected (CRD) machine checks? */ 368 369 printk(KERN_CRIT "PALcode logout frame: " 370 "MCHK_Code %d " 371 "MCHK_Frame_Rev %d\n" 372 "I_STAT %016lx " 373 "DC_STAT %016lx " 374 "C_ADDR %016lx\n" 375 "SYND1 %016lx " 376 "SYND0 %016lx " 377 "C_STAT %016lx\n" 378 "C_STS %016lx " 379 "RES %016lx " 380 "EXC_ADDR%016lx\n" 381 "IER_CM %016lx " 382 "ISUM %016lx " 383 "MM_STAT %016lx\n" 384 "PALBASE %016lx " 385 "I_CTL %016lx " 386 "PCTX %016lx\n" 387 "CPU registers: " 388 "PC %016lx " 389 "Return %016lx\n", 390 L->MCHK_Code, L->MCHK_Frame_Rev, L->I_STAT, L->DC_STAT, 391 L->C_ADDR, L->DC1_SYNDROME, L->DC0_SYNDROME, L->C_STAT, 392 L->C_STS, L->RESERVED0, L->EXC_ADDR, L->IER_CM, L->ISUM, 393 L->MM_STAT, L->PAL_BASE, L->I_CTL, L->PCTX, 394 regs->pc, regs->r26); 395 396 /* Attempt an interpretation on the meanings of the fields above. */ 397 sprintf(interp, "No interpretation available!" ); 398 if (vector == SCB_Q_PROCERR) 399 ev6_crd_interp(interp, L); 400 else if (vector == SCB_Q_PROCMCHK) 401 ev6_mchk_interp(interp, L); 402 403 printk(KERN_CRIT "interpretation: %s\n\n", interp); 404} 405 406 407/* Perform analysis of a machine check that arrived from the system (NMI) */ 408 409static void 410naut_sys_machine_check(unsigned long vector, unsigned long la_ptr, 411 struct pt_regs *regs) 412{ 413 printk("xtime %lx\n", CURRENT_TIME); 414 printk("PC %lx RA %lx\n", regs->pc, regs->r26); 415 irongate_pci_clr_err(); 416} 417 418/* Machine checks can come from two sources - those on the CPU and those 419 in the system. They are analysed separately but all starts here. */ 420 421void 422nautilus_machine_check(unsigned long vector, unsigned long la_ptr, 423 struct pt_regs *regs) 424{ 425 char *mchk_class; 426 unsigned cpu_analysis=0, sys_analysis=0; 427 428 /* Now for some analysis. Machine checks fall into two classes -- 429 those picked up by the system, and those picked up by the CPU. 430 Add to that the two levels of severity - correctable or not. */ 431 432 if (vector == SCB_Q_SYSMCHK 433 && ((IRONGATE0->dramms & 0x300) == 0x300)) { 434 unsigned long nmi_ctl; 435 436 /* Clear ALI NMI */ 437 nmi_ctl = inb(0x61); 438 nmi_ctl |= 0x0c; 439 outb(nmi_ctl, 0x61); 440 nmi_ctl &= ~0x0c; 441 outb(nmi_ctl, 0x61); 442 443 /* Write again clears error bits. */ 444 IRONGATE0->stat_cmd = IRONGATE0->stat_cmd & ~0x100; 445 mb(); 446 IRONGATE0->stat_cmd; 447 448 /* Write again clears error bits. */ 449 IRONGATE0->dramms = IRONGATE0->dramms; 450 mb(); 451 IRONGATE0->dramms; 452 453 draina(); 454 wrmces(0x7); 455 mb(); 456 return; 457 } 458 459 switch (vector) { 460 case SCB_Q_SYSERR: 461 mchk_class = "Correctable System Machine Check (NMI)"; 462 sys_analysis = 1; 463 break; 464 case SCB_Q_SYSMCHK: 465 mchk_class = "Fatal System Machine Check (NMI)"; 466 sys_analysis = 1; 467 break; 468 469 case SCB_Q_PROCERR: 470 mchk_class = "Correctable Processor Machine Check"; 471 cpu_analysis = 1; 472 break; 473 case SCB_Q_PROCMCHK: 474 mchk_class = "Fatal Processor Machine Check"; 475 cpu_analysis = 1; 476 break; 477 478 default: 479 mchk_class = "Unknown vector!"; 480 break; 481 } 482 483 printk(KERN_CRIT "NAUTILUS Machine check 0x%lx [%s]\n", 484 vector, mchk_class); 485 486 if (cpu_analysis) 487 ev6_cpu_machine_check(vector, 488 (struct el_common_EV6_mcheck *)la_ptr, 489 regs); 490 if (sys_analysis) 491 naut_sys_machine_check(vector, la_ptr, regs); 492 493 /* Tell the PALcode to clear the machine check */ 494 draina(); 495 wrmces(0x7); 496 mb(); 497} 498 499 500 501/* 502 * The System Vectors 503 */ 504 505struct alpha_machine_vector nautilus_mv __initmv = { 506 vector_name: "Nautilus", 507 DO_EV6_MMU, 508 DO_DEFAULT_RTC, 509 DO_IRONGATE_IO, 510 DO_IRONGATE_BUS, 511 machine_check: nautilus_machine_check, 512 max_dma_address: ALPHA_NAUTILUS_MAX_DMA_ADDRESS, 513 min_io_address: DEFAULT_IO_BASE, 514 min_mem_address: IRONGATE_DEFAULT_MEM_BASE, 515 516 nr_irqs: 16, 517 device_interrupt: isa_device_interrupt, 518 519 init_arch: irongate_init_arch, 520 init_irq: nautilus_init_irq, 521 init_rtc: common_init_rtc, 522 init_pci: common_init_pci, 523 kill_arch: nautilus_kill_arch, 524 pci_map_irq: nautilus_map_irq, 525 pci_swizzle: common_swizzle, 526}; 527ALIAS_MV(nautilus) 528