1/* 2 * linux/arch/alpha/kernel/pci.c 3 * 4 * Extruded from code written by 5 * Dave Rusling (david.rusling@reo.mts.dec.com) 6 * David Mosberger (davidm@cs.arizona.edu) 7 */ 8 9/* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */ 10 11/* 12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 13 * PCI-PCI bridges cleanup 14 */ 15 16#include <linux/string.h> 17#include <linux/pci.h> 18#include <linux/init.h> 19#include <linux/ioport.h> 20#include <linux/kernel.h> 21#include <linux/bootmem.h> 22#include <asm/machvec.h> 23 24#include "proto.h" 25#include "pci_impl.h" 26 27 28/* 29 * Some string constants used by the various core logics. 30 */ 31 32const char *const pci_io_names[] = { 33 "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3", 34 "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7" 35}; 36 37const char *const pci_mem_names[] = { 38 "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3", 39 "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7" 40}; 41 42const char pci_hae0_name[] = "HAE0"; 43 44 45/* 46 * The PCI controller list. 47 */ 48 49struct pci_controller *hose_head, **hose_tail = &hose_head; 50struct pci_controller *pci_isa_hose; 51 52/* 53 * Quirks. 54 */ 55 56static void __init 57quirk_eisa_bridge(struct pci_dev *dev) 58{ 59 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 60} 61 62static void __init 63quirk_isa_bridge(struct pci_dev *dev) 64{ 65 dev->class = PCI_CLASS_BRIDGE_ISA << 8; 66} 67 68static void __init 69quirk_ali_ide_ports(struct pci_dev *dev) 70{ 71 if (dev->resource[0].end == 0xffff) 72 dev->resource[0].end = dev->resource[0].start + 7; 73 if (dev->resource[2].end == 0xffff) 74 dev->resource[2].end = dev->resource[2].start + 7; 75 if (dev->resource[3].end == 0xffff) 76 dev->resource[3].end = dev->resource[3].start + 7; 77} 78 79static void __init 80quirk_cypress(struct pci_dev *dev) 81{ 82 /* The Notorious Cy82C693 chip. */ 83 84 /* The Cypress IDE controller doesn't support native mode, but it 85 has programmable addresses of IDE command/control registers. 86 This violates PCI specifications, confuses the IDE subsystem and 87 causes resource conflicts between the primary HD_CMD register and 88 the floppy controller. Ugh. Fix that. */ 89 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) { 90 dev->resource[0].flags = 0; 91 dev->resource[1].flags = 0; 92 } 93 94 /* The Cypress bridge responds on the PCI bus in the address range 95 0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no 96 way to turn this off. The bridge also supports several extended 97 BIOS ranges (disabled after power-up), and some consoles do turn 98 them on. So if we use a large direct-map window, or a large SG 99 window, we must avoid entire 0xfff00000-0xffffffff region. */ 100 else if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) { 101 if (__direct_map_base + __direct_map_size >= 0xfff00000) 102 __direct_map_size = 0xfff00000 - __direct_map_base; 103 else { 104 struct pci_controller *hose = dev->sysdata; 105 struct pci_iommu_arena *pci = hose->sg_pci; 106 if (pci && pci->dma_base + pci->size >= 0xfff00000) 107 pci->size = 0xfff00000 - pci->dma_base; 108 } 109 } 110} 111 112struct pci_fixup pcibios_fixups[] __initdata = { 113 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, 114 quirk_eisa_bridge }, 115 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, 116 quirk_isa_bridge }, 117 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, 118 quirk_ali_ide_ports }, 119 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, 120 quirk_cypress }, 121 { 0 } 122}; 123 124#define MAX(val1, val2) ((val1) > (val2) ? (val1) : (val2)) 125#define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1)) 126#define KB 1024 127#define MB (1024*KB) 128#define GB (1024*MB) 129 130void 131pcibios_align_resource(void *data, struct resource *res, 132 unsigned long size, unsigned long align) 133{ 134 struct pci_dev *dev = data; 135 struct pci_controller *hose = dev->sysdata; 136 unsigned long alignto; 137 unsigned long start = res->start; 138 139 if (res->flags & IORESOURCE_IO) { 140 /* Make sure we start at our min on all hoses */ 141 if (start - hose->io_space->start < PCIBIOS_MIN_IO) 142 start = PCIBIOS_MIN_IO + hose->io_space->start; 143 144 /* 145 * Put everything into 0x00-0xff region modulo 0x400 146 */ 147 if (start & 0x300) 148 start = (start + 0x3ff) & ~0x3ff; 149 } 150 else if (res->flags & IORESOURCE_MEM) { 151 /* Make sure we start at our min on all hoses */ 152 if (start - hose->mem_space->start < PCIBIOS_MIN_MEM) 153 start = PCIBIOS_MIN_MEM + hose->mem_space->start; 154 155 /* 156 * The following holds at least for the Low Cost 157 * Alpha implementation of the PCI interface: 158 * 159 * In sparse memory address space, the first 160 * octant (16MB) of every 128MB segment is 161 * aliased to the very first 16 MB of the 162 * address space (i.e., it aliases the ISA 163 * memory address space). Thus, we try to 164 * avoid allocating PCI devices in that range. 165 * Can be allocated in 2nd-7th octant only. 166 * Devices that need more than 112MB of 167 * address space must be accessed through 168 * dense memory space only! 169 */ 170 171 /* Align to multiple of size of minimum base. */ 172 alignto = MAX(0x1000, align); 173 start = ALIGN(start, alignto); 174 if (hose->sparse_mem_base && size <= 7 * 16*MB) { 175 if (((start / (16*MB)) & 0x7) == 0) { 176 start &= ~(128*MB - 1); 177 start += 16*MB; 178 start = ALIGN(start, alignto); 179 } 180 if (start/(128*MB) != (start + size - 1)/(128*MB)) { 181 start &= ~(128*MB - 1); 182 start += (128 + 16)*MB; 183 start = ALIGN(start, alignto); 184 } 185 } 186 } 187 188 res->start = start; 189} 190#undef MAX 191#undef ALIGN 192#undef KB 193#undef MB 194#undef GB 195 196void __init 197pcibios_init(void) 198{ 199 if (!alpha_mv.init_pci) 200 return; 201 alpha_mv.init_pci(); 202} 203 204char * __init 205pcibios_setup(char *str) 206{ 207 return str; 208} 209 210void __init 211pcibios_fixup_resource(struct resource *res, struct resource *root) 212{ 213 res->start += root->start; 214 res->end += root->start; 215} 216 217void __init 218pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus) 219{ 220 /* Update device resources. */ 221 struct pci_controller *hose = (struct pci_controller *)bus->sysdata; 222 int i; 223 224 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 225 if (!dev->resource[i].start) 226 continue; 227 if (dev->resource[i].flags & IORESOURCE_IO) 228 pcibios_fixup_resource(&dev->resource[i], 229 hose->io_space); 230 else if (dev->resource[i].flags & IORESOURCE_MEM) 231 pcibios_fixup_resource(&dev->resource[i], 232 hose->mem_space); 233 } 234} 235 236void __init 237pcibios_fixup_bus(struct pci_bus *bus) 238{ 239 /* Propogate hose info into the subordinate devices. */ 240 241 struct pci_controller *hose = bus->sysdata; 242 struct list_head *ln; 243 struct pci_dev *dev = bus->self; 244 245 if (!dev) { 246 /* Root bus */ 247 bus->resource[0] = hose->io_space; 248 bus->resource[1] = hose->mem_space; 249 } 250 251 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 252 struct pci_dev *dev = pci_dev_b(ln); 253 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 254 pcibios_fixup_device_resources(dev, bus); 255 } 256} 257 258void 259pcibios_update_resource(struct pci_dev *dev, struct resource *root, 260 struct resource *res, int resource) 261{ 262 struct pci_controller *hose = dev->sysdata; 263 int where; 264 u32 reg; 265 266 if (resource < PCI_ROM_RESOURCE) 267 where = PCI_BASE_ADDRESS_0 + (resource * 4); 268 else if (resource == PCI_ROM_RESOURCE) 269 where = dev->rom_base_reg; 270 else { 271 return; /* Don't update non-standard resources here. */ 272 } 273 274 /* Point root at the hose root. */ 275 if (res->flags & IORESOURCE_IO) 276 root = hose->io_space; 277 if (res->flags & IORESOURCE_MEM) 278 root = hose->mem_space; 279 280 reg = (res->start - root->start) | (res->flags & 0xf); 281 pci_write_config_dword(dev, where, reg); 282 if ((res->flags & (PCI_BASE_ADDRESS_SPACE 283 | PCI_BASE_ADDRESS_MEM_TYPE_MASK)) 284 == (PCI_BASE_ADDRESS_SPACE_MEMORY 285 | PCI_BASE_ADDRESS_MEM_TYPE_64)) { 286 pci_write_config_dword(dev, where+4, 0); 287 printk(KERN_WARNING "PCI: dev %s type 64-bit\n", dev->name); 288 } 289 290} 291 292void __init 293pcibios_update_irq(struct pci_dev *dev, int irq) 294{ 295 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 296 297} 298 299/* Most Alphas have straight-forward swizzling needs. */ 300 301u8 __init 302common_swizzle(struct pci_dev *dev, u8 *pinp) 303{ 304 struct pci_controller *hose = dev->sysdata; 305 306 if (dev->bus->number != hose->first_busno) { 307 u8 pin = *pinp; 308 do { 309 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); 310 /* Move up the chain of bridges. */ 311 dev = dev->bus->self; 312 } while (dev->bus->self); 313 *pinp = pin; 314 315 /* The slot is the slot of the last bridge. */ 316 } 317 318 return PCI_SLOT(dev->devfn); 319} 320 321void __init 322pcibios_fixup_pbus_ranges(struct pci_bus * bus, 323 struct pbus_set_ranges_data * ranges) 324{ 325 struct pci_controller *hose = (struct pci_controller *)bus->sysdata; 326 327 ranges->io_start -= hose->io_space->start; 328 ranges->io_end -= hose->io_space->start; 329 ranges->mem_start -= hose->mem_space->start; 330 ranges->mem_end -= hose->mem_space->start; 331 ranges->prefetch_start -= hose->mem_space->start; 332 ranges->prefetch_end -= hose->mem_space->start; 333} 334 335int 336pcibios_enable_device(struct pci_dev *dev, int mask) 337{ 338 /* Nothing to do, since we enable all devices at startup. */ 339 return 0; 340} 341 342/* 343 * If we set up a device for bus mastering, we need to check the latency 344 * timer as certain firmware forgets to set it properly, as seen 345 * on SX164 and LX164 with SRM. 346 */ 347void 348pcibios_set_master(struct pci_dev *dev) 349{ 350 u8 lat; 351 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 352 if (lat >= 16) return; 353 printk("PCI: Setting latency timer of device %s to 64\n", 354 dev->slot_name); 355 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); 356} 357 358void __init 359common_init_pci(void) 360{ 361 struct pci_controller *hose; 362 struct pci_bus *bus; 363 int next_busno; 364 365 /* Scan all of the recorded PCI controllers. */ 366 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { 367 hose->first_busno = next_busno; 368 hose->last_busno = 0xff; 369 bus = pci_scan_bus(next_busno, alpha_mv.pci_ops, hose); 370 hose->bus = bus; 371 next_busno = hose->last_busno = bus->subordinate; 372 next_busno += 1; 373 } 374 375 pci_assign_unassigned_resources(); 376 pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq); 377} 378 379 380struct pci_controller * __init 381alloc_pci_controller(void) 382{ 383 struct pci_controller *hose; 384 385 hose = alloc_bootmem(sizeof(*hose)); 386 387 *hose_tail = hose; 388 hose_tail = &hose->next; 389 390 return hose; 391} 392 393struct resource * __init 394alloc_resource(void) 395{ 396 struct resource *res; 397 398 res = alloc_bootmem(sizeof(*res)); 399 400 return res; 401} 402 403 404/* Provide information on locations of various I/O regions in physical 405 memory. Do this on a per-card basis so that we choose the right hose. */ 406 407asmlinkage long 408sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn) 409{ 410 struct pci_controller *hose; 411 struct pci_dev *dev; 412 413 /* from hose or from bus.devfn */ 414 if (which & IOBASE_FROM_HOSE) { 415 for(hose = hose_head; hose; hose = hose->next) 416 if (hose->index == bus) break; 417 if (!hose) return -ENODEV; 418 } else { 419 /* Special hook for ISA access. */ 420 if (bus == 0 && dfn == 0) { 421 hose = pci_isa_hose; 422 } else { 423 dev = pci_find_slot(bus, dfn); 424 if (!dev) 425 return -ENODEV; 426 hose = dev->sysdata; 427 } 428 } 429 430 switch (which & ~IOBASE_FROM_HOSE) { 431 case IOBASE_HOSE: 432 return hose->index; 433 case IOBASE_SPARSE_MEM: 434 return hose->sparse_mem_base; 435 case IOBASE_DENSE_MEM: 436 return hose->dense_mem_base; 437 case IOBASE_SPARSE_IO: 438 return hose->sparse_io_base; 439 case IOBASE_DENSE_IO: 440 return hose->dense_io_base; 441 case IOBASE_ROOT_BUS: 442 return hose->bus->number; 443 } 444 445 return -EOPNOTSUPP; 446} 447 448/* Return the index of the PCI controller for device PDEV. */ 449int 450pci_controller_num(struct pci_dev *pdev) 451{ 452 struct pci_controller *hose = pdev->sysdata; 453 return (hose ? hose->index : -ENXIO); 454} 455