1/* 2 * BCM43XX SiliconBackplane PCIE core hardware definitions. 3 * 4 * Copyright 2007, Broadcom Corporation 5 * All Rights Reserved. 6 * 7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY 8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM 9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS 10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. 11 * 12 * $Id: sbpcie.h,v 1.1.1.1 2008/10/15 03:25:54 james26_jang Exp $ 13 */ 14 15#ifndef _SBPCIE_H 16#define _SBPCIE_H 17 18/* cpp contortions to concatenate w/arg prescan */ 19#ifndef PAD 20#define _PADLINE(line) pad ## line 21#define _XSTR(line) _PADLINE(line) 22#define PAD _XSTR(__LINE__) 23#endif 24 25/* PCIE Enumeration space offsets */ 26#define PCIE_CORE_CONFIG_OFFSET 0x0 27#define PCIE_FUNC0_CONFIG_OFFSET 0x400 28#define PCIE_FUNC1_CONFIG_OFFSET 0x500 29#define PCIE_FUNC2_CONFIG_OFFSET 0x600 30#define PCIE_FUNC3_CONFIG_OFFSET 0x700 31#define PCIE_SPROM_SHADOW_OFFSET 0x800 32#define PCIE_SBCONFIG_OFFSET 0xE00 33 34/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */ 35#define PCIE_DEV_BAR0_SIZE 0x4000 36#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0 37#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000 38#define PCIE_BAR0_PCIECORE_OFFSET 0x2000 39#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000 40 41/* different register spaces to access thr'u pcie indirect access */ 42#define PCIE_CONFIGREGS 1 /* Access to config space */ 43#define PCIE_PCIEREGS 2 /* Access to pcie registers */ 44 45/* SB side: PCIE core and host control registers */ 46typedef struct sbpcieregs { 47 uint32 PAD[3]; 48 uint32 biststatus; /* bist Status: 0x00C */ 49 uint32 gpiosel; /* PCIE gpio sel: 0x010 */ 50 uint32 gpioouten; /* PCIE gpio outen: 0x14 */ 51 uint32 PAD[4]; 52 uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */ 53 uint32 PAD[54]; 54 uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */ 55 uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */ 56 uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */ 57 uint32 PAD[4]; 58 59 /* pcie core supports in direct access to config space */ 60 uint32 configaddr; /* pcie config space access: Address field: 0x120 */ 61 uint32 configdata; /* pcie config space access: Data field: 0x124 */ 62 63 /* mdio access to serdes */ 64 uint32 mdiocontrol; /* controls the mdio access: 0x128 */ 65 uint32 mdiodata; /* Data to the mdio access: 0x12c */ 66 67 /* pcie protocol phy/dllp/tlp register indirect access mechanism */ 68 uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */ 69 uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */ 70 71 uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */ 72 uint32 PAD[433]; 73 uint16 sprom[36]; /* SPROM shadow Area */ 74} sbpcieregs_t; 75 76/* SB to PCIE translation masks */ 77#define SBTOPCIE0_MASK 0xfc000000 78#define SBTOPCIE1_MASK 0xfc000000 79#define SBTOPCIE2_MASK 0xc0000000 80 81/* Access type bits (0:1) */ 82#define SBTOPCIE_MEM 0 83#define SBTOPCIE_IO 1 84#define SBTOPCIE_CFG0 2 85#define SBTOPCIE_CFG1 3 86 87/* Prefetch enable bit 2 */ 88#define SBTOPCIE_PF 4 89 90/* Write Burst enable for memory write bit 3 */ 91#define SBTOPCIE_WR_BURST 8 92 93/* config access */ 94#define CONFIGADDR_FUNC_MASK 0x7000 95#define CONFIGADDR_FUNC_SHF 12 96#define CONFIGADDR_REG_MASK 0x0FFF 97#define CONFIGADDR_REG_SHF 0 98 99/* PCIE protocol regs Indirect Address */ 100#define PCIEADDR_PROT_MASK 0x300 101#define PCIEADDR_PROT_SHF 8 102#define PCIEADDR_PL_TLP 0 103#define PCIEADDR_PL_DLLP 1 104#define PCIEADDR_PL_PLP 2 105 106/* PCIE protocol PHY diagnostic registers */ 107#define PCIE_PLP_MODEREG 0x200 /* Mode */ 108#define PCIE_PLP_STATUSREG 0x204 /* Status */ 109#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */ 110#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */ 111#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */ 112#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */ 113#define PCIE_PLP_ATTNREG 0x218 /* Attention */ 114#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */ 115#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */ 116#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */ 117#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */ 118#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */ 119#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */ 120#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */ 121#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */ 122#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */ 123 124/* PCIE protocol DLLP diagnostic registers */ 125#define PCIE_DLLP_LCREG 0x100 /* Link Control */ 126#define PCIE_DLLP_LSREG 0x104 /* Link Status */ 127#define PCIE_DLLP_LAREG 0x108 /* Link Attention */ 128#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */ 129#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */ 130#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */ 131#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */ 132#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */ 133#define PCIE_DLLP_LRREG 0x120 /* Link Replay */ 134#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */ 135#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */ 136#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */ 137#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */ 138#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */ 139#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */ 140#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */ 141#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */ 142#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */ 143#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */ 144#define PCIE_DLLP_TESTREG 0x14C /* Test */ 145#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */ 146#define PCIE_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */ 147 148/* PCIE protocol TLP diagnostic registers */ 149#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */ 150#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */ 151#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */ 152#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */ 153#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */ 154#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */ 155#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */ 156#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */ 157#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */ 158#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */ 159#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */ 160#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */ 161#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */ 162#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */ 163#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */ 164#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */ 165#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */ 166#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */ 167#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */ 168#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */ 169#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */ 170#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */ 171#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */ 172#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */ 173#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */ 174#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */ 175#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */ 176#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */ 177#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */ 178#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */ 179#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */ 180 181/* MDIO control */ 182#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ 183#define MDIOCTL_DIVISOR_VAL 0x2 184#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */ 185#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */ 186 187/* MDIO Data */ 188#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */ 189#define MDIODATA_TA 0x00020000 /* Turnaround */ 190#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */ 191#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */ 192#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */ 193#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */ 194#define MDIODATA_WRITE 0x10000000 /* write Transaction */ 195#define MDIODATA_READ 0x20000000 /* Read Transaction */ 196#define MDIODATA_START 0x40000000 /* start of Transaction */ 197 198/* MDIO devices (SERDES modules) */ 199#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */ 200#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */ 201#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */ 202 203/* SERDES RX registers */ 204#define SERDES_RX_CTRL 1 /* Rx cntrl */ 205#define SERDES_RX_TIMER1 2 /* Rx Timer1 */ 206#define SERDES_RX_CDR 6 /* CDR */ 207#define SERDES_RX_CDRBW 7 /* CDR BW */ 208 209/* SERDES RX control register */ 210#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ 211#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */ 212 213/* SERDES PLL registers */ 214#define SERDES_PLL_CTRL 1 /* PLL control reg */ 215#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ 216 217#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */ 218#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */ 219#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */ 220 221/* SPROM offsets */ 222#define SRSH_ASPM_OFFSET 4 /* word 4 */ 223#define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */ 224#define SRSH_CLKREQ_OFFSET 20 /* word 20 */ 225#define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */ 226 227/* Linkcontrol reg offset in PCIE Cap */ 228#define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */ 229#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */ 230#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */ 231#define PCIE_ASPM_ENAB 0x03 /* ASPM L0s & L1 in linkctrl */ 232#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */ 233 234/* Status reg PCIE_PLP_STATUSREG */ 235#define PCIE_PLP_POLARITYINV_STAT 0x10 236 237#endif /* _SBPCIE_H */ 238