1/******************************************************************************/ 2/* */ 3/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2005 Broadcom */ 4/* Corporation. */ 5/* All rights reserved. */ 6/* */ 7/* This program is free software; you can redistribute it and/or modify */ 8/* it under the terms of the GNU General Public License as published by */ 9/* the Free Software Foundation, located in the file LICENSE. */ 10/* */ 11/* History: */ 12/* */ 13/******************************************************************************/ 14 15#ifndef TIGON3_H 16#define TIGON3_H 17 18#include "lm.h" 19#if INCLUDE_TBI_SUPPORT 20#include "autoneg.h" 21#endif 22 23 24 25/******************************************************************************/ 26/* Constants. */ 27/******************************************************************************/ 28 29#ifndef TIGON3_DEBUG 30#define TIGON3_DEBUG 0 31#endif /* TIGON3_DEBUG */ 32 33/* Number of entries in the Jumbo Receive RCB. This value must 256 or 0. */ 34/* Currently, Jumbo Receive RCB is disabled. */ 35#ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT 36#define T3_JUMBO_RCV_RCB_ENTRY_COUNT 0 37#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ 38 39#ifndef T3_JUMBO_RCV_ENTRY_COUNT 40#define T3_JUMBO_RCV_ENTRY_COUNT 0 41#endif /* T3_JUMBO_RCV_ENTRY_COUNT */ 42 43#ifndef T3_JUMBO_RCB_ENTRY_COUNT 44#define T3_JUMBO_RCB_ENTRY_COUNT 0 45#endif /* T3_JUMBO_RCB_ENTRY_COUNT */ 46 47/* Maxim number of packet descriptors used for sending packets. */ 48#define MAX_TX_PACKET_DESC_COUNT T3_SEND_RCB_ENTRY_COUNT 49#define DEFAULT_TX_PACKET_DESC_COUNT 120 50 51/* Maximum number of packet descriptors used for receiving packets. */ 52#if T3_JUMBO_RCB_ENTRY_COUNT 53#define MAX_RX_PACKET_DESC_COUNT \ 54 (T3_STD_RCV_RCB_ENTRY_COUNT + T3_JUMBO_RCV_RCB_ENTRY_COUNT) 55#else 56#define MAX_RX_PACKET_DESC_COUNT T3_STD_RCV_RCB_ENTRY_COUNT 57#endif 58#define DEFAULT_RX_PACKET_DESC_COUNT 200 59 60/* Threshhold for double copying small tx packets. 0 will disable double */ 61/* copying of small Tx packets. */ 62#define DEFAULT_TX_COPY_BUFFER_SIZE 0 63#define MIN_TX_COPY_BUFFER_SIZE 64 64#define MAX_TX_COPY_BUFFER_SIZE 512 65 66/* Cache line. */ 67#define COMMON_CACHE_LINE_SIZE 0x20 68#define COMMON_CACHE_LINE_MASK (COMMON_CACHE_LINE_SIZE-1) 69 70/* Maximum number of fragment we can handle. */ 71#ifndef MAX_FRAGMENT_COUNT 72#define MAX_FRAGMENT_COUNT 32 73#endif 74 75/* B0 bug. */ 76#define BCM5700_BX_MIN_FRAG_SIZE 10 77#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */ 78#define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1) 79#define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \ 80 MAX_FRAGMENT_COUNT) 81 82/* MAGIC number. */ 83//#define T3_MAGIC_NUM 'KevT' 84#define T3_FIRMWARE_MAILBOX 0x0b50 85#define T3_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4B657654 86#define T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 87 88#define T3_NIC_DATA_SIG_ADDR 0x0b54 89#define T3_NIC_DATA_SIG 0x4b657654 90 91#define T3_NIC_DATA_NIC_CFG_ADDR 0x0b58 92#define T3_NIC_CFG_LED_MAC_MODE BIT_NONE 93#define T3_NIC_CFG_LED_PHY_MODE_1 BIT_2 94#define T3_NIC_CFG_LED_PHY_MODE_2 BIT_3 95#define T3_NIC_CFG_LED_MODE_MASK (BIT_2 | BIT_3) 96#define T3_NIC_CFG_PHY_TYPE_UNKNOWN BIT_NONE 97#define T3_NIC_CFG_PHY_TYPE_COPPER BIT_4 98#define T3_NIC_CFG_PHY_TYPE_FIBER BIT_5 99#define T3_NIC_CFG_PHY_TYPE_MASK (BIT_4 | BIT_5) 100#define T3_NIC_CFG_ENABLE_WOL BIT_6 101#define T3_NIC_CFG_ENABLE_ASF BIT_7 102#define T3_NIC_EEPROM_WP BIT_8 103#define T3_NIC_WOL_LIMIT_10 BIT_10 104#define T3_NIC_MINI_PCI BIT_12 105#define T3_NIC_FIBER_WOL_CAPABLE BIT_14 106#define T3_NIC_BOTH_PORT_100MB_WOL_CAPABLE BIT_15 107#define T3_NIC_GPIO2_NOT_AVAILABLE BIT_20 108 109#define T3_NIC_DATA_VER 0x0b5c 110#define T3_NIC_DATA_VER_SHIFT 16 111 112#define T3_NIC_DATA_PHY_ID_ADDR 0x0b74 113#define T3_NIC_PHY_ID1_MASK 0xffff0000 114#define T3_NIC_PHY_ID2_MASK 0x0000ffff 115 116#define T3_CMD_MAILBOX 0x0b78 117#define T3_CMD_NICDRV_ALIVE 0x01 118#define T3_CMD_NICDRV_PAUSE_FW 0x02 119#define T3_CMD_NICDRV_IPV4ADDR_CHANGE 0x03 120#define T3_CMD_NICDRV_IPV6ADDR_CHANGE 0x04 121#define T3_CMD_5703A0_FIX_DMAFW_DMAR 0x05 122#define T3_CMD_5703A0_FIX_DMAFW_DMAW 0x06 123 124#define T3_CMD_NICDRV_ALIVE2 0x0d 125 126#define T3_CMD_LENGTH_MAILBOX 0x0b7c 127#define T3_CMD_DATA_MAILBOX 0x0b80 128 129#define T3_ASF_FW_STATUS_MAILBOX 0x0c00 130 131#define T3_DRV_STATE_MAILBOX 0x0c04 132#define T3_DRV_STATE_START 0x01 133#define T3_DRV_STATE_START_DONE 0x80000001 134#define T3_DRV_STATE_UNLOAD 0x02 135#define T3_DRV_STATE_UNLOAD_DONE 0x80000002 136#define T3_DRV_STATE_WOL 0x03 137#define T3_DRV_STATE_SUSPEND 0x04 138 139#define T3_FW_RESET_TYPE_MAILBOX 0x0c08 140 141#define T3_MAC_ADDR_HIGH_MAILBOX 0x0c14 142#define T3_MAC_ADDR_LOW_MAILBOX 0x0c18 143 144#define DRV_WOL_MAILBOX 0xd30 145#define DRV_WOL_SIGNATURE 0x474c0000 146 147#define DRV_DOWN_STATE_SHUTDOWN 0x1 148 149#define DRV_WOL_SET_MAGIC_PKT BIT_2 150 151#define T3_NIC_DATA_NIC_CFG_ADDR2 0x0d38 /* bit 2-3 are same as in */ 152 /* 0xb58 */ 153#define T3_SHASTA_EXT_LED_MODE_MASK (BIT_15 | BIT_16) 154#define T3_SHASTA_EXT_LED_LEGACY_MODE BIT_NONE 155#define T3_SHASTA_EXT_LED_SHARED_TRAFFIC_LINK_MODE BIT_15 156#define T3_SHASTA_EXT_LED_MAC_MODE BIT_16 157#define T3_SHASTA_EXT_LED_WIRELESS_COMBO_MODE (BIT_15 | BIT_16) 158#define T3_NIC_CFG_CAPACITIVE_COUPLING BIT_17 159#define T3_NIC_CFG_PRESERVE_PREEMPHASIS BIT_18 160 161/******************************************************************************/ 162/* Hardware constants. */ 163/******************************************************************************/ 164 165/* Number of entries in the send ring: must be 512. */ 166#define T3_SEND_RCB_ENTRY_COUNT 512 167#define T3_SEND_RCB_ENTRY_COUNT_MASK (T3_SEND_RCB_ENTRY_COUNT-1) 168 169/* Number of send RCBs. May be 1-16 but for now, only support one. */ 170#define T3_MAX_SEND_RCB_COUNT 16 171 172/* Number of entries in the Standard Receive RCB. Must be 512 entries. */ 173#define T3_STD_RCV_RCB_ENTRY_COUNT 512 174#define T3_STD_RCV_RCB_ENTRY_COUNT_MASK (T3_STD_RCV_RCB_ENTRY_COUNT-1) 175#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */ 176#define MAX_STD_RCV_BUFFER_SIZE 0x600 177 178/* Number of entries in the Mini Receive RCB. This value can either be */ 179/* 0, 1024. Currently Mini Receive RCB is disabled. */ 180#ifndef T3_MINI_RCV_RCB_ENTRY_COUNT 181#define T3_MINI_RCV_RCB_ENTRY_COUNT 0 182#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */ 183#define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK (T3_MINI_RCV_RCB_ENTRY_COUNT-1) 184#define MAX_MINI_RCV_BUFFER_SIZE 512 185#define DEFAULT_MINI_RCV_BUFFER_SIZE 64 186#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */ 187 188#define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1) 189 190#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */ 191#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */ 192#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */ 193 194#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */ 195#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */ 196 197/* Number of receive return RCBs. Maybe 1-16 but for now, only support one. */ 198#define T3_MAX_RCV_RETURN_RCB_COUNT 16 199 200/* Number of entries in a Receive Return ring. This value is either 1024 */ 201/* or 2048. */ 202#ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT 203#define T3_RCV_RETURN_RCB_ENTRY_COUNT 1024 204#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */ 205#define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK (T3_RCV_RETURN_RCB_ENTRY_COUNT-1) 206 207 208/* Default coalescing parameters. */ 209#ifdef BCM_NAPI_RXPOLL 210#define DEFAULT_RX_COALESCING_TICKS 18 211#define DEFAULT_RX_MAX_COALESCED_FRAMES 6 212#else 213#define DEFAULT_RX_COALESCING_TICKS 60 214#define DEFAULT_RX_MAX_COALESCED_FRAMES 15 215#endif 216 217#define DEFAULT_TX_COALESCING_TICKS 200 218#define DEFAULT_TX_MAX_COALESCED_FRAMES 35 219 220#define MAX_RX_COALESCING_TICKS 500 221#define MAX_TX_COALESCING_TICKS 500 222#define MAX_RX_MAX_COALESCED_FRAMES 100 223#define MAX_TX_MAX_COALESCED_FRAMES 100 224 225#define ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES 5 226#define ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES 48 227#define ADAPTIVE_LO_RX_COALESCING_TICKS 25 228#define ADAPTIVE_HI_RX_COALESCING_TICKS 120 229#define ADAPTIVE_LO_PKT_THRESH 52000 230#define ADAPTIVE_HI_PKT_THRESH 112000 231#define ADAPTIVE_LO_TX_MAX_COALESCED_FRAMES 20 232#define ADAPTIVE_HI_TX_MAX_COALESCED_FRAMES 75 233 234#ifdef BCM_NAPI_RXPOLL 235#define DEFAULT_RX_COALESCING_TICKS_DURING_INT 18 236#define DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT 6 237#else 238#define DEFAULT_RX_COALESCING_TICKS_DURING_INT 25 239#define DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT 2 240#endif 241#define DEFAULT_TX_COALESCING_TICKS_DURING_INT 25 242#define ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES_DURING_INT 1 243#define ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES_DURING_INT 5 244#define DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT 5 245 246#define BAD_DEFAULT_VALUE 0xffffffff 247 248#define DEFAULT_STATS_COALESCING_TICKS 1000000 249#define MIN_STATS_COALESCING_TICKS 100 250#define MAX_STATS_COALESCING_TICKS 3600000000U 251 252 253/* Receive BD Replenish thresholds. */ 254#define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD 4 255#define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD 4 256 257/* Maximum physical fragment size. */ 258#define MAX_FRAGMENT_SIZE (64 * 1024) 259 260 261/* Standard view. */ 262#define T3_STD_VIEW_SIZE (64 * 1024) 263#define T3_FLAT_VIEW_SIZE (32 * 1024 * 1024) 264 265 266/* Buffer descriptor base address on the NIC's memory. */ 267 268#define T3_NIC_SND_BUFFER_DESC_ADDR 0x4000 269#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR 0x6000 270#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR 0x7000 271 272#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xc000 273#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xd000 274#define T3_NIC_MINI_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xe000 275 276#define T3_NIC_SND_BUFFER_DESC_SIZE (T3_SEND_RCB_ENTRY_COUNT * \ 277 sizeof(T3_SND_BD) / 4) 278 279#define T3_NIC_STD_RCV_BUFFER_DESC_SIZE (T3_STD_RCV_RCB_ENTRY_COUNT * \ 280 sizeof(T3_RCV_BD) / 4) 281 282#define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \ 283 sizeof(T3_EXT_RCV_BD) / 4) 284 285 286/* MBUF pool. */ 287#define T3_NIC_MBUF_POOL_ADDR 0x8000 288#define T3_NIC_MBUF_POOL_SIZE32 0x8000 289#define T3_NIC_MBUF_POOL_SIZE96 0x18000 290#define T3_NIC_MBUF_POOL_SIZE64 0x10000 291 292#define T3_NIC_MBUF_POOL_ADDR_EXT_MEM 0x20000 293 294#define T3_NIC_BCM5705_MBUF_POOL_ADDR 0x10000 295#define T3_NIC_BCM5705_MBUF_POOL_SIZE 0xe000 296 297/* DMA descriptor pool */ 298#define T3_NIC_DMA_DESC_POOL_ADDR 0x2000 299#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */ 300 301#define T3_DEF_DMA_MBUF_LOW_WMARK 0x50 302#define T3_DEF_RX_MAC_MBUF_LOW_WMARK 0x20 303#define T3_DEF_MBUF_HIGH_WMARK 0x60 304 305#define T3_DEF_DMA_MBUF_LOW_WMARK_5705 0x0 306#define T3_DEF_RX_MAC_MBUF_LOW_WMARK_5705 0x10 307#define T3_DEF_MBUF_HIGH_WMARK_5705 0x60 308 309#define T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO 304 310#define T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO 152 311#define T3_DEF_MBUF_HIGH_WMARK_JUMBO 380 312 313#define T3_DEF_DMA_DESC_LOW_WMARK 5 314#define T3_DEF_DMA_DESC_HIGH_WMARK 10 315 316/* Maximum size of giant TCP packet can be sent */ 317#define T3_TCP_SEG_MAX_OFFLOAD_SIZE 64*1000 318#define T3_TCP_SEG_MIN_NUM_SEG 20 319 320#define T3_RX_CPU_ID 0x1 321#define T3_TX_CPU_ID 0x2 322#define T3_RX_CPU_SPAD_ADDR 0x30000 323#define T3_RX_CPU_SPAD_SIZE 0x4000 324#define T3_TX_CPU_SPAD_ADDR 0x34000 325#define T3_TX_CPU_SPAD_SIZE 0x4000 326 327typedef struct T3_DIR_ENTRY 328{ 329 PLM_UINT8 Buffer; 330 LM_UINT32 Offset; 331 LM_UINT32 Length; 332} T3_DIR_ENTRY,*PT3_DIR_ENTRY; 333 334typedef struct T3_FWIMG_INFO 335{ 336 LM_UINT32 StartAddress; 337 T3_DIR_ENTRY Text; 338 T3_DIR_ENTRY ROnlyData; 339 T3_DIR_ENTRY Data; 340 T3_DIR_ENTRY Sbss; 341 T3_DIR_ENTRY Bss; 342} T3_FWIMG_INFO, *PT3_FWIMG_INFO; 343 344 345 346/******************************************************************************/ 347/* Tigon3 PCI Registers. */ 348/******************************************************************************/ 349/* MSI ENABLE bit is located at this offset */ 350#define T3_PCI_MSI_ENABLE 0x58 351 352#define T3_PCI_ID_BCM5700 0x164414e4 353#define T3_PCI_ID_BCM5701 0x164514e4 354#define T3_PCI_ID_BCM5702 0x164614e4 355#define T3_PCI_ID_BCM5702x 0x16A614e4 356#define T3_PCI_ID_BCM5703 0x164714e4 357#define T3_PCI_ID_BCM5703x 0x16A714e4 358#define T3_PCI_ID_BCM5702FE 0x164D14e4 359#define T3_PCI_ID_BCM5704 0x164814e4 360#define T3_PCI_ID_BCM5705 0x165314e4 361#define T3_PCI_ID_BCM5705M 0x165D14e4 362#define T3_PCI_ID_BCM5705F 0x166E14e4 363#define T3_PCI_ID_BCM5901 0x170D14e4 364#define T3_PCI_ID_BCM5901A2 0x170E14e4 365#define T3_PCI_ID_BCM5751F 0x167E14e4 366 367#define T3_PCI_ID_BCM471F 0x471f14e4 368 369#define T3_PCI_ID_BCM5753 0x16f714e4 370#define T3_PCI_ID_BCM5753M 0x16fd14e4 371#define T3_PCI_ID_BCM5753F 0x16fe14e4 372#define T3_PCI_ID_BCM5781 0x16dd14e4 373 374#define T3_PCI_ID_BCM5903M 0x16ff14e4 375 376#define T3_PCI_VENDOR_ID(x) ((x) & 0xffff) 377#define T3_PCI_DEVICE_ID(x) ((x) >> 16) 378 379#define T3_PCI_MISC_HOST_CTRL_REG 0x68 380 381/* The most significant 16bit of register 0x68. */ 382/* ChipId:4, ChipRev:4, MetalRev:8 */ 383#define T3_CHIP_ID_5700_A0 0x7000 384#define T3_CHIP_ID_5700_A1 0x7001 385#define T3_CHIP_ID_5700_B0 0x7100 386#define T3_CHIP_ID_5700_B1 0x7101 387#define T3_CHIP_ID_5700_C0 0x7200 388 389#define T3_CHIP_ID_5701_A0 0x0000 390#define T3_CHIP_ID_5701_B0 0x0100 391#define T3_CHIP_ID_5701_B2 0x0102 392#define T3_CHIP_ID_5701_B5 0x0105 393 394#define T3_CHIP_ID_5703_A0 0x1000 395#define T3_CHIP_ID_5703_A1 0x1001 396#define T3_CHIP_ID_5703_A2 0x1002 397#define T3_CHIP_ID_5703_A3 0x1003 398 399#define T3_CHIP_ID_5704_A0 0x2000 400#define T3_CHIP_ID_5704_A1 0x2001 401#define T3_CHIP_ID_5704_A2 0x2002 402 403#define T3_CHIP_ID_5705_A0 0x3000 404#define T3_CHIP_ID_5705_A1 0x3001 405#define T3_CHIP_ID_5705_A2 0x3002 406#define T3_CHIP_ID_5705_A3 0x3003 407 408#define T3_CHIP_ID_5750_A0 0x4000 409#define T3_CHIP_ID_5750_A1 0x4001 410#define T3_CHIP_ID_5750_A3 0x4003 411#define T3_CHIP_ID_5750_B0 0x4010 412#define T3_CHIP_ID_5750_C0 0x4200 413 414#define T3_CHIP_ID_5714_A0 0x5000 415#define T3_CHIP_ID_5752_A0 0x6000 416#define T3_CHIP_ID_5714 0x8000 417 418 419/* Chip Id. */ 420#define T3_ASIC_REV(_ChipRevId) ((_ChipRevId) >> 12) 421#define T3_ASIC_REV_5700 0x07 422#define T3_ASIC_REV_5701 0x00 423#define T3_ASIC_REV_5703 0x01 424#define T3_ASIC_REV_5704 0x02 425#define T3_ASIC_REV_5705 0x03 426#define T3_ASIC_REV_5750 0x04 427#define T3_ASIC_REV_5714_A0 0x05 /*5714,5715*/ 428#define T3_ASIC_REV_5752 0x06 429#define T3_ASIC_REV_5780 0x08 /* 5780 previously htle */ 430#define T3_ASIC_REV_5714 0x09 /*5714,5715*/ 431 432#define T3_ASIC_IS_5705_BEYOND(_ChipRevId) \ 433 ((T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5705) || \ 434 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5750) || \ 435 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714_A0) || \ 436 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5780) || \ 437 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714) || \ 438 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5752)) 439 440#define T3_ASIC_IS_575X_PLUS(_ChipRevId) \ 441 ((T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5750) || \ 442 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714_A0) || \ 443 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5780) || \ 444 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714) || \ 445 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5752)) 446 447#define T3_ASIC_5714_FAMILY(_ChipRevId) \ 448 ((T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714_A0) || \ 449 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5780) || \ 450 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714)) 451 452#define T3_ASIC_IS_JUMBO_CAPABLE(_ChipRevId) \ 453 ((T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5700) || \ 454 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5701) || \ 455 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5703) || \ 456 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714_A0) || \ 457 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5780) || \ 458 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5714) || \ 459 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5704)) 460 461#define T3_ASIC_5752(_ChipRevId) \ 462 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5752) 463 464#define T3_ASIC_5705_OR_5750(_ChipRevId) \ 465 ((T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5705) || \ 466 (T3_ASIC_REV(_ChipRevId) == T3_ASIC_REV_5750)) 467 468/* Chip id and revision. */ 469#define T3_CHIP_REV(_ChipRevId) ((_ChipRevId) >> 8) 470#define T3_CHIP_REV_5700_AX 0x70 471#define T3_CHIP_REV_5700_BX 0x71 472#define T3_CHIP_REV_5700_CX 0x72 473#define T3_CHIP_REV_5701_AX 0x00 474#define T3_CHIP_REV_5703_AX 0x10 475#define T3_CHIP_REV_5704_AX 0x20 476#define T3_CHIP_REV_5704_BX 0x21 477 478#define T3_CHIP_REV_5750_AX 0x40 479#define T3_CHIP_REV_5750_BX 0x41 480 481/* Metal revision. */ 482#define T3_METAL_REV(_ChipRevId) ((_ChipRevId) & 0xff) 483#define T3_METAL_REV_A0 0x00 484#define T3_METAL_REV_A1 0x01 485#define T3_METAL_REV_B0 0x00 486#define T3_METAL_REV_B1 0x01 487#define T3_METAL_REV_B2 0x02 488 489#define T3_PCI_REG_CLOCK_CTRL 0x74 490 491#define T3_PCI_DISABLE_RX_CLOCK BIT_10 492#define T3_PCI_DISABLE_TX_CLOCK BIT_11 493#define T3_PCI_SELECT_ALTERNATE_CLOCK BIT_12 494#define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15 495#define T3_PCI_44MHZ_CORE_CLOCK BIT_18 496#define T3_PCI_625_CORE_CLOCK BIT_20 497#define T3_PCI_FORCE_CLKRUN BIT_21 498#define T3_PCI_CLKRUN_OUTPUT_EN BIT_22 499 500 501#define T3_PCI_REG_ADDR_REG 0x78 502#define T3_PCI_REG_DATA_REG 0x80 503 504#define T3_PCI_MEM_WIN_ADDR_REG 0x7c 505#define T3_PCI_MEM_WIN_DATA_REG 0x84 506 507#define T3_PCI_PM_CAP_REG 0x48 508 509#define T3_PCI_PM_CAP_PME_D3COLD BIT_31 510#define T3_PCI_PM_CAP_PME_D3HOT BIT_30 511 512#define T3_PCI_PM_STATUS_CTRL_REG 0x4c 513 514#define T3_PM_POWER_STATE_MASK (BIT_0 | BIT_1) 515#define T3_PM_POWER_STATE_D0 BIT_NONE 516#define T3_PM_POWER_STATE_D1 BIT_0 517#define T3_PM_POWER_STATE_D2 BIT_1 518#define T3_PM_POWER_STATE_D3 (BIT_0 | BIT_1) 519 520#define T3_PM_PME_ENABLE BIT_8 521#define T3_PM_PME_ASSERTED BIT_15 522 523#define T3_MSI_CAPABILITY_ID_REG 0x58 524#define T3_MSI_NEXT_CAPABILITY_PTR 0x59 525 526/* PCI state register. */ 527#define T3_PCI_STATE_REG 0x70 528 529#define T3_PCI_STATE_FORCE_RESET BIT_0 530#define T3_PCI_STATE_INT_NOT_ACTIVE BIT_1 531#define T3_PCI_STATE_CONVENTIONAL_PCI_MODE BIT_2 532#define T3_PCI_STATE_BUS_SPEED_HIGH BIT_3 533#define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 534 535 536/* Broadcom subsystem/subvendor IDs. */ 537#define T3_SVID_BROADCOM 0x14e4 538 539#define T3_SSID_BROADCOM_BCM95700A6 0x1644 540#define T3_SSID_BROADCOM_BCM95701A5 0x0001 541#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */ 542#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */ 543#define T3_SSID_BROADCOM_BCM95701T1 0x0005 544#define T3_SSID_BROADCOM_BCM95701T8 0x0006 545#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */ 546#define T3_SSID_BROADCOM_BCM95701A10 0x0008 547#define T3_SSID_BROADCOM_BCM95701A12 0x8008 548#define T3_SSID_BROADCOM_BCM95703Ax1 0x0009 549#define T3_SSID_BROADCOM_BCM95703Ax2 0x8009 550 551/* 3COM subsystem/subvendor IDs. */ 552#define T3_SVID_3COM 0x10b7 553 554#define T3_SSID_3COM_3C996T 0x1000 555#define T3_SSID_3COM_3C996BT 0x1006 556#define T3_SSID_3COM_3C996CT 0x1002 557#define T3_SSID_3COM_3C997T 0x1003 558#define T3_SSID_3COM_3C1000T 0x1007 559#define T3_SSID_3COM_3C940BR01 0x1008 560 561/* Fiber boards. */ 562#define T3_SSID_3COM_3C996SX 0x1004 563#define T3_SSID_3COM_3C997SX 0x1005 564 565 566/* Dell subsystem/subvendor IDs. */ 567 568#define T3_SVID_DELL 0x1028 569 570#define T3_SSID_DELL_VIPER 0x00d1 571#define T3_SSID_DELL_JAGUAR 0x0106 572#define T3_SSID_DELL_MERLOT 0x0109 573#define T3_SSID_DELL_SLIM_MERLOT 0x010a 574 575/* Compaq subsystem/subvendor IDs */ 576 577#define T3_SVID_COMPAQ 0x0e11 578 579#define T3_SSID_COMPAQ_BANSHEE 0x007c 580#define T3_SSID_COMPAQ_BANSHEE_2 0x009a 581#define T3_SSID_COMPAQ_CHANGELING 0x007d 582#define T3_SSID_COMPAQ_NC7780 0x0085 583#define T3_SSID_COMPAQ_NC7780_2 0x0099 584 585#define T3_PCIE_CAPABILITY_ID_REG 0xD0 586#define T3_PCIE_CAPABILITY_ID 0x10 587 588#define T3_PCIE_CAPABILITY_REG 0xD2 589 590/******************************************************************************/ 591/* MII registers. */ 592/******************************************************************************/ 593 594/* Control register. */ 595#define PHY_CTRL_REG 0x00 596 597#define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13) 598#define PHY_CTRL_SPEED_SELECT_10MBPS BIT_NONE 599#define PHY_CTRL_SPEED_SELECT_100MBPS BIT_13 600#define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_6 601#define PHY_CTRL_COLLISION_TEST_ENABLE BIT_7 602#define PHY_CTRL_FULL_DUPLEX_MODE BIT_8 603#define PHY_CTRL_RESTART_AUTO_NEG BIT_9 604#define PHY_CTRL_ISOLATE_PHY BIT_10 605#define PHY_CTRL_LOWER_POWER_MODE BIT_11 606#define PHY_CTRL_AUTO_NEG_ENABLE BIT_12 607#define PHY_CTRL_LOOPBACK_MODE BIT_14 608#define PHY_CTRL_PHY_RESET BIT_15 609 610 611/* Status register. */ 612#define PHY_STATUS_REG 0x01 613 614#define PHY_STATUS_LINK_PASS BIT_2 615#define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5 616 617 618/* Phy Id registers. */ 619#define PHY_ID1_REG 0x02 620#define PHY_ID1_OUI_MASK 0xffff 621 622#define PHY_ID2_REG 0x03 623#define PHY_ID2_REV_MASK 0x000f 624#define PHY_ID2_MODEL_MASK 0x03f0 625#define PHY_ID2_OUI_MASK 0xfc00 626 627 628/* Auto-negotiation advertisement register. */ 629#define PHY_AN_AD_REG 0x04 630 631#define PHY_AN_AD_ASYM_PAUSE BIT_11 632#define PHY_AN_AD_PAUSE_CAPABLE BIT_10 633#define PHY_AN_AD_10BASET_HALF BIT_5 634#define PHY_AN_AD_10BASET_FULL BIT_6 635#define PHY_AN_AD_100BASETX_HALF BIT_7 636#define PHY_AN_AD_100BASETX_FULL BIT_8 637#define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01 638 639/* Defines for 5714 family fiber on the 546x phy*/ 640 641#define PHY_AN_AD_1000XFULL 0x20 642#define PHY_AN_AD_1000XHALF 0x40 643#define PHY_AN_AD_1000XPAUSE 0x80 644#define PHY_AN_AD_1000XPSE_ASYM 0x100 645#define PHY_AN_AD_1000XREM_FAULT_OFFLINE 0x2000 646#define PHY_AN_AD_1000XREM_FAULT_AN_ERROR 0x3000 647 648#define PHY_AN_AD_ALL_SPEEDS (PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |\ 649 PHY_AN_AD_100BASETX_HALF | PHY_AN_AD_100BASETX_FULL) 650 651/* Auto-negotiation Link Partner Ability register. */ 652#define PHY_LINK_PARTNER_ABILITY_REG 0x05 653 654#define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11 655#define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10 656 657 658/* Auto-negotiation expansion register. */ 659#define PHY_AN_EXPANSION_REG 0x06 660 661 662 663/******************************************************************************/ 664/* BCM5400 and BCM5401 phy info. */ 665/******************************************************************************/ 666 667#define PHY_DEVICE_ID 1 668 669/* OUI: bit 31-10; Model#: bit 9-4; Rev# bit 3-0. */ 670#define PHY_UNKNOWN_PHY 0x00000000 671#define PHY_BCM5400_PHY_ID 0x60008040 672#define PHY_BCM5401_PHY_ID 0x60008050 673#define PHY_BCM5411_PHY_ID 0x60008070 674#define PHY_BCM5461_PHY_ID 0x600080c0 675#define PHY_BCM5701_PHY_ID 0x60008110 676#define PHY_BCM5703_PHY_ID 0x60008160 677#define PHY_BCM5704_PHY_ID 0x60008190 678#define PHY_BCM5705_PHY_ID 0x600081a0 679#define PHY_BCM5750_PHY_ID 0x60008180 680#define PHY_BCM8002_PHY_ID 0x60010140 681#define PHY_BCM5714_PHY_ID 0x60008340 682#define PHY_BCM5780_PHY_ID 0x60008350 683#define PHY_BCM5752_PHY_ID 0x60008100 684 685#define PHY_BCM5401_B0_REV 0x1 686#define PHY_BCM5401_B2_REV 0x3 687#define PHY_BCM5401_C0_REV 0x6 688 689#define PHY_ID_OUI_MASK 0xfffffc00 690#define PHY_ID_MODEL_MASK 0x000003f0 691#define PHY_ID_REV_MASK 0x0000000f 692#define PHY_ID_MASK (PHY_ID_OUI_MASK | \ 693 PHY_ID_MODEL_MASK) 694 695#define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \ 696 (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \ 697 (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \ 698 (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \ 699 (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \ 700 (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \ 701 (((x) & PHY_ID_MASK) != PHY_BCM5705_PHY_ID) && \ 702 (((x) & PHY_ID_MASK) != PHY_BCM5750_PHY_ID) && \ 703 (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID) && \ 704 (((x) & PHY_ID_MASK) != PHY_BCM5714_PHY_ID) && \ 705 (((x) & PHY_ID_MASK) != PHY_BCM5780_PHY_ID) && \ 706 (((x) & PHY_ID_MASK) != PHY_BCM5752_PHY_ID) && \ 707 (((x) & PHY_ID_MASK) != PHY_BCM5461_PHY_ID)) 708 709/* 1000Base-T control register. */ 710#define BCM540X_1000BASET_CTRL_REG 0x09 711 712#define BCM540X_AN_AD_1000BASET_HALF BIT_8 713#define BCM540X_AN_AD_1000BASET_FULL BIT_9 714#define BCM540X_CONFIG_AS_MASTER BIT_11 715#define BCM540X_ENABLE_CONFIG_AS_MASTER BIT_12 716 717#define BCM540X_AN_AD_ALL_1G_SPEEDS (BCM540X_AN_AD_1000BASET_HALF | \ 718 BCM540X_AN_AD_1000BASET_FULL) 719 720/* Extended control register. */ 721#define BCM540X_EXT_CTRL_REG 0x10 722 723#define BCM540X_EXT_CTRL_LINK3_LED_MODE BIT_1 724#define BCM540X_EXT_CTRL_FORCE_LED_OFF BIT_3 725#define BCM540X_EXT_CTRL_TBI BIT_15 726 727/* PHY extended status register. */ 728#define BCM540X_EXT_STATUS_REG 0x11 729 730#define BCM540X_EXT_STATUS_LINK_PASS BIT_8 731 732 733/* DSP Coefficient Read/Write Port. */ 734#define BCM540X_DSP_RW_PORT 0x15 735 736 737/* DSP Coeficient Address Register. */ 738#define BCM540X_DSP_ADDRESS_REG 0x17 739 740#define BCM540X_DSP_TAP_NUMBER_MASK 0x00 741#define BCM540X_DSP_AGC_A 0x00 742#define BCM540X_DSP_AGC_B 0x01 743#define BCM540X_DSP_MSE_PAIR_STATUS 0x02 744#define BCM540X_DSP_SOFT_DECISION 0x03 745#define BCM540X_DSP_PHASE_REG 0x04 746#define BCM540X_DSP_SKEW 0x05 747#define BCM540X_DSP_POWER_SAVER_UPPER_BOUND 0x06 748#define BCM540X_DSP_POWER_SAVER_LOWER_BOUND 0x07 749#define BCM540X_DSP_LAST_ECHO 0x08 750#define BCM540X_DSP_FREQUENCY 0x09 751#define BCM540X_DSP_PLL_BANDWIDTH 0x0a 752#define BCM540X_DSP_PLL_PHASE_OFFSET 0x0b 753 754#define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11) 755#define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11) 756#define BCM540X_DSP_FILTER_FEXT2 (BIT_9 | BIT_11) 757#define BCM540X_DSP_FILTER_FEXT1 (BIT_8 | BIT_11) 758#define BCM540X_DSP_FILTER_FEXT0 BIT_11 759#define BCM540X_DSP_FILTER_NEXT3 (BIT_8 | BIT_9 | BIT_10) 760#define BCM540X_DSP_FILTER_NEXT2 (BIT_9 | BIT_10) 761#define BCM540X_DSP_FILTER_NEXT1 (BIT_8 | BIT_10) 762#define BCM540X_DSP_FILTER_NEXT0 BIT_10 763#define BCM540X_DSP_FILTER_ECHO (BIT_8 | BIT_9) 764#define BCM540X_DSP_FILTER_DFE BIT_9 765#define BCM540X_DSP_FILTER_FFE BIT_8 766 767#define BCM540X_DSP_CONTROL_ALL_FILTERS BIT_12 768 769#define BCM540X_DSP_SEL_CH_0 BIT_NONE 770#define BCM540X_DSP_SEL_CH_1 BIT_13 771#define BCM540X_DSP_SEL_CH_2 BIT_14 772#define BCM540X_DSP_SEL_CH_3 (BIT_13 | BIT_14) 773 774#define BCM540X_CONTROL_ALL_CHANNELS BIT_15 775 776 777/* Auxilliary Control Register (Shadow Register) */ 778#define BCM5401_AUX_CTRL 0x18 779 780#define BCM5401_SHADOW_SEL_MASK 0x7 781#define BCM5401_SHADOW_SEL_NORMAL 0x00 782#define BCM5401_SHADOW_SEL_10BASET 0x01 783#define BCM5401_SHADOW_SEL_POWER_CONTROL 0x02 784#define BCM5401_SHADOW_SEL_IP_PHONE 0x03 785#define BCM5401_SHADOW_SEL_MISC_TEST1 0x04 786#define BCM5401_SHADOW_SEL_MISC_TEST2 0x05 787#define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06 788 789 790/* Shadow register selector == '000' */ 791#define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3 792#define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4 793#define BCM5401_SHDW_NORMAL_DISABLE_LOW_PWR BIT_5 794#define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF BIT_6 795#define BCM5401_SHDW_NORMAL_DISABLE_PRF BIT_7 796#define BCM5401_SHDW_NORMAL_RX_SLICING_NORMAL BIT_NONE 797#define BCM5401_SHDW_NORMAL_RX_SLICING_4D BIT_8 798#define BCM5401_SHDW_NORMAL_RX_SLICING_3LVL_1D BIT_9 799#define BCM5401_SHDW_NORMAL_RX_SLICING_5LVL_1D (BIT_8 | BIT_9) 800#define BCM5401_SHDW_NORMAL_TX_6DB_CODING BIT_10 801#define BCM5401_SHDW_NORMAL_ENABLE_SM_DSP_CLOCK BIT_11 802#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_4NS BIT_NONE 803#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_5NS BIT_12 804#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_3NS BIT_13 805#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS (BIT_12 | BIT_13) 806#define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14 807#define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15 808 809 810/* Auxilliary status summary. */ 811#define BCM540X_AUX_STATUS_REG 0x19 812 813#define BCM540X_AUX_LINK_PASS BIT_2 814#define BCM540X_AUX_SPEED_MASK (BIT_8 | BIT_9 | BIT_10) 815#define BCM540X_AUX_10BASET_HD BIT_8 816#define BCM540X_AUX_10BASET_FD BIT_9 817#define BCM540X_AUX_100BASETX_HD (BIT_8 | BIT_9) 818#define BCM540X_AUX_100BASET4 BIT_10 819#define BCM540X_AUX_100BASETX_FD (BIT_8 | BIT_10) 820#define BCM540X_AUX_100BASET_HD (BIT_9 | BIT_10) 821#define BCM540X_AUX_100BASET_FD (BIT_8 | BIT_9 | BIT_10) 822 823 824/* Interrupt status. */ 825#define BCM540X_INT_STATUS_REG 0x1a 826 827#define BCM540X_INT_LINK_CHANGE BIT_1 828#define BCM540X_INT_SPEED_CHANGE BIT_2 829#define BCM540X_INT_DUPLEX_CHANGE BIT_3 830#define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10 831 832 833/* Interrupt mask register. */ 834#define BCM540X_INT_MASK_REG 0x1b 835 836/* BCM5461 x1c Shadow Control register */ 837#define BCM546X_1c_SHADOW_REG 0x1c 838 839#define BCM546X_1c_WR_EN 0x8000 /* shadow (1c) write enable bit mask */ 840 841#define BCM546X_1c_SPR_CTRL_1 0x0800 /* shadow (1c) reg 00010 addr */ 842#define BCM546X_1c_SP1_LINK_LED 0x0001 /* shadow (1c) reg 00010 link LED mode mask */ 843 844#define BCM546X_1c_SPR_CTRL_2 0x100C /* shadow (1c) reg 00100 addr */ 845#define BCM546X_1c_SP2_NRG_DET 0x0002 /* shadow (1c) reg 00100 energy detect bit mask */ 846 847 848 849/******************************************************************************/ 850/* Register definitions. */ 851/******************************************************************************/ 852 853typedef volatile LM_UINT8 T3_8BIT_REGISTER, *PT3_8BIT_REGISTER; 854typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER; 855typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER; 856 857typedef struct { 858 /* Big endian format. */ 859 T3_32BIT_REGISTER High; 860 T3_32BIT_REGISTER Low; 861} T3_64BIT_REGISTER, *PT3_64BIT_REGISTER; 862 863typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR; 864 865#define T3_NUM_OF_DMA_DESC 256 866#define T3_NUM_OF_MBUF 768 867 868typedef struct 869{ 870 T3_64BIT_REGISTER host_addr; 871 T3_32BIT_REGISTER nic_mbuf; 872 T3_16BIT_REGISTER len; 873 T3_16BIT_REGISTER cqid_sqid; 874 T3_32BIT_REGISTER flags; 875 T3_32BIT_REGISTER opaque1; 876 T3_32BIT_REGISTER opaque2; 877 T3_32BIT_REGISTER opaque3; 878}T3_DMA_DESC, *PT3_DMA_DESC; 879 880 881 882/******************************************************************************/ 883/* Ring control block. */ 884/******************************************************************************/ 885 886typedef struct { 887 T3_64BIT_REGISTER HostRingAddr; 888 889 union { 890 struct { 891#ifdef BIG_ENDIAN_HOST 892 T3_16BIT_REGISTER MaxLen; 893 T3_16BIT_REGISTER Flags; 894#else /* BIG_ENDIAN_HOST */ 895 T3_16BIT_REGISTER Flags; 896 T3_16BIT_REGISTER MaxLen; 897#endif 898 } s; 899 900 T3_32BIT_REGISTER MaxLen_Flags; 901 } u; 902 903 T3_32BIT_REGISTER NicRingAddr; 904} T3_RCB, *PT3_RCB; 905 906#define T3_RCB_FLAG_USE_EXT_RECV_BD BIT_0 907#define T3_RCB_FLAG_RING_DISABLED BIT_1 908 909 910 911/******************************************************************************/ 912/* Status block. */ 913/******************************************************************************/ 914 915/* 916 * Size of status block is actually 0x50 bytes. Use 0x80 bytes for 917 * cache line alignment. 918 */ 919#define T3_STATUS_BLOCK_SIZE 0x80 920 921typedef struct { 922 volatile LM_UINT32 Status; 923 #define STATUS_BLOCK_UPDATED BIT_0 924 #define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1 925 #define STATUS_BLOCK_ERROR BIT_2 926 927 volatile LM_UINT32 StatusTag; 928 929#ifdef BIG_ENDIAN_HOST 930 volatile LM_UINT16 RcvStdConIdx; 931 volatile LM_UINT16 RcvJumboConIdx; 932 933 volatile LM_UINT16 Reserved2; 934 volatile LM_UINT16 RcvMiniConIdx; 935 936 struct { 937 volatile LM_UINT16 SendConIdx; /* Send consumer index. */ 938 volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ 939 } Idx[16]; 940#else /* BIG_ENDIAN_HOST */ 941 volatile LM_UINT16 RcvJumboConIdx; 942 volatile LM_UINT16 RcvStdConIdx; 943 944 volatile LM_UINT16 RcvMiniConIdx; 945 volatile LM_UINT16 Reserved2; 946 947 struct { 948 volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ 949 volatile LM_UINT16 SendConIdx; /* Send consumer index. */ 950 } Idx[16]; 951#endif 952} T3_STATUS_BLOCK, *PT3_STATUS_BLOCK; 953 954 955 956/******************************************************************************/ 957/* Receive buffer descriptors. */ 958/******************************************************************************/ 959 960typedef struct { 961 T3_64BIT_HOST_ADDR HostAddr; 962 963#ifdef BIG_ENDIAN_HOST 964 volatile LM_UINT16 Index; 965 volatile LM_UINT16 Len; 966 967 volatile LM_UINT16 Type; 968 volatile LM_UINT16 Flags; 969 970 volatile LM_UINT16 IpCksum; 971 volatile LM_UINT16 TcpUdpCksum; 972 973 volatile LM_UINT16 ErrorFlag; 974 volatile LM_UINT16 VlanTag; 975#else /* BIG_ENDIAN_HOST */ 976 volatile LM_UINT16 Len; 977 volatile LM_UINT16 Index; 978 979 volatile LM_UINT16 Flags; 980 volatile LM_UINT16 Type; 981 982 volatile LM_UINT16 TcpUdpCksum; 983 volatile LM_UINT16 IpCksum; 984 985 volatile LM_UINT16 VlanTag; 986 volatile LM_UINT16 ErrorFlag; 987#endif 988 989 volatile LM_UINT32 Reserved; 990 volatile LM_UINT32 Opaque; 991} T3_RCV_BD, *PT3_RCV_BD; 992 993 994typedef struct { 995 T3_64BIT_HOST_ADDR HostAddr[3]; 996 997#ifdef BIG_ENDIAN_HOST 998 LM_UINT16 Len1; 999 LM_UINT16 Len2; 1000 1001 LM_UINT16 Len3; 1002 LM_UINT16 Reserved1; 1003#else /* BIG_ENDIAN_HOST */ 1004 LM_UINT16 Len2; 1005 LM_UINT16 Len1; 1006 1007 LM_UINT16 Reserved1; 1008 LM_UINT16 Len3; 1009#endif 1010 1011 T3_RCV_BD StdRcvBd; 1012} T3_EXT_RCV_BD, *PT3_EXT_RCV_BD; 1013 1014 1015/* Error flags. */ 1016#define RCV_BD_ERR_BAD_CRC 0x0001 1017#define RCV_BD_ERR_COLL_DETECT 0x0002 1018#define RCV_BD_ERR_LINK_LOST_DURING_PKT 0x0004 1019#define RCV_BD_ERR_PHY_DECODE_ERR 0x0008 1020#define RCV_BD_ERR_ODD_NIBBLED_RCVD_MII 0x0010 1021#define RCV_BD_ERR_MAC_ABORT 0x0020 1022#define RCV_BD_ERR_LEN_LT_64 0x0040 1023#define RCV_BD_ERR_TRUNC_NO_RESOURCES 0x0080 1024#define RCV_BD_ERR_GIANT_FRAME_RCVD 0x0100 1025 1026 1027/* Buffer descriptor flags. */ 1028#define RCV_BD_FLAG_END 0x0004 1029#define RCV_BD_FLAG_JUMBO_RING 0x0020 1030#define RCV_BD_FLAG_VLAN_TAG 0x0040 1031#define RCV_BD_FLAG_FRAME_HAS_ERROR 0x0400 1032#define RCV_BD_FLAG_MINI_RING 0x0800 1033#define RCV_BD_FLAG_IP_CHKSUM_FIELD 0x1000 1034#define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD 0x2000 1035#define RCV_BD_FLAG_TCP_PACKET 0x4000 1036 1037 1038 1039/******************************************************************************/ 1040/* Send buffer descriptor. */ 1041/******************************************************************************/ 1042 1043typedef struct { 1044 T3_64BIT_HOST_ADDR HostAddr; 1045 1046 union { 1047 struct { 1048#ifdef BIG_ENDIAN_HOST 1049 LM_UINT16 Len; 1050 LM_UINT16 Flags; 1051#else /* BIG_ENDIAN_HOST */ 1052 LM_UINT16 Flags; 1053 LM_UINT16 Len; 1054#endif 1055 } s1; 1056 1057 LM_UINT32 Len_Flags; 1058 } u1; 1059 1060 union { 1061 struct { 1062#ifdef BIG_ENDIAN_HOST 1063 LM_UINT16 Reserved; 1064 LM_UINT16 VlanTag; 1065#else /* BIG_ENDIAN_HOST */ 1066 LM_UINT16 VlanTag; 1067 LM_UINT16 Reserved; 1068#endif 1069 } s2; 1070 1071 LM_UINT32 VlanTag; 1072 } u2; 1073} T3_SND_BD, *PT3_SND_BD; 1074 1075 1076/* Send buffer descriptor flags. */ 1077#define SND_BD_FLAG_TCP_UDP_CKSUM 0x0001 1078#define SND_BD_FLAG_IP_CKSUM 0x0002 1079#define SND_BD_FLAG_END 0x0004 1080#define SND_BD_FLAG_IP_FRAG 0x0008 1081#define SND_BD_FLAG_IP_FRAG_END 0x0010 1082#define SND_BD_FLAG_VLAN_TAG 0x0040 1083#define SND_BD_FLAG_COAL_NOW 0x0080 1084#define SND_BD_FLAG_CPU_PRE_DMA 0x0100 1085#define SND_BD_FLAG_CPU_POST_DMA 0x0200 1086#define SND_BD_FLAG_INSERT_SRC_ADDR 0x1000 1087#define SND_BD_FLAG_CHOOSE_SRC_ADDR 0x6000 1088#define SND_BD_FLAG_DONT_GEN_CRC 0x8000 1089 1090/* MBUFs */ 1091typedef struct T3_MBUF_FRAME_DESC { 1092#ifdef BIG_ENDIAN_HOST 1093 LM_UINT32 status_control; 1094 union { 1095 struct { 1096 LM_UINT8 cqid; 1097 LM_UINT8 reserved1; 1098 LM_UINT16 length; 1099 }s1; 1100 LM_UINT32 word; 1101 }u1; 1102 union { 1103 struct 1104 { 1105 LM_UINT16 ip_hdr_start; 1106 LM_UINT16 tcp_udp_hdr_start; 1107 }s2; 1108 1109 LM_UINT32 word; 1110 }u2; 1111 1112 union { 1113 struct { 1114 LM_UINT16 data_start; 1115 LM_UINT16 vlan_id; 1116 }s3; 1117 1118 LM_UINT32 word; 1119 }u3; 1120 1121 union { 1122 struct { 1123 LM_UINT16 ip_checksum; 1124 LM_UINT16 tcp_udp_checksum; 1125 }s4; 1126 1127 LM_UINT32 word; 1128 }u4; 1129 1130 union { 1131 struct { 1132 LM_UINT16 pseudo_checksum; 1133 LM_UINT16 checksum_status; 1134 }s5; 1135 1136 LM_UINT32 word; 1137 }u5; 1138 1139 union { 1140 struct { 1141 LM_UINT16 rule_match; 1142 LM_UINT8 class; 1143 LM_UINT8 rupt; 1144 }s6; 1145 1146 LM_UINT32 word; 1147 }u6; 1148 1149 union { 1150 struct { 1151 LM_UINT16 reserved2; 1152 LM_UINT16 mbuf_num; 1153 }s7; 1154 1155 LM_UINT32 word; 1156 }u7; 1157 1158 LM_UINT32 reserved3; 1159 LM_UINT32 reserved4; 1160#else 1161 LM_UINT32 status_control; 1162 union { 1163 struct { 1164 LM_UINT16 length; 1165 LM_UINT8 reserved1; 1166 LM_UINT8 cqid; 1167 }s1; 1168 LM_UINT32 word; 1169 }u1; 1170 union { 1171 struct 1172 { 1173 LM_UINT16 tcp_udp_hdr_start; 1174 LM_UINT16 ip_hdr_start; 1175 }s2; 1176 1177 LM_UINT32 word; 1178 }u2; 1179 1180 union { 1181 struct { 1182 LM_UINT16 vlan_id; 1183 LM_UINT16 data_start; 1184 }s3; 1185 1186 LM_UINT32 word; 1187 }u3; 1188 1189 union { 1190 struct { 1191 LM_UINT16 tcp_udp_checksum; 1192 LM_UINT16 ip_checksum; 1193 }s4; 1194 1195 LM_UINT32 word; 1196 }u4; 1197 1198 union { 1199 struct { 1200 LM_UINT16 checksum_status; 1201 LM_UINT16 pseudo_checksum; 1202 }s5; 1203 1204 LM_UINT32 word; 1205 }u5; 1206 1207 union { 1208 struct { 1209 LM_UINT8 rupt; 1210 LM_UINT8 class; 1211 LM_UINT16 rule_match; 1212 }s6; 1213 1214 LM_UINT32 word; 1215 }u6; 1216 1217 union { 1218 struct { 1219 LM_UINT16 mbuf_num; 1220 LM_UINT16 reserved2; 1221 }s7; 1222 1223 LM_UINT32 word; 1224 }u7; 1225 1226 LM_UINT32 reserved3; 1227 LM_UINT32 reserved4; 1228#endif 1229}T3_MBUF_FRAME_DESC,*PT3_MBUF_FRAME_DESC; 1230 1231typedef struct T3_MBUF_HDR { 1232 union { 1233 struct { 1234 unsigned int C:1; 1235 unsigned int F:1; 1236 unsigned int reserved1:7; 1237 unsigned int next_mbuf:16; 1238 unsigned int length:7; 1239 }s1; 1240 1241 LM_UINT32 word; 1242 }u1; 1243 1244 LM_UINT32 next_frame_ptr; 1245}T3_MBUF_HDR, *PT3_MBUF_HDR; 1246 1247typedef struct T3_MBUF 1248{ 1249 T3_MBUF_HDR hdr; 1250 union 1251 { 1252 struct { 1253 T3_MBUF_FRAME_DESC frame_hdr; 1254 LM_UINT32 data[20]; 1255 }s1; 1256 1257 struct { 1258 LM_UINT32 data[30]; 1259 }s2; 1260 }body; 1261}T3_MBUF, *PT3_MBUF; 1262 1263#define T3_MBUF_BASE (T3_NIC_MBUF_POOL_ADDR >> 7) 1264#define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7) 1265 1266 1267 1268/******************************************************************************/ 1269/* Statistics block. */ 1270/******************************************************************************/ 1271 1272typedef struct { 1273 LM_UINT8 Reserved0[0x400-0x300]; 1274 1275 /* Statistics maintained by Receive MAC. */ 1276 T3_64BIT_REGISTER ifHCInOctets; 1277 T3_64BIT_REGISTER Reserved1; 1278 T3_64BIT_REGISTER etherStatsFragments; 1279 T3_64BIT_REGISTER ifHCInUcastPkts; 1280 T3_64BIT_REGISTER ifHCInMulticastPkts; 1281 T3_64BIT_REGISTER ifHCInBroadcastPkts; 1282 T3_64BIT_REGISTER dot3StatsFCSErrors; 1283 T3_64BIT_REGISTER dot3StatsAlignmentErrors; 1284 T3_64BIT_REGISTER xonPauseFramesReceived; 1285 T3_64BIT_REGISTER xoffPauseFramesReceived; 1286 T3_64BIT_REGISTER macControlFramesReceived; 1287 T3_64BIT_REGISTER xoffStateEntered; 1288 T3_64BIT_REGISTER dot3StatsFramesTooLong; 1289 T3_64BIT_REGISTER etherStatsJabbers; 1290 T3_64BIT_REGISTER etherStatsUndersizePkts; 1291 T3_64BIT_REGISTER inRangeLengthError; 1292 T3_64BIT_REGISTER outRangeLengthError; 1293 T3_64BIT_REGISTER etherStatsPkts64Octets; 1294 T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets; 1295 T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets; 1296 T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets; 1297 T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets; 1298 T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets; 1299 T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets; 1300 T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets; 1301 T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets; 1302 T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets; 1303 1304 T3_64BIT_REGISTER Unused1[37]; 1305 1306 /* Statistics maintained by Transmit MAC. */ 1307 T3_64BIT_REGISTER ifHCOutOctets; 1308 T3_64BIT_REGISTER Reserved2; 1309 T3_64BIT_REGISTER etherStatsCollisions; 1310 T3_64BIT_REGISTER outXonSent; 1311 T3_64BIT_REGISTER outXoffSent; 1312 T3_64BIT_REGISTER flowControlDone; 1313 T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors; 1314 T3_64BIT_REGISTER dot3StatsSingleCollisionFrames; 1315 T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames; 1316 T3_64BIT_REGISTER dot3StatsDeferredTransmissions; 1317 T3_64BIT_REGISTER Reserved3; 1318 T3_64BIT_REGISTER dot3StatsExcessiveCollisions; 1319 T3_64BIT_REGISTER dot3StatsLateCollisions; 1320 T3_64BIT_REGISTER dot3Collided2Times; 1321 T3_64BIT_REGISTER dot3Collided3Times; 1322 T3_64BIT_REGISTER dot3Collided4Times; 1323 T3_64BIT_REGISTER dot3Collided5Times; 1324 T3_64BIT_REGISTER dot3Collided6Times; 1325 T3_64BIT_REGISTER dot3Collided7Times; 1326 T3_64BIT_REGISTER dot3Collided8Times; 1327 T3_64BIT_REGISTER dot3Collided9Times; 1328 T3_64BIT_REGISTER dot3Collided10Times; 1329 T3_64BIT_REGISTER dot3Collided11Times; 1330 T3_64BIT_REGISTER dot3Collided12Times; 1331 T3_64BIT_REGISTER dot3Collided13Times; 1332 T3_64BIT_REGISTER dot3Collided14Times; 1333 T3_64BIT_REGISTER dot3Collided15Times; 1334 T3_64BIT_REGISTER ifHCOutUcastPkts; 1335 T3_64BIT_REGISTER ifHCOutMulticastPkts; 1336 T3_64BIT_REGISTER ifHCOutBroadcastPkts; 1337 T3_64BIT_REGISTER dot3StatsCarrierSenseErrors; 1338 T3_64BIT_REGISTER ifOutDiscards; 1339 T3_64BIT_REGISTER ifOutErrors; 1340 1341 T3_64BIT_REGISTER Unused2[31]; 1342 1343 /* Statistics maintained by Receive List Placement. */ 1344 T3_64BIT_REGISTER COSIfHCInPkts[16]; 1345 T3_64BIT_REGISTER COSFramesDroppedDueToFilters; 1346 T3_64BIT_REGISTER nicDmaWriteQueueFull; 1347 T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull; 1348 T3_64BIT_REGISTER nicNoMoreRxBDs; 1349 T3_64BIT_REGISTER ifInDiscards; 1350 T3_64BIT_REGISTER ifInErrors; 1351 T3_64BIT_REGISTER nicRecvThresholdHit; 1352 1353 T3_64BIT_REGISTER Unused3[9]; 1354 1355 /* Statistics maintained by Send Data Initiator. */ 1356 T3_64BIT_REGISTER COSIfHCOutPkts[16]; 1357 T3_64BIT_REGISTER nicDmaReadQueueFull; 1358 T3_64BIT_REGISTER nicDmaReadHighPriQueueFull; 1359 T3_64BIT_REGISTER nicSendDataCompQueueFull; 1360 1361 /* Statistics maintained by Host Coalescing. */ 1362 T3_64BIT_REGISTER nicRingSetSendProdIndex; 1363 T3_64BIT_REGISTER nicRingStatusUpdate; 1364 T3_64BIT_REGISTER nicInterrupts; 1365 T3_64BIT_REGISTER nicAvoidedInterrupts; 1366 T3_64BIT_REGISTER nicSendThresholdHit; 1367 1368 LM_UINT8 Reserved4[0xb00-0x9c0]; 1369} T3_STATS_BLOCK, *PT3_STATS_BLOCK; 1370 1371 1372 1373/******************************************************************************/ 1374/* PCI configuration registers. */ 1375/******************************************************************************/ 1376 1377typedef struct { 1378 T3_16BIT_REGISTER VendorId; 1379 T3_16BIT_REGISTER DeviceId; 1380 1381 T3_16BIT_REGISTER Command; 1382 T3_16BIT_REGISTER Status; 1383 1384 T3_32BIT_REGISTER ClassCodeRevId; 1385 1386 T3_8BIT_REGISTER CacheLineSize; 1387 T3_8BIT_REGISTER LatencyTimer; 1388 T3_8BIT_REGISTER HeaderType; 1389 T3_8BIT_REGISTER Bist; 1390 1391 T3_32BIT_REGISTER MemBaseAddrLow; 1392 T3_32BIT_REGISTER MemBaseAddrHigh; 1393 1394 LM_UINT8 Unused1[20]; 1395 1396 T3_16BIT_REGISTER SubsystemVendorId; 1397 T3_16BIT_REGISTER SubsystemId; 1398 1399 T3_32BIT_REGISTER RomBaseAddr; 1400 1401 T3_8BIT_REGISTER PciXCapiblityPtr; 1402 LM_UINT8 Unused2[7]; 1403 1404 T3_8BIT_REGISTER IntLine; 1405 T3_8BIT_REGISTER IntPin; 1406 T3_8BIT_REGISTER MinGnt; 1407 T3_8BIT_REGISTER MaxLat; 1408 1409 T3_8BIT_REGISTER PciXCapabilities; 1410 T3_8BIT_REGISTER PmCapabilityPtr; 1411 T3_16BIT_REGISTER PciXCommand; 1412 #define PXC_MAX_READ_BYTE_COUNT_MASK (BIT_3 | BIT_2) 1413 #define PXC_MAX_READ_BYTE_COUNT_512 (0) 1414 #define PXC_MAX_READ_BYTE_COUNT_1024 (BIT_2) 1415 #define PXC_MAX_READ_BYTE_COUNT_2048 (BIT_3) 1416 #define PXC_MAX_READ_BYTE_COUNT_4096 (BIT_3 | BIT_2) 1417 1418 T3_32BIT_REGISTER PciXStatus; 1419 1420 T3_8BIT_REGISTER PmCapabilityId; 1421 T3_8BIT_REGISTER VpdCapabilityPtr; 1422 T3_16BIT_REGISTER PmCapabilities; 1423 1424 T3_16BIT_REGISTER PmCtrlStatus; 1425 #define PM_CTRL_PME_STATUS BIT_15 1426 #define PM_CTRL_PME_ENABLE BIT_8 1427 #define PM_CTRL_PME_POWER_STATE_D0 0 1428 #define PM_CTRL_PME_POWER_STATE_D1 1 1429 #define PM_CTRL_PME_POWER_STATE_D2 2 1430 #define PM_CTRL_PME_POWER_STATE_D3H 3 1431 1432 T3_8BIT_REGISTER BridgeSupportExt; 1433 T3_8BIT_REGISTER PmData; 1434 1435 T3_8BIT_REGISTER VpdCapabilityId; 1436 T3_8BIT_REGISTER MsiCapabilityPtr; 1437 T3_16BIT_REGISTER VpdAddrFlag; 1438 #define VPD_FLAG_WRITE (1 << 15) 1439 #define VPD_FLAG_RW_MASK (1 << 15) 1440 #define VPD_FLAG_READ 0 1441 1442 1443 T3_32BIT_REGISTER VpdData; 1444 1445 T3_8BIT_REGISTER MsiCapabilityId; 1446 T3_8BIT_REGISTER NextCapabilityPtr; 1447 T3_16BIT_REGISTER MsiCtrl; 1448 #define MSI_CTRL_64BIT_CAP (1 << 7) 1449 #define MSI_CTRL_MSG_ENABLE(x) (x << 4) 1450 #define MSI_CTRL_MSG_CAP(x) (x << 1) 1451 #define MSI_CTRL_ENABLE (1 << 0) 1452 1453 1454 T3_32BIT_REGISTER MsiAddrLow; 1455 T3_32BIT_REGISTER MsiAddrHigh; 1456 1457 T3_16BIT_REGISTER MsiData; 1458 T3_16BIT_REGISTER Unused3; 1459 1460 T3_32BIT_REGISTER MiscHostCtrl; 1461 #define MISC_HOST_CTRL_CLEAR_INT BIT_0 1462 #define MISC_HOST_CTRL_MASK_PCI_INT BIT_1 1463 #define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2 1464 #define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3 1465 #define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4 1466 #define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5 1467 #define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6 1468 #define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7 1469 #define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8 1470 #define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9 1471 1472 T3_32BIT_REGISTER DmaReadWriteCtrl; 1473 #define DMA_CTRL_WRITE_CMD 0x70000000 1474 #define DMA_CTRL_WRITE_BOUNDARY_64_PCIE 0x10000000 1475 #define DMA_CTRL_WRITE_BOUNDARY_128_PCIE 0x30000000 1476 #define DMA_CTRL_WRITE_BOUNDARY_DISABLE_PCIE 0x70000000 1477 #define DMA_CTRL_READ_CMD 0x06000000 1478 1479 /* bits 21:19 */ 1480 #define DMA_CTRL_WRITE_PCIE_H20MARK_128 0x00180000 1481 #define DMA_CTRL_WRITE_PCIE_H20MARK_256 0x00380000 1482 1483 #define DMA_CTRL_PCIX_READ_WATERMARK_MASK (BIT_18 | BIT_17 | BIT_16) 1484 #define DMA_CTRL_PCIX_READ_WATERMARK_64 (0) 1485 #define DMA_CTRL_PCIX_READ_WATERMARK_128 (BIT_16) 1486 #define DMA_CTRL_PCIX_READ_WATERMARK_256 (BIT_17) 1487 #define DMA_CTRL_PCIX_READ_WATERMARK_384 (BIT_17 | BIT_16) 1488 #define DMA_CTRL_PCIX_READ_WATERMARK_512 (BIT_18) 1489 #define DMA_CTRL_PCIX_READ_WATERMARK_1024 (BIT_18 | BIT_16) 1490 #define DMA_CTRL_PCIX_READ_WATERMARK_1536X (BIT_18 | BIT_17) 1491 #define DMA_CTRL_PCIX_READ_WATERMARK_1536 (BIT_18 | BIT_17 | BIT_16) 1492 1493 #define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13) 1494 #define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0 1495 #define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11 1496 #define DMA_CTRL_WRITE_BOUNDARY_128_PCIX BIT_11 1497 #define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12 1498 #define DMA_CTRL_WRITE_BOUNDARY_256_PCIX BIT_12 1499 #define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11) 1500 #define DMA_CTRL_WRITE_BOUNDARY_384_PCIX (BIT_12 | BIT_11) 1501 #define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13 1502 #define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11) 1503 #define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12) 1504 #define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11) 1505 #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14 1506 1507 #define DMA_CTRL_READ_BOUNDARY_MASK (BIT_10 | BIT_9 | BIT_8) 1508 #define DMA_CTRL_READ_BOUNDARY_DISABLE 0 1509 #define DMA_CTRL_READ_BOUNDARY_16 BIT_8 1510 #define DMA_CTRL_READ_BOUNDARY_128_PCIX BIT_8 1511 #define DMA_CTRL_READ_BOUNDARY_32 BIT_9 1512 #define DMA_CTRL_READ_BOUNDARY_256_PCIX BIT_9 1513 #define DMA_CTRL_READ_BOUNDARY_64 (BIT_9 | BIT_8) 1514 #define DMA_CTRL_READ_BOUNDARY_384_PCIX (BIT_9 | BIT_8) 1515 #define DMA_CTRL_READ_BOUNDARY_128 BIT_10 1516 #define DMA_CTRL_READ_BOUNDARY_256 (BIT_10 | BIT_8) 1517 #define DMA_CTRL_READ_BOUNDARY_512 (BIT_10 | BIT_9) 1518 #define DMA_CTRL_READ_BOUNDARY_1024 (BIT_10 | BIT_9 | BIT_8) 1519 1520 T3_32BIT_REGISTER PciState; 1521 #define T3_PCI_STATE_FORCE_PCI_RESET BIT_0 1522 #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1 1523 #define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2 1524 #define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3 1525 #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 1526 #define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5 1527 #define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6 1528 #define T3_PCI_STATE_FLAT_VIEW BIT_8 1529 #define T3_PCI_STATE_RETRY_SAME_DMA BIT_13 1530 1531 T3_32BIT_REGISTER ClockCtrl; 1532 #define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11 1533 #define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10 1534 #define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9 1535 1536 T3_32BIT_REGISTER RegBaseAddr; 1537 1538 T3_32BIT_REGISTER MemWindowBaseAddr; 1539 1540#ifdef NIC_CPU_VIEW 1541 /* These registers are ONLY visible to NIC CPU */ 1542 T3_32BIT_REGISTER PowerConsumed; 1543 T3_32BIT_REGISTER PowerDissipated; 1544#else /* NIC_CPU_VIEW */ 1545 T3_32BIT_REGISTER RegData; 1546 T3_32BIT_REGISTER MemWindowData; 1547#endif /* !NIC_CPU_VIEW */ 1548 1549 T3_32BIT_REGISTER ModeCtrl; 1550 1551 T3_32BIT_REGISTER MiscCfg; 1552 1553 T3_32BIT_REGISTER MiscLocalCtrl; 1554 1555 T3_32BIT_REGISTER Unused4; 1556 1557 /* NOTE: Big/Little-endian clarification needed. Are these register */ 1558 /* in big or little endian formate. */ 1559 T3_64BIT_REGISTER StdRingProdIdx; 1560 T3_64BIT_REGISTER RcvRetRingConIdx; 1561 T3_64BIT_REGISTER SndProdIdx; 1562 1563 T3_32BIT_REGISTER Unused5[2]; /* 0xb0-0xb7 */ 1564 1565 T3_32BIT_REGISTER DualMacCtrl; /* 0xb8 */ 1566 #define T3_DUAL_MAC_CH_CTRL_MASK (BIT_1 | BIT_0) 1567 #define T3_DUAL_MAC_ID BIT_2 1568 1569 T3_32BIT_REGISTER MacMessageExchangeOutput; /* 0xbc */ 1570 T3_32BIT_REGISTER MacMessageExchangeInput; /* 0xc0 */ 1571 1572 T3_32BIT_REGISTER FunctionEventMask; /* 0xc4 */ 1573 1574 T3_32BIT_REGISTER Unused6[4]; /* 0xc8-0xd7 */ 1575 1576 T3_32BIT_REGISTER DeviceCtrl; /* 0xd8 */ 1577 #define MAX_PAYLOAD_SIZE_MASK 0x0e0 1578 1579 LM_UINT8 Unused7[36]; 1580 1581} T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION; 1582 1583#define PCIX_CMD_MAX_SPLIT_MASK 0x00700000 1584#define PCIX_CMD_MAX_SPLIT_SHL 20 1585#define PCIX_CMD_MAX_BURST_MASK 0x000c0000 1586#define PCIX_CMD_MAX_BURST_SHL 18 1587#define PCIX_CMD_MAX_BURST_CPIOB 2 1588 1589/******************************************************************************/ 1590/* Mac control registers. */ 1591/******************************************************************************/ 1592 1593typedef struct { 1594 /* MAC mode control. */ 1595 T3_32BIT_REGISTER Mode; 1596 #define MAC_MODE_GLOBAL_RESET BIT_0 1597 #define MAC_MODE_HALF_DUPLEX BIT_1 1598 #define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3) 1599 #define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3) 1600 #define MAC_MODE_PORT_MODE_GMII BIT_3 1601 #define MAC_MODE_PORT_MODE_MII BIT_2 1602 #define MAC_MODE_PORT_MODE_NONE BIT_NONE 1603 #define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4 1604 #define MAC_MODE_TAGGED_MAC_CONTROL BIT_7 1605 #define MAC_MODE_TX_BURSTING BIT_8 1606 #define MAC_MODE_MAX_DEFER BIT_9 1607 #define MAC_MODE_LINK_POLARITY BIT_10 1608 #define MAC_MODE_ENABLE_RX_STATISTICS BIT_11 1609 #define MAC_MODE_CLEAR_RX_STATISTICS BIT_12 1610 #define MAC_MODE_FLUSH_RX_STATISTICS BIT_13 1611 #define MAC_MODE_ENABLE_TX_STATISTICS BIT_14 1612 #define MAC_MODE_CLEAR_TX_STATISTICS BIT_15 1613 #define MAC_MODE_FLUSH_TX_STATISTICS BIT_16 1614 #define MAC_MODE_SEND_CONFIGS BIT_17 1615 #define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18 1616 #define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19 1617 #define MAC_MODE_ENABLE_MIP BIT_20 1618 #define MAC_MODE_ENABLE_TDE BIT_21 1619 #define MAC_MODE_ENABLE_RDE BIT_22 1620 #define MAC_MODE_ENABLE_FHDE BIT_23 1621 1622 /* MAC status */ 1623 T3_32BIT_REGISTER Status; 1624 #define MAC_STATUS_PCS_SYNCED BIT_0 1625 #define MAC_STATUS_SIGNAL_DETECTED BIT_1 1626 #define MAC_STATUS_RECEIVING_CFG BIT_2 1627 #define MAC_STATUS_CFG_CHANGED BIT_3 1628 #define MAC_STATUS_SYNC_CHANGED BIT_4 1629 #define MAC_STATUS_PORT_DECODE_ERROR BIT_10 1630 #define MAC_STATUS_LINK_STATE_CHANGED BIT_12 1631 #define MAC_STATUS_MI_COMPLETION BIT_22 1632 #define MAC_STATUS_MI_INTERRUPT BIT_23 1633 #define MAC_STATUS_AP_ERROR BIT_24 1634 #define MAC_STATUS_ODI_ERROR BIT_25 1635 #define MAC_STATUS_RX_STATS_OVERRUN BIT_26 1636 #define MAC_STATUS_TX_STATS_OVERRUN BIT_27 1637 1638 /* Event Enable */ 1639 T3_32BIT_REGISTER MacEvent; 1640 #define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10 1641 #define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12 1642 #define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22 1643 #define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23 1644 #define MAC_EVENT_ENABLE_AP_ERROR BIT_24 1645 #define MAC_EVENT_ENABLE_ODI_ERROR BIT_25 1646 #define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26 1647 #define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27 1648 1649 /* Led control. */ 1650 T3_32BIT_REGISTER LedCtrl; 1651 #define LED_CTRL_OVERRIDE_LINK_LED BIT_0 1652 #define LED_CTRL_1000MBPS_LED_ON BIT_1 1653 #define LED_CTRL_100MBPS_LED_ON BIT_2 1654 #define LED_CTRL_10MBPS_LED_ON BIT_3 1655 #define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4 1656 #define LED_CTRL_BLINK_TRAFFIC_LED BIT_5 1657 #define LED_CTRL_TRAFFIC_LED BIT_6 1658 #define LED_CTRL_1000MBPS_LED_STATUS BIT_7 1659 #define LED_CTRL_100MBPS_LED_STATUS BIT_8 1660 #define LED_CTRL_10MBPS_LED_STATUS BIT_9 1661 #define LED_CTRL_TRAFFIC_LED_STATUS BIT_10 1662 #define LED_CTRL_MAC_MODE BIT_NONE 1663 #define LED_CTRL_PHY_MODE_1 BIT_11 1664 #define LED_CTRL_PHY_MODE_2 BIT_12 1665 #define LED_CTRL_SHASTA_MAC_MODE BIT_13 1666 #define LED_CTRL_SHARED_TRAFFIC_LINK BIT_14 1667 #define LED_CTRL_WIRELESS_COMBO BIT_15 1668 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 1669 #define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19 1670 #define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31 1671 1672 /* MAC addresses. */ 1673 struct { 1674 T3_32BIT_REGISTER High; /* Upper 2 bytes. */ 1675 T3_32BIT_REGISTER Low; /* Lower 4 bytes. */ 1676 } MacAddr[4]; 1677 1678 /* ACPI Mbuf pointer. */ 1679 T3_32BIT_REGISTER AcpiMbufPtr; 1680 1681 /* ACPI Length and Offset. */ 1682 T3_32BIT_REGISTER AcpiLengthOffset; 1683 #define ACPI_LENGTH_MASK 0xffff 1684 #define ACPI_OFFSET_MASK 0x0fff0000 1685 #define ACPI_LENGTH(x) x 1686 #define ACPI_OFFSET(x) ((x) << 16) 1687 1688 /* Transmit random backoff. */ 1689 T3_32BIT_REGISTER TxBackoffSeed; 1690 #define MAC_TX_BACKOFF_SEED_MASK 0x3ff 1691 1692 /* Receive MTU */ 1693 T3_32BIT_REGISTER MtuSize; 1694 #define MAC_RX_MTU_MASK 0xffff 1695 1696 /* Gigabit PCS Test. */ 1697 T3_32BIT_REGISTER PcsTest; 1698 #define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff 1699 #define MAC_PCS_TEST_ENABLE BIT_20 1700 1701 /* Transmit Gigabit Auto-Negotiation. */ 1702 T3_32BIT_REGISTER TxAutoNeg; 1703 #define MAC_AN_TX_AN_DATA_MASK 0xffff 1704 1705 /* Receive Gigabit Auto-Negotiation. */ 1706 T3_32BIT_REGISTER RxAutoNeg; 1707 #define MAC_AN_RX_AN_DATA_MASK 0xffff 1708 1709 /* MI Communication. */ 1710 T3_32BIT_REGISTER MiCom; 1711 #define MI_COM_CMD_MASK (BIT_26 | BIT_27) 1712 #define MI_COM_CMD_WRITE BIT_26 1713 #define MI_COM_CMD_READ BIT_27 1714 #define MI_COM_READ_FAILED BIT_28 1715 #define MI_COM_START BIT_29 1716 #define MI_COM_BUSY BIT_29 1717 1718 #define MI_COM_PHY_ADDR_MASK 0x1f 1719 #define MI_COM_FIRST_PHY_ADDR_BIT 21 1720 1721 #define MI_COM_PHY_REG_ADDR_MASK 0x1f 1722 #define MI_COM_FIRST_PHY_REG_ADDR_BIT 16 1723 1724 #define MI_COM_PHY_DATA_MASK 0xffff 1725 1726 /* MI Status. */ 1727 T3_32BIT_REGISTER MiStatus; 1728 #define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0 1729 #define MI_STATUS_10MBPS BIT_1 1730 1731 /* MI Mode. */ 1732 T3_32BIT_REGISTER MiMode; 1733 #define MI_MODE_CLOCK_SPEED_10MHZ BIT_0 1734 #define MI_MODE_USE_SHORT_PREAMBLE BIT_1 1735 #define MI_MODE_AUTO_POLLING_ENABLE BIT_4 1736 #define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15 1737 1738 /* Auto-polling status. */ 1739 T3_32BIT_REGISTER AutoPollStatus; 1740 #define AUTO_POLL_ERROR BIT_0 1741 1742 /* Transmit MAC mode. */ 1743 T3_32BIT_REGISTER TxMode; 1744 #define TX_MODE_RESET BIT_0 1745 #define TX_MODE_ENABLE BIT_1 1746 #define TX_MODE_ENABLE_FLOW_CONTROL BIT_4 1747 #define TX_MODE_ENABLE_BIG_BACKOFF BIT_5 1748 #define TX_MODE_ENABLE_LONG_PAUSE BIT_6 1749 1750 /* Transmit MAC status. */ 1751 T3_32BIT_REGISTER TxStatus; 1752 #define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0 1753 #define TX_STATUS_SENT_XOFF BIT_1 1754 #define TX_STATUS_SENT_XON BIT_2 1755 #define TX_STATUS_LINK_UP BIT_3 1756 #define TX_STATUS_ODI_UNDERRUN BIT_4 1757 #define TX_STATUS_ODI_OVERRUN BIT_5 1758 1759 /* Transmit MAC length. */ 1760 T3_32BIT_REGISTER TxLengths; 1761 #define TX_LEN_SLOT_TIME_MASK 0xff 1762 #define TX_LEN_IPG_MASK 0x0f00 1763 #define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13) 1764 1765 /* Receive MAC mode. */ 1766 T3_32BIT_REGISTER RxMode; 1767 #define RX_MODE_RESET BIT_0 1768 #define RX_MODE_ENABLE BIT_1 1769 #define RX_MODE_ENABLE_FLOW_CONTROL BIT_2 1770 #define RX_MODE_KEEP_MAC_CONTROL BIT_3 1771 #define RX_MODE_KEEP_PAUSE BIT_4 1772 #define RX_MODE_ACCEPT_OVERSIZED BIT_5 1773 #define RX_MODE_ACCEPT_RUNTS BIT_6 1774 #define RX_MODE_LENGTH_CHECK BIT_7 1775 #define RX_MODE_PROMISCUOUS_MODE BIT_8 1776 #define RX_MODE_NO_CRC_CHECK BIT_9 1777 #define RX_MODE_KEEP_VLAN_TAG BIT_10 1778 1779 /* Receive MAC status. */ 1780 T3_32BIT_REGISTER RxStatus; 1781 #define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0 1782 #define RX_STATUS_XOFF_RECEIVED BIT_1 1783 #define RX_STATUS_XON_RECEIVED BIT_2 1784 1785 /* Hash registers. */ 1786 T3_32BIT_REGISTER HashReg[4]; 1787 1788 /* Receive placement rules registers. */ 1789 struct { 1790 T3_32BIT_REGISTER Rule; 1791 T3_32BIT_REGISTER Value; 1792 } RcvRules[16]; 1793 1794 #define RCV_DISABLE_RULE_MASK 0x7fffffff 1795 1796 #define RCV_RULE1_REJECT_BROADCAST_IDX 0x00 1797 #define REJECT_BROADCAST_RULE1_RULE 0xc2000000 1798 #define REJECT_BROADCAST_RULE1_VALUE 0xffffffff 1799 1800 #define RCV_RULE2_REJECT_BROADCAST_IDX 0x01 1801 #define REJECT_BROADCAST_RULE2_RULE 0x86000004 1802 #define REJECT_BROADCAST_RULE2_VALUE 0xffffffff 1803 1804#if INCLUDE_5701_AX_FIX 1805 #define RCV_LAST_RULE_IDX 0x04 1806#else 1807 #define RCV_LAST_RULE_IDX 0x02 1808#endif 1809 1810 T3_32BIT_REGISTER RcvRuleCfg; 1811 #define RX_RULE_DEFAULT_CLASS (1 << 3) 1812 1813 T3_32BIT_REGISTER LowWaterMarkMaxRxFrame; 1814 1815 LM_UINT8 Reserved1[24]; 1816 1817 T3_32BIT_REGISTER HashRegU[4]; 1818 1819 struct { 1820 T3_32BIT_REGISTER High; 1821 T3_32BIT_REGISTER Low; 1822 } MacAddrExt[12]; 1823 1824 T3_32BIT_REGISTER SerdesCfg; 1825 T3_32BIT_REGISTER SerdesStatus; 1826 1827 LM_UINT8 Reserved2[24]; 1828 1829 T3_32BIT_REGISTER SgDigControl; 1830 T3_32BIT_REGISTER SgDigStatus; 1831 1832 LM_UINT8 Reserved3[72]; 1833 1834 volatile LM_UINT8 TxMacState[16]; 1835 volatile LM_UINT8 RxMacState[20]; 1836 1837 LM_UINT8 Reserved4[476]; 1838 1839 T3_32BIT_REGISTER ifHCOutOctets; 1840 T3_32BIT_REGISTER Reserved5; 1841 T3_32BIT_REGISTER etherStatsCollisions; 1842 T3_32BIT_REGISTER outXonSent; 1843 T3_32BIT_REGISTER outXoffSent; 1844 T3_32BIT_REGISTER Reserved6; 1845 T3_32BIT_REGISTER dot3StatsInternalMacTransmitErrors; 1846 T3_32BIT_REGISTER dot3StatsSingleCollisionFrames; 1847 T3_32BIT_REGISTER dot3StatsMultipleCollisionFrames; 1848 T3_32BIT_REGISTER dot3StatsDeferredTransmissions; 1849 T3_32BIT_REGISTER Reserved7; 1850 T3_32BIT_REGISTER dot3StatsExcessiveCollisions; 1851 T3_32BIT_REGISTER dot3StatsLateCollisions; 1852 T3_32BIT_REGISTER Reserved8[14]; 1853 T3_32BIT_REGISTER ifHCOutUcastPkts; 1854 T3_32BIT_REGISTER ifHCOutMulticastPkts; 1855 T3_32BIT_REGISTER ifHCOutBroadcastPkts; 1856 T3_32BIT_REGISTER Reserved9[2]; 1857 T3_32BIT_REGISTER ifHCInOctets; 1858 T3_32BIT_REGISTER Reserved10; 1859 T3_32BIT_REGISTER etherStatsFragments; 1860 T3_32BIT_REGISTER ifHCInUcastPkts; 1861 T3_32BIT_REGISTER ifHCInMulticastPkts; 1862 T3_32BIT_REGISTER ifHCInBroadcastPkts; 1863 T3_32BIT_REGISTER dot3StatsFCSErrors; 1864 T3_32BIT_REGISTER dot3StatsAlignmentErrors; 1865 T3_32BIT_REGISTER xonPauseFramesReceived; 1866 T3_32BIT_REGISTER xoffPauseFramesReceived; 1867 T3_32BIT_REGISTER macControlFramesReceived; 1868 T3_32BIT_REGISTER xoffStateEntered; 1869 T3_32BIT_REGISTER dot3StatsFramesTooLong; 1870 T3_32BIT_REGISTER etherStatsJabbers; 1871 T3_32BIT_REGISTER etherStatsUndersizePkts; 1872 1873 T3_32BIT_REGISTER Reserved11[209]; 1874 1875} T3_MAC_CONTROL, *PT3_MAC_CONTROL; 1876 1877 1878 1879/******************************************************************************/ 1880/* Send data initiator control registers. */ 1881/******************************************************************************/ 1882 1883typedef struct { 1884 T3_32BIT_REGISTER Mode; 1885 #define T3_SND_DATA_IN_MODE_RESET BIT_0 1886 #define T3_SND_DATA_IN_MODE_ENABLE BIT_1 1887 #define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2 1888 1889 T3_32BIT_REGISTER Status; 1890 #define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2 1891 1892 T3_32BIT_REGISTER StatsCtrl; 1893 #define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0 1894 #define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1 1895 #define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2 1896 #define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3 1897 #define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4 1898 1899 T3_32BIT_REGISTER StatsEnableMask; 1900 1901 T3_32BIT_REGISTER StatsIncMask; 1902 1903 LM_UINT8 Reserved[108]; 1904 1905 T3_32BIT_REGISTER ClassOfServCnt[16]; 1906 T3_32BIT_REGISTER DmaReadQFullCnt; 1907 T3_32BIT_REGISTER DmaPriorityReadQFullCnt; 1908 T3_32BIT_REGISTER SdcQFullCnt; 1909 1910 T3_32BIT_REGISTER NicRingSetSendProdIdxCnt; 1911 T3_32BIT_REGISTER StatusUpdatedCnt; 1912 T3_32BIT_REGISTER InterruptsCnt; 1913 T3_32BIT_REGISTER AvoidInterruptsCnt; 1914 T3_32BIT_REGISTER SendThresholdHitCnt; 1915 1916 /* Unused space. */ 1917 LM_UINT8 Unused[800]; 1918} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR; 1919 1920 1921 1922/******************************************************************************/ 1923/* Send data completion control registers. */ 1924/******************************************************************************/ 1925 1926typedef struct { 1927 T3_32BIT_REGISTER Mode; 1928 #define SND_DATA_COMP_MODE_RESET BIT_0 1929 #define SND_DATA_COMP_MODE_ENABLE BIT_1 1930 1931 /* Unused space. */ 1932 LM_UINT8 Unused[1020]; 1933} T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION; 1934 1935 1936 1937/******************************************************************************/ 1938/* Send BD Ring Selector Control Registers. */ 1939/******************************************************************************/ 1940 1941typedef struct { 1942 T3_32BIT_REGISTER Mode; 1943 #define SND_BD_SEL_MODE_RESET BIT_0 1944 #define SND_BD_SEL_MODE_ENABLE BIT_1 1945 #define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2 1946 1947 T3_32BIT_REGISTER Status; 1948 #define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2 1949 1950 T3_32BIT_REGISTER HwDiag; 1951 1952 /* Unused space. */ 1953 LM_UINT8 Unused1[52]; 1954 1955 /* Send BD Ring Selector Local NIC Send BD Consumer Index. */ 1956 T3_32BIT_REGISTER NicSendBdSelConIdx[16]; 1957 1958 /* Unused space. */ 1959 LM_UINT8 Unused2[896]; 1960} T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR; 1961 1962 1963 1964/******************************************************************************/ 1965/* Send BD initiator control registers. */ 1966/******************************************************************************/ 1967 1968typedef struct { 1969 T3_32BIT_REGISTER Mode; 1970 #define SND_BD_IN_MODE_RESET BIT_0 1971 #define SND_BD_IN_MODE_ENABLE BIT_1 1972 #define SND_BD_IN_MODE_ATTN_ENABLE BIT_2 1973 1974 T3_32BIT_REGISTER Status; 1975 #define SND_BD_IN_STATUS_ERROR_ATTN BIT_2 1976 1977 /* Send BD initiator local NIC send BD producer index. */ 1978 T3_32BIT_REGISTER NicSendBdInProdIdx[16]; 1979 1980 /* Unused space. */ 1981 LM_UINT8 Unused2[952]; 1982} T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR; 1983 1984 1985 1986/******************************************************************************/ 1987/* Send BD Completion Control. */ 1988/******************************************************************************/ 1989 1990typedef struct { 1991 T3_32BIT_REGISTER Mode; 1992 #define SND_BD_COMP_MODE_RESET BIT_0 1993 #define SND_BD_COMP_MODE_ENABLE BIT_1 1994 #define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2 1995 1996 /* Unused space. */ 1997 LM_UINT8 Unused2[1020]; 1998} T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION; 1999 2000 2001 2002/******************************************************************************/ 2003/* Receive list placement control registers. */ 2004/******************************************************************************/ 2005 2006typedef struct { 2007 /* Mode. */ 2008 T3_32BIT_REGISTER Mode; 2009 #define RCV_LIST_PLMT_MODE_RESET BIT_0 2010 #define RCV_LIST_PLMT_MODE_ENABLE BIT_1 2011 #define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2 2012 #define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3 2013 #define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4 2014 2015 /* Status. */ 2016 T3_32BIT_REGISTER Status; 2017 #define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2 2018 #define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3 2019 #define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4 2020 2021 /* Receive selector list lock register. */ 2022 T3_32BIT_REGISTER Lock; 2023 #define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff 2024 #define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000 2025 2026 /* Selector non-empty bits. */ 2027 T3_32BIT_REGISTER NonEmptyBits; 2028 #define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff 2029 2030 /* Receive list placement configuration register. */ 2031 T3_32BIT_REGISTER Config; 2032 2033 /* Receive List Placement statistics Control. */ 2034 T3_32BIT_REGISTER StatsCtrl; 2035#define RCV_LIST_STATS_ENABLE BIT_0 2036#define RCV_LIST_STATS_FAST_UPDATE BIT_1 2037 2038 /* Receive List Placement statistics Enable Mask. */ 2039 T3_32BIT_REGISTER StatsEnableMask; 2040 #define T3_DISABLE_LONG_BURST_READ_DYN_FIX BIT_22 2041 2042 /* Receive List Placement statistics Increment Mask. */ 2043 T3_32BIT_REGISTER StatsIncMask; 2044 2045 /* Unused space. */ 2046 LM_UINT8 Unused1[224]; 2047 2048 struct { 2049 T3_32BIT_REGISTER Head; 2050 T3_32BIT_REGISTER Tail; 2051 T3_32BIT_REGISTER Count; 2052 2053 /* Unused space. */ 2054 LM_UINT8 Unused[4]; 2055 } RcvSelectorList[16]; 2056 2057 /* Local statistics counter. */ 2058 T3_32BIT_REGISTER ClassOfServCnt[16]; 2059 2060 T3_32BIT_REGISTER DropDueToFilterCnt; 2061 T3_32BIT_REGISTER DmaWriteQFullCnt; 2062 T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt; 2063 T3_32BIT_REGISTER NoMoreReceiveBdCnt; 2064 T3_32BIT_REGISTER IfInDiscardsCnt; 2065 T3_32BIT_REGISTER IfInErrorsCnt; 2066 T3_32BIT_REGISTER RcvThresholdHitCnt; 2067 2068 /* Another unused space. */ 2069 LM_UINT8 Unused2[420]; 2070} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT; 2071 2072 2073 2074/******************************************************************************/ 2075/* Receive Data and Receive BD Initiator Control. */ 2076/******************************************************************************/ 2077 2078typedef struct { 2079 /* Mode. */ 2080 T3_32BIT_REGISTER Mode; 2081 #define RCV_DATA_BD_IN_MODE_RESET BIT_0 2082 #define RCV_DATA_BD_IN_MODE_ENABLE BIT_1 2083 #define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2 2084 #define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3 2085 #define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4 2086 2087 /* Status. */ 2088 T3_32BIT_REGISTER Status; 2089 #define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2 2090 #define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3 2091 #define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4 2092 2093 /* Split frame minium size. */ 2094 T3_32BIT_REGISTER SplitFrameMinSize; 2095 2096 /* Unused space. */ 2097 LM_UINT8 Unused1[0x2440-0x240c]; 2098 2099 /* Receive RCBs. */ 2100 T3_RCB JumboRcvRcb; 2101 T3_RCB StdRcvRcb; 2102 T3_RCB MiniRcvRcb; 2103 2104 /* Receive Data and Receive BD Ring Initiator Local NIC Receive */ 2105 /* BD Consumber Index. */ 2106 T3_32BIT_REGISTER NicJumboConIdx; 2107 T3_32BIT_REGISTER NicStdConIdx; 2108 T3_32BIT_REGISTER NicMiniConIdx; 2109 2110 /* Unused space. */ 2111 LM_UINT8 Unused2[4]; 2112 2113 /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */ 2114 T3_32BIT_REGISTER RcvDataBdProdIdx[16]; 2115 2116 /* Receive Data and Receive BD Initiator Hardware Diagnostic. */ 2117 T3_32BIT_REGISTER HwDiag; 2118 2119 /* Unused space. */ 2120 LM_UINT8 Unused3[828]; 2121} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR; 2122 2123 2124 2125/******************************************************************************/ 2126/* Receive Data Completion Control Registes. */ 2127/******************************************************************************/ 2128 2129typedef struct { 2130 T3_32BIT_REGISTER Mode; 2131 #define RCV_DATA_COMP_MODE_RESET BIT_0 2132 #define RCV_DATA_COMP_MODE_ENABLE BIT_1 2133 #define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2 2134 2135 /* Unused spaced. */ 2136 LM_UINT8 Unused[1020]; 2137} T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION; 2138 2139 2140 2141/******************************************************************************/ 2142/* Receive BD Initiator Control. */ 2143/******************************************************************************/ 2144 2145typedef struct { 2146 T3_32BIT_REGISTER Mode; 2147 #define RCV_BD_IN_MODE_RESET BIT_0 2148 #define RCV_BD_IN_MODE_ENABLE BIT_1 2149 #define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2 2150 2151 T3_32BIT_REGISTER Status; 2152 #define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2 2153 2154 T3_32BIT_REGISTER NicJumboRcvProdIdx; 2155 T3_32BIT_REGISTER NicStdRcvProdIdx; 2156 T3_32BIT_REGISTER NicMiniRcvProdIdx; 2157 2158 T3_32BIT_REGISTER MiniRcvThreshold; 2159 T3_32BIT_REGISTER StdRcvThreshold; 2160 T3_32BIT_REGISTER JumboRcvThreshold; 2161 2162 /* Unused space. */ 2163 LM_UINT8 Unused[992]; 2164} T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR; 2165 2166 2167 2168/******************************************************************************/ 2169/* Receive BD Completion Control Registers. */ 2170/******************************************************************************/ 2171 2172typedef struct { 2173 T3_32BIT_REGISTER Mode; 2174 #define RCV_BD_COMP_MODE_RESET BIT_0 2175 #define RCV_BD_COMP_MODE_ENABLE BIT_1 2176 #define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2 2177 2178 T3_32BIT_REGISTER Status; 2179 #define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2 2180 2181 T3_32BIT_REGISTER NicJumboRcvBdProdIdx; 2182 T3_32BIT_REGISTER NicStdRcvBdProdIdx; 2183 T3_32BIT_REGISTER NicMiniRcvBdProdIdx; 2184 2185 /* Unused space. */ 2186 LM_UINT8 Unused[1004]; 2187} T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION; 2188 2189 2190 2191/******************************************************************************/ 2192/* Receive list selector control register. */ 2193/******************************************************************************/ 2194 2195typedef struct { 2196 T3_32BIT_REGISTER Mode; 2197 #define RCV_LIST_SEL_MODE_RESET BIT_0 2198 #define RCV_LIST_SEL_MODE_ENABLE BIT_1 2199 #define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2 2200 2201 T3_32BIT_REGISTER Status; 2202 #define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2 2203 2204 /* Unused space. */ 2205 LM_UINT8 Unused[1016]; 2206} T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR; 2207 2208 2209 2210/******************************************************************************/ 2211/* Mbuf cluster free registers. */ 2212/******************************************************************************/ 2213 2214typedef struct { 2215 T3_32BIT_REGISTER Mode; 2216#define MBUF_CLUSTER_FREE_MODE_RESET BIT_0 2217#define MBUF_CLUSTER_FREE_MODE_ENABLE BIT_1 2218 2219 T3_32BIT_REGISTER Status; 2220 2221 /* Unused space. */ 2222 LM_UINT8 Unused[1016]; 2223} T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE; 2224 2225 2226 2227/******************************************************************************/ 2228/* Host coalescing control registers. */ 2229/******************************************************************************/ 2230 2231typedef struct { 2232 /* Mode. */ 2233 T3_32BIT_REGISTER Mode; 2234 #define HOST_COALESCE_RESET BIT_0 2235 #define HOST_COALESCE_ENABLE BIT_1 2236 #define HOST_COALESCE_ATTN BIT_2 2237 #define HOST_COALESCE_NOW BIT_3 2238 #define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE 2239 #define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7 2240 #define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8 2241 #define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9 2242 #define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10 2243 #define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11 2244 #define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12 2245 2246 /* Status. */ 2247 T3_32BIT_REGISTER Status; 2248 #define HOST_COALESCE_ERROR_ATTN BIT_2 2249 2250 /* Receive coalescing ticks. */ 2251 T3_32BIT_REGISTER RxCoalescingTicks; 2252 2253 /* Send coalescing ticks. */ 2254 T3_32BIT_REGISTER TxCoalescingTicks; 2255 2256 /* Receive max coalesced frames. */ 2257 T3_32BIT_REGISTER RxMaxCoalescedFrames; 2258 2259 /* Send max coalesced frames. */ 2260 T3_32BIT_REGISTER TxMaxCoalescedFrames; 2261 2262 /* Receive coalescing ticks during interrupt. */ 2263 T3_32BIT_REGISTER RxCoalescedTickDuringInt; 2264 2265 /* Send coalescing ticks during interrupt. */ 2266 T3_32BIT_REGISTER TxCoalescedTickDuringInt; 2267 2268 /* Receive max coalesced frames during interrupt. */ 2269 T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt; 2270 2271 /* Send max coalesced frames during interrupt. */ 2272 T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt; 2273 2274 /* Statistics tick. */ 2275 T3_32BIT_REGISTER StatsCoalescingTicks; 2276 2277 /* Unused space. */ 2278 LM_UINT8 Unused2[4]; 2279 2280 /* Statistics host address. */ 2281 T3_64BIT_REGISTER StatsBlkHostAddr; 2282 2283 /* Status block host address.*/ 2284 T3_64BIT_REGISTER StatusBlkHostAddr; 2285 2286 /* Statistics NIC address. */ 2287 T3_32BIT_REGISTER StatsBlkNicAddr; 2288 2289 /* Statust block NIC address. */ 2290 T3_32BIT_REGISTER StatusBlkNicAddr; 2291 2292 /* Flow attention registers. */ 2293 T3_32BIT_REGISTER FlowAttn; 2294 2295 /* Unused space. */ 2296 LM_UINT8 Unused3[4]; 2297 2298 T3_32BIT_REGISTER NicJumboRcvBdConIdx; 2299 T3_32BIT_REGISTER NicStdRcvBdConIdx; 2300 T3_32BIT_REGISTER NicMiniRcvBdConIdx; 2301 2302 /* Unused space. */ 2303 LM_UINT8 Unused4[36]; 2304 2305 T3_32BIT_REGISTER NicRetProdIdx[16]; 2306 T3_32BIT_REGISTER NicSndBdConIdx[16]; 2307 2308 /* Unused space. */ 2309 LM_UINT8 Unused5[768]; 2310} T3_HOST_COALESCING, *PT3_HOST_COALESCING; 2311 2312 2313 2314/******************************************************************************/ 2315/* Memory arbiter registers. */ 2316/******************************************************************************/ 2317 2318typedef struct { 2319 T3_32BIT_REGISTER Mode; 2320#define T3_MEM_ARBITER_MODE_RESET BIT_0 2321#define T3_MEM_ARBITER_MODE_ENABLE BIT_1 2322 2323 T3_32BIT_REGISTER Status; 2324 2325 T3_32BIT_REGISTER ArbTrapAddrLow; 2326 T3_32BIT_REGISTER ArbTrapAddrHigh; 2327 2328 /* Unused space. */ 2329 LM_UINT8 Unused[1008]; 2330} T3_MEM_ARBITER, *PT3_MEM_ARBITER; 2331 2332 2333 2334/******************************************************************************/ 2335/* Buffer manager control register. */ 2336/******************************************************************************/ 2337 2338typedef struct { 2339 T3_32BIT_REGISTER Mode; 2340 #define BUFMGR_MODE_RESET BIT_0 2341 #define BUFMGR_MODE_ENABLE BIT_1 2342 #define BUFMGR_MODE_ATTN_ENABLE BIT_2 2343 #define BUFMGR_MODE_BM_TEST BIT_3 2344 #define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4 2345 2346 T3_32BIT_REGISTER Status; 2347 #define BUFMGR_STATUS_ERROR BIT_2 2348 #define BUFMGR_STATUS_MBUF_LOW BIT_4 2349 2350 T3_32BIT_REGISTER MbufPoolAddr; 2351 T3_32BIT_REGISTER MbufPoolSize; 2352 T3_32BIT_REGISTER MbufReadDmaLowWaterMark; 2353 T3_32BIT_REGISTER MbufMacRxLowWaterMark; 2354 T3_32BIT_REGISTER MbufHighWaterMark; 2355 2356 T3_32BIT_REGISTER RxCpuMbufAllocReq; 2357 #define BUFMGR_MBUF_ALLOC_BIT BIT_31 2358 T3_32BIT_REGISTER RxCpuMbufAllocResp; 2359 T3_32BIT_REGISTER TxCpuMbufAllocReq; 2360 T3_32BIT_REGISTER TxCpuMbufAllocResp; 2361 2362 T3_32BIT_REGISTER DmaDescPoolAddr; 2363 T3_32BIT_REGISTER DmaDescPoolSize; 2364 T3_32BIT_REGISTER DmaLowWaterMark; 2365 T3_32BIT_REGISTER DmaHighWaterMark; 2366 2367 T3_32BIT_REGISTER RxCpuDmaAllocReq; 2368 T3_32BIT_REGISTER RxCpuDmaAllocResp; 2369 T3_32BIT_REGISTER TxCpuDmaAllocReq; 2370 T3_32BIT_REGISTER TxCpuDmaAllocResp; 2371 2372 T3_32BIT_REGISTER Hwdiag[3]; 2373 2374 /* Unused space. */ 2375 LM_UINT8 Unused[936]; 2376} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER; 2377 2378 2379 2380/******************************************************************************/ 2381/* Read DMA control registers. */ 2382/******************************************************************************/ 2383 2384typedef struct { 2385 T3_32BIT_REGISTER Mode; 2386 #define DMA_READ_MODE_RESET BIT_0 2387 #define DMA_READ_MODE_ENABLE BIT_1 2388 #define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 2389 #define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 2390 #define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 2391 #define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 2392 #define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 2393 #define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 2394 #define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 2395 #define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9 2396 #define DMA_READ_MODE_MULTI_SPLIT_ENABLE BIT_11 2397 #define DMA_READ_MODE_MULTI_SPLIT_RESET BIT_12 2398 #define DMA_READ_MODE_FIFO_SIZE_128 BIT_17 2399 #define DMA_READ_MODE_FIFO_LONG_BURST (BIT_16 | BIT_17) 2400 2401 T3_32BIT_REGISTER Status; 2402 #define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2 2403 #define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3 2404 #define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4 2405 #define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5 2406 #define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6 2407 #define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7 2408 #define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8 2409 #define DMA_READ_STATUS_LONG_READ_ATTN BIT_9 2410 2411 /* Unused space. */ 2412 LM_UINT8 Unused[1016]; 2413} T3_DMA_READ, *PT3_DMA_READ; 2414 2415#if defined(PC) 2416#undef PC 2417#define PC pc 2418#endif 2419 2420typedef union T3_CPU 2421{ 2422 struct 2423 { 2424 T3_32BIT_REGISTER mode; 2425 #define CPU_MODE_HALT BIT_10 2426 #define CPU_MODE_RESET BIT_0 2427 T3_32BIT_REGISTER state; 2428 T3_32BIT_REGISTER EventMask; 2429 T3_32BIT_REGISTER reserved1[4]; 2430 T3_32BIT_REGISTER PC; 2431 T3_32BIT_REGISTER Instruction; 2432 T3_32BIT_REGISTER SpadUnderflow; 2433 T3_32BIT_REGISTER WatchdogClear; 2434 T3_32BIT_REGISTER WatchdogVector; 2435 T3_32BIT_REGISTER WatchdogSavedPC; 2436 T3_32BIT_REGISTER HardwareBp; 2437 T3_32BIT_REGISTER reserved2[3]; 2438 T3_32BIT_REGISTER WatchdogSavedState; 2439 T3_32BIT_REGISTER LastBrchAddr; 2440 T3_32BIT_REGISTER SpadUnderflowSet; 2441 T3_32BIT_REGISTER reserved3[(0x200-0x50)/4]; 2442 T3_32BIT_REGISTER Regs[32]; 2443 T3_32BIT_REGISTER reserved4[(0x400-0x280)/4]; 2444 }reg; 2445}T3_CPU, *PT3_CPU; 2446 2447/******************************************************************************/ 2448/* Write DMA control registers. */ 2449/******************************************************************************/ 2450 2451typedef struct { 2452 T3_32BIT_REGISTER Mode; 2453 #define DMA_WRITE_MODE_RESET BIT_0 2454 #define DMA_WRITE_MODE_ENABLE BIT_1 2455 #define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 2456 #define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 2457 #define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 2458 #define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 2459 #define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 2460 #define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 2461 #define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 2462 #define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9 2463 #define DMA_WRITE_MODE_RECEIVE_ACCELERATE BIT_10 2464 2465 T3_32BIT_REGISTER Status; 2466 #define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2 2467 #define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3 2468 #define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4 2469 #define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5 2470 #define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6 2471 #define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7 2472 #define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8 2473 #define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9 2474 2475 /* Unused space. */ 2476 LM_UINT8 Unused[1016]; 2477} T3_DMA_WRITE, *PT3_DMA_WRITE; 2478 2479 2480 2481/******************************************************************************/ 2482/* Mailbox registers. */ 2483/******************************************************************************/ 2484 2485typedef struct { 2486 /* Interrupt mailbox registers. */ 2487 T3_64BIT_REGISTER Interrupt[4]; 2488 2489 /* General mailbox registers. */ 2490 T3_64BIT_REGISTER General[8]; 2491 2492 /* Reload statistics mailbox. */ 2493 T3_64BIT_REGISTER ReloadStat; 2494 2495 /* Receive BD ring producer index registers. */ 2496 T3_64BIT_REGISTER RcvStdProdIdx; 2497 T3_64BIT_REGISTER RcvJumboProdIdx; 2498 T3_64BIT_REGISTER RcvMiniProdIdx; 2499 2500 /* Receive return ring consumer index registers. */ 2501 T3_64BIT_REGISTER RcvRetConIdx[16]; 2502 2503 /* Send BD ring host producer index registers. */ 2504 T3_64BIT_REGISTER SendHostProdIdx[16]; 2505 2506 /* Send BD ring nic producer index registers. */ 2507 T3_64BIT_REGISTER SendNicProdIdx[16]; 2508}T3_MAILBOX, *PT3_MAILBOX; 2509 2510typedef struct { 2511 T3_MAILBOX Mailbox; 2512 2513 /* Priority mailbox registers. */ 2514 T3_32BIT_REGISTER HighPriorityEventVector; 2515 T3_32BIT_REGISTER HighPriorityEventMask; 2516 T3_32BIT_REGISTER LowPriorityEventVector; 2517 T3_32BIT_REGISTER LowPriorityEventMask; 2518 2519 /* Unused space. */ 2520 LM_UINT8 Unused[496]; 2521} T3_GRC_MAILBOX, *PT3_GRC_MAILBOX; 2522 2523 2524/******************************************************************************/ 2525/* Flow through queues. */ 2526/******************************************************************************/ 2527 2528typedef struct { 2529 T3_32BIT_REGISTER Reset; 2530 2531 LM_UINT8 Unused[12]; 2532 2533 T3_32BIT_REGISTER DmaNormalReadFtqCtrl; 2534 T3_32BIT_REGISTER DmaNormalReadFtqFullCnt; 2535 T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue; 2536 T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek; 2537 2538 T3_32BIT_REGISTER DmaHighReadFtqCtrl; 2539 T3_32BIT_REGISTER DmaHighReadFtqFullCnt; 2540 T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue; 2541 T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek; 2542 2543 T3_32BIT_REGISTER DmaCompDiscardFtqCtrl; 2544 T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt; 2545 T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue; 2546 T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek; 2547 2548 T3_32BIT_REGISTER SendBdCompFtqCtrl; 2549 T3_32BIT_REGISTER SendBdCompFtqFullCnt; 2550 T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue; 2551 T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek; 2552 2553 T3_32BIT_REGISTER SendDataInitiatorFtqCtrl; 2554 T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt; 2555 T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue; 2556 T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek; 2557 2558 T3_32BIT_REGISTER DmaNormalWriteFtqCtrl; 2559 T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt; 2560 T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue; 2561 T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek; 2562 2563 T3_32BIT_REGISTER DmaHighWriteFtqCtrl; 2564 T3_32BIT_REGISTER DmaHighWriteFtqFullCnt; 2565 T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue; 2566 T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek; 2567 2568 T3_32BIT_REGISTER SwType1FtqCtrl; 2569 T3_32BIT_REGISTER SwType1FtqFullCnt; 2570 T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue; 2571 T3_32BIT_REGISTER SwType1FtqFifoWritePeek; 2572 2573 T3_32BIT_REGISTER SendDataCompFtqCtrl; 2574 T3_32BIT_REGISTER SendDataCompFtqFullCnt; 2575 T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue; 2576 T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek; 2577 2578 T3_32BIT_REGISTER HostCoalesceFtqCtrl; 2579 T3_32BIT_REGISTER HostCoalesceFtqFullCnt; 2580 T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue; 2581 T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek; 2582 2583 T3_32BIT_REGISTER MacTxFtqCtrl; 2584 T3_32BIT_REGISTER MacTxFtqFullCnt; 2585 T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue; 2586 T3_32BIT_REGISTER MacTxFtqFifoWritePeek; 2587 2588 T3_32BIT_REGISTER MbufClustFreeFtqCtrl; 2589 T3_32BIT_REGISTER MbufClustFreeFtqFullCnt; 2590 T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue; 2591 T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek; 2592 2593 T3_32BIT_REGISTER RcvBdCompFtqCtrl; 2594 T3_32BIT_REGISTER RcvBdCompFtqFullCnt; 2595 T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue; 2596 T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek; 2597 2598 T3_32BIT_REGISTER RcvListPlmtFtqCtrl; 2599 T3_32BIT_REGISTER RcvListPlmtFtqFullCnt; 2600 T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue; 2601 T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek; 2602 2603 T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl; 2604 T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt; 2605 T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue; 2606 T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek; 2607 2608 T3_32BIT_REGISTER RcvDataCompFtqCtrl; 2609 T3_32BIT_REGISTER RcvDataCompFtqFullCnt; 2610 T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue; 2611 T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek; 2612 2613 T3_32BIT_REGISTER SwType2FtqCtrl; 2614 T3_32BIT_REGISTER SwType2FtqFullCnt; 2615 T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue; 2616 T3_32BIT_REGISTER SwType2FtqFifoWritePeek; 2617 2618 /* Unused space. */ 2619 LM_UINT8 Unused2[736]; 2620} T3_FTQ, *PT3_FTQ; 2621 2622 2623 2624/******************************************************************************/ 2625/* Message signaled interrupt registers. */ 2626/******************************************************************************/ 2627 2628typedef struct { 2629 T3_32BIT_REGISTER Mode; 2630#define MSI_MODE_RESET BIT_0 2631#define MSI_MODE_ENABLE BIT_1 2632 T3_32BIT_REGISTER Status; 2633 2634 T3_32BIT_REGISTER MsiFifoAccess; 2635 2636 /* Unused space. */ 2637 LM_UINT8 Unused[1012]; 2638} T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT; 2639 2640 2641 2642/******************************************************************************/ 2643/* DMA Completion registes. */ 2644/******************************************************************************/ 2645 2646typedef struct { 2647 T3_32BIT_REGISTER Mode; 2648 #define DMA_COMP_MODE_RESET BIT_0 2649 #define DMA_COMP_MODE_ENABLE BIT_1 2650 2651 /* Unused space. */ 2652 LM_UINT8 Unused[1020]; 2653} T3_DMA_COMPLETION, *PT3_DMA_COMPLETION; 2654 2655 2656 2657/******************************************************************************/ 2658/* GRC registers. */ 2659/******************************************************************************/ 2660 2661typedef struct { 2662 /* Mode control register. */ 2663 T3_32BIT_REGISTER Mode; 2664 #define GRC_MODE_UPDATE_ON_COALESCING BIT_0 2665 #define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1 2666 #define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2 2667 #define GRC_MODE_BYTE_SWAP_DATA BIT_4 2668 #define GRC_MODE_WORD_SWAP_DATA BIT_5 2669 #define GRC_MODE_SPLIT_HEADER_MODE BIT_8 2670 #define GRC_MODE_NO_FRAME_CRACKING BIT_9 2671 #define GRC_MODE_INCLUDE_CRC BIT_10 2672 #define GRC_MODE_ALLOW_BAD_FRAMES BIT_11 2673 #define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13 2674 #define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14 2675 #define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15 2676 #define GRC_MODE_HOST_STACK_UP BIT_16 2677 #define GRC_MODE_HOST_SEND_BDS BIT_17 2678 #define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20 2679 #define GRC_MODE_NVRAM_WRITE_ENABLE BIT_21 2680 #define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23 2681 #define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24 2682 #define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25 2683 #define GRC_MODE_INT_ON_MAC_ATTN BIT_26 2684 #define GRC_MODE_INT_ON_DMA_ATTN BIT_27 2685 #define GRC_MODE_INT_ON_FLOW_ATTN BIT_28 2686 #define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29 2687 #define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30 2688 2689 /* Misc configuration register. */ 2690 T3_32BIT_REGISTER MiscCfg; 2691 #define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0 2692 #define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe 2693 #define GRC_MISC_BD_ID_MASK 0x0001e000 2694 #define GRC_MISC_BD_ID_5700 0x0001e000 2695 #define GRC_MISC_BD_ID_5701 0x00000000 2696 #define GRC_MISC_BD_ID_5703 0x00000000 2697 #define GRC_MISC_BD_ID_5703S 0x00002000 2698 #define GRC_MISC_BD_ID_5702FE 0x00004000 2699 #define GRC_MISC_BD_ID_5704 0x00000000 2700 #define GRC_MISC_BD_ID_5704CIOBE 0x00004000 2701 #define GRC_MISC_BD_ID_5788 0x00010000 2702 #define GRC_MISC_BD_ID_5788M 0x00018000 2703 #define GRC_MISC_GPHY_KEEP_POWER_DURING_RESET BIT_26 2704 2705 /* Miscellaneous local control register. */ 2706 T3_32BIT_REGISTER LocalCtrl; 2707 #define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0 2708 #define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1 2709 #define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2 2710 #define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3 2711 2712 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT3 BIT_5 2713 #define GRC_MISC_LOCAL_CTRL_GPIO_OE3 BIT_6 2714 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT3 BIT_7 2715 2716 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8 2717 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9 2718 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10 2719 #define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11 2720 #define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12 2721 #define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13 2722 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14 2723 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15 2724 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16 2725 #define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17 2726 #define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21 2727 #define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22 2728 2729 #define GRC_MISC_MEMSIZE_256K 0 2730 #define GRC_MISC_MEMSIZE_512K (1 << 18) 2731 #define GRC_MISC_MEMSIZE_1024K (2 << 18) 2732 #define GRC_MISC_MEMSIZE_2048K (3 << 18) 2733 #define GRC_MISC_MEMSIZE_4096K (4 << 18) 2734 #define GRC_MISC_MEMSIZE_8192K (5 << 18) 2735 #define GRC_MISC_MEMSIZE_16M (6 << 18) 2736 #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24 2737 2738 2739 T3_32BIT_REGISTER Timer; 2740 2741 T3_32BIT_REGISTER RxCpuEvent; 2742 T3_32BIT_REGISTER RxTimerRef; 2743 T3_32BIT_REGISTER RxCpuSemaphore; 2744 T3_32BIT_REGISTER RemoteRxCpuAttn; 2745 2746 T3_32BIT_REGISTER TxCpuEvent; 2747 T3_32BIT_REGISTER TxTimerRef; 2748 T3_32BIT_REGISTER TxCpuSemaphore; 2749 T3_32BIT_REGISTER RemoteTxCpuAttn; 2750 2751 T3_64BIT_REGISTER MemoryPowerUp; 2752 2753 T3_32BIT_REGISTER EepromAddr; 2754 #define SEEPROM_ADDR_WRITE 0 2755 #define SEEPROM_ADDR_READ (1 << 31) 2756 #define SEEPROM_ADDR_RW_MASK 0x80000000 2757 #define SEEPROM_ADDR_COMPLETE (1 << 30) 2758 #define SEEPROM_ADDR_FSM_RESET (1 << 29) 2759 #define SEEPROM_ADDR_DEV_ID(x) (x << 26) 2760 #define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000 2761 #define SEEPROM_ADDR_START (1 << 25) 2762 #define SEEPROM_ADDR_CLK_PERD(x) (x << 16) 2763 #define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc) 2764 #define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff 2765 2766 #define SEEPROM_CLOCK_PERIOD 60 2767 #define SEEPROM_CHIP_SIZE (64 * 1024) 2768 2769 T3_32BIT_REGISTER EepromData; 2770 T3_32BIT_REGISTER EepromCtrl; 2771 2772 T3_32BIT_REGISTER MdiCtrl; 2773 T3_32BIT_REGISTER SepromDelay; 2774 2775 /* Unused space. */ 2776 LM_UINT8 Unused[948]; 2777} T3_GRC, *PT3_GRC; 2778 2779 2780/******************************************************************************/ 2781/* NVRAM control registers. */ 2782/******************************************************************************/ 2783 2784typedef struct 2785{ 2786 T3_32BIT_REGISTER Cmd; 2787 #define NVRAM_CMD_RESET BIT_0 2788 #define NVRAM_CMD_DONE BIT_3 2789 #define NVRAM_CMD_DO_IT BIT_4 2790 #define NVRAM_CMD_WR BIT_5 2791 #define NVRAM_CMD_RD BIT_NONE 2792 #define NVRAM_CMD_ERASE BIT_6 2793 #define NVRAM_CMD_FIRST BIT_7 2794 #define NVRAM_CMD_LAST BIT_8 2795 #define NVRAM_CMD_WRITE_ENABLE BIT_16 2796 #define NVRAM_CMD_WRITE_DISABLE BIT_17 2797 #define NVRAM_CMD_EN_WR_SR BIT_18 2798 #define NVRAM_CMD_DO_WR_SR BIT_19 2799 2800 T3_32BIT_REGISTER Status; 2801 T3_32BIT_REGISTER WriteData; 2802 2803 T3_32BIT_REGISTER Addr; 2804 #define NVRAM_ADDRESS_MASK 0xffffff 2805 2806 T3_32BIT_REGISTER ReadData; 2807 2808 /* Flash config 1 register. */ 2809 T3_32BIT_REGISTER Config1; 2810 #define FLASH_INTERFACE_ENABLE BIT_0 2811 #define FLASH_SSRAM_BUFFERED_MODE BIT_1 2812 #define FLASH_PASS_THRU_MODE BIT_2 2813 #define FLASH_BIT_BANG_MODE BIT_3 2814 #define FLASH_STATUS_BITS_MASK (BIT_4 | BIT_5 | BIT_6) 2815 #define FLASH_SIZE BIT_25 2816 #define FLASH_COMPAT_BYPASS BIT_31 2817 #define FLASH_VENDOR_MASK (BIT_25 | BIT_24 | BIT_1 | BIT_0) 2818 #define FLASH_VENDOR_ATMEL_EEPROM BIT_25 2819 #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED (BIT_25 | BIT_1 | BIT_0) 2820 #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED (BIT_1 | BIT_0) 2821 #define FLASH_VENDOR_ST (BIT_25 | BIT_24 | BIT_0) 2822 #define FLASH_VENDOR_SAIFUN (BIT_24 | BIT_1 | BIT_0) 2823 #define FLASH_VENDOR_SST_SMALL BIT_0 2824 #define FLASH_VENDOR_SST_LARGE (BIT_25 | BIT_0) 2825 2826 #define BUFFERED_FLASH (FLASH_INTERFACE_ENABLE | FLASH_SSRAM_BUFFERED_MODE) 2827 2828 /* Buffered flash (Atmel: AT45DB011B) specific information */ 2829 #define BUFFERED_FLASH_PAGE_POS 9 2830 #define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<<BUFFERED_FLASH_PAGE_POS) - 1) 2831 #define BUFFERED_FLASH_PAGE_SIZE 264 2832 #define BUFFERED_FLASH_PHY_PAGE_SIZE 512 2833 2834 /* Bleh! Definitions for Baxter. */ 2835 #define FLASH_PART_5750_TYPEMASK \ 2836 (BIT_25 | BIT_24 | BIT_1 | BIT_0) 2837 2838 #define FLASH_PART_5752_TYPEMASK \ 2839 (BIT_25 | BIT_24 | BIT_23 | BIT_22 | BIT_1 | BIT_0) 2840 2841 #define FLASH_PART_5752_EEPROM_ATMEL_64K BIT_NONE 2842 #define FLASH_PART_5752_EEPROM_ATMEL_376K BIT_25 2843 #define FLASH_PART_5752_FLASH_ATMEL_AT45DB041 (BIT_25 | BIT_1 | BIT_0) 2844 #define FLASH_PART_5752_FLASH_ATMEL_AT25F512 (BIT_1 | BIT_0) 2845 #define FLASH_PART_5752_FLASH_SST_45VF010 (BIT_25 | BIT_0) 2846 #define FLASH_PART_5752_FLASH_SST_25F512 (BIT_0) 2847 #define FLASH_PART_5752_FLASH_ST_M25P10A (BIT_25 | BIT_24 | BIT_0) 2848 #define FLASH_PART_5752_FLASH_ST_M25P05A (BIT_24 | BIT_0) 2849 #define FLASH_PART_5752_FLASH_SAIFUN_SA25F010 (BIT_22) 2850 #define FLASH_PART_5752_FLASH_SAIFUN_SA25F020 (BIT_22 | BIT_1) 2851 #define FLASH_PART_5752_FLASH_SAIFUN_SA25F040 (BIT_22 | BIT_0) 2852 #define FLASH_PART_5752_FLASH_SST_25VF010 (BIT_24 | BIT_22) 2853 #define FLASH_PART_5752_FLASH_SST_25VF020 (BIT_24 | BIT_22 | BIT_1) 2854 #define FLASH_PART_5752_FLASH_SST_25VF040 (BIT_24 | BIT_22 | BIT_0) 2855 #define FLASH_PART_5752_FLASH_ST_M45PE10 (BIT_25 | BIT_22) 2856 #define FLASH_PART_5752_FLASH_ST_M45PE20 (BIT_25 | BIT_22 | BIT_1) 2857 #define FLASH_PART_5752_FLASH_ST_M45PE40 (BIT_25 | BIT_22 | BIT_0) 2858 2859 #define FLASH_PART_5752_PAGEMASK \ 2860 (BIT_30 | BIT_29 | BIT_28) 2861 2862 #define FLASH_PART_5752_PAGE_SIZE_256B BIT_NONE 2863 #define FLASH_PART_5752_PAGE_SIZE_512B BIT_28 2864 #define FLASH_PART_5752_PAGE_SIZE_1K BIT_29 2865 #define FLASH_PART_5752_PAGE_SIZE_2K (BIT_29 | BIT_28) 2866 #define FLASH_PART_5752_PAGE_SIZE_4K BIT_30 2867 #define FLASH_PART_5752_PAGE_SIZE_264B (BIT_30 | BIT_28) 2868 2869 2870 T3_32BIT_REGISTER Config2; 2871 #define NVRAM_COMMAND_MASK 0x000000ff 2872 #define NVRAM_STATUS_COMMAND(x) ((x) << 16) 2873 #define NVRAM_ERASE_COMMAND(x) (x) 2874 2875 T3_32BIT_REGISTER Config3; 2876 #define NVRAM_COMMAND_MASK 0x000000ff 2877 #define NVRAM_READ_COMMAND(x) ((x) << 24) 2878 #define NVRAM_WRITE_UNBUFFERED_COMMAND(x) ((x) << 8) 2879 #define NVRAM_WRITE_BUFFERED_COMMAND(x) ((x) << 16) 2880 #define NVRAM_RESET_COMMAND(x) (x) 2881 2882 T3_32BIT_REGISTER SwArb; 2883 #define SW_ARB_REQ_SET0 BIT_0 2884 #define SW_ARB_REQ_SET1 BIT_1 2885 #define SW_ARB_REQ_SET2 BIT_2 2886 #define SW_ARB_REQ_SET3 BIT_3 2887 #define SW_ARB_REQ_CLR0 BIT_4 2888 #define SW_ARB_REQ_CLR1 BIT_5 2889 #define SW_ARB_REQ_CLR2 BIT_6 2890 #define SW_ARB_REQ_CLR3 BIT_7 2891 #define SW_ARB_GNT0 BIT_8 2892 #define SW_ARB_GNT1 BIT_9 2893 #define SW_ARB_GNT2 BIT_10 2894 #define SW_ARB_GNT3 BIT_11 2895 #define SW_ARB_REQ0 BIT_12 2896 #define SW_ARB_REQ1 BIT_13 2897 #define SW_ARB_REQ2 BIT_14 2898 #define SW_ARB_REQ3 BIT_15 2899 2900 T3_32BIT_REGISTER NvmAccess; 2901 #define ACCESS_EN BIT_0 2902 #define ACCESS_WR_EN BIT_1 2903 #define NVRAM_ACCESS_ENABLE BIT_0 2904 #define NVRAM_ACCESS_WRITE_ENABLE BIT_1 2905 2906 T3_32BIT_REGISTER Write1; 2907 #define NVRAM_WRITE1_WRENA_CMD(x) (x) 2908 #define NVRAM_WRITE1_WRDIS_CMD(x) ((x) << 8) 2909 2910 T3_32BIT_REGISTER WatchTimer; 2911 2912 T3_32BIT_REGISTER Config4; 2913 2914 /* Unused space. */ 2915 LM_UINT8 Unused[972]; 2916} T3_NVRAM, *PT3_NVRAM; 2917 2918 2919/******************************************************************************/ 2920/* NIC's internal memory. */ 2921/******************************************************************************/ 2922 2923typedef struct { 2924 /* Page zero for the internal CPUs. */ 2925 LM_UINT8 PageZero[0x100]; /* 0x0000 */ 2926 2927 /* Send RCBs. */ 2928 T3_RCB SendRcb[16]; /* 0x0100 */ 2929 2930 /* Receive Return RCBs. */ 2931 T3_RCB RcvRetRcb[16]; /* 0x0200 */ 2932 2933 /* Statistics block. */ 2934 T3_STATS_BLOCK StatsBlk; /* 0x0300 */ 2935 2936 /* Status block. */ 2937 T3_STATUS_BLOCK StatusBlk; /* 0x0b00 */ 2938 2939 /* Reserved for software. */ 2940 LM_UINT8 Reserved[1200]; /* 0x0b50 */ 2941 2942 /* Unmapped region. */ 2943 LM_UINT8 Unmapped[4096]; /* 0x1000 */ 2944 2945 /* DMA descriptors. */ 2946 LM_UINT8 DmaDesc[8192]; /* 0x2000 */ 2947 2948 /* Buffer descriptors. */ 2949 LM_UINT8 BufferDesc[16384]; /* 0x4000 */ 2950} T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM; 2951 2952 2953 2954/******************************************************************************/ 2955/* Memory layout. */ 2956/******************************************************************************/ 2957 2958typedef struct { 2959 /* PCI configuration registers. */ 2960 T3_PCI_CONFIGURATION PciCfg; 2961 2962 /* Unused. */ 2963 LM_UINT8 Unused1[0x100]; /* 0x0100 */ 2964 2965 /* Mailbox . */ 2966 T3_MAILBOX Mailbox; /* 0x0200 */ 2967 2968 /* MAC control registers. */ 2969 T3_MAC_CONTROL MacCtrl; /* 0x0400 */ 2970 2971 /* Send data initiator control registers. */ 2972 T3_SEND_DATA_INITIATOR SndDataIn; /* 0x0c00 */ 2973 2974 /* Send data completion Control registers. */ 2975 T3_SEND_DATA_COMPLETION SndDataComp; /* 0x1000 */ 2976 2977 /* Send BD ring selector. */ 2978 T3_SEND_BD_SELECTOR SndBdSel; /* 0x1400 */ 2979 2980 /* Send BD initiator control registers. */ 2981 T3_SEND_BD_INITIATOR SndBdIn; /* 0x1800 */ 2982 2983 /* Send BD completion control registers. */ 2984 T3_SEND_BD_COMPLETION SndBdComp; /* 0x1c00 */ 2985 2986 /* Receive list placement control registers. */ 2987 T3_RCV_LIST_PLACEMENT RcvListPlmt; /* 0x2000 */ 2988 2989 /* Receive Data and Receive BD Initiator Control. */ 2990 T3_RCV_DATA_BD_INITIATOR RcvDataBdIn; /* 0x2400 */ 2991 2992 /* Receive Data Completion Control */ 2993 T3_RCV_DATA_COMPLETION RcvDataComp; /* 0x2800 */ 2994 2995 /* Receive BD Initiator Control Registers. */ 2996 T3_RCV_BD_INITIATOR RcvBdIn; /* 0x2c00 */ 2997 2998 /* Receive BD Completion Control Registers. */ 2999 T3_RCV_BD_COMPLETION RcvBdComp; /* 0x3000 */ 3000 3001 /* Receive list selector control registers. */ 3002 T3_RCV_LIST_SELECTOR RcvListSel; /* 0x3400 */ 3003 3004 /* Mbuf cluster free registers. */ 3005 T3_MBUF_CLUSTER_FREE MbufClusterFree; /* 0x3800 */ 3006 3007 /* Host coalescing control registers. */ 3008 T3_HOST_COALESCING HostCoalesce; /* 0x3c00 */ 3009 3010 /* Memory arbiter control registers. */ 3011 T3_MEM_ARBITER MemArbiter; /* 0x4000 */ 3012 3013 /* Buffer manger control registers. */ 3014 T3_BUFFER_MANAGER BufMgr; /* 0x4400 */ 3015 3016 /* Read DMA control registers. */ 3017 T3_DMA_READ DmaRead; /* 0x4800 */ 3018 3019 /* Write DMA control registers. */ 3020 T3_DMA_WRITE DmaWrite; /* 0x4c00 */ 3021 3022 T3_CPU rxCpu; /* 0x5000 */ 3023 T3_CPU txCpu; /* 0x5400 */ 3024 3025 /* Mailboxes. */ 3026 T3_GRC_MAILBOX GrcMailbox; /* 0x5800 */ 3027 3028 /* Flow Through queues. */ 3029 T3_FTQ Ftq; /* 0x5c00 */ 3030 3031 /* Message signaled interrupt registes. */ 3032 T3_MSG_SIGNALED_INT Msi; /* 0x6000 */ 3033 3034 /* DMA completion registers. */ 3035 T3_DMA_COMPLETION DmaComp; /* 0x6400 */ 3036 3037 /* GRC registers. */ 3038 T3_GRC Grc; /* 0x6800 */ 3039 3040 /* Unused space. */ 3041 LM_UINT8 Unused2[1024]; /* 0x6c00 */ 3042 3043 /* NVRAM registers. */ 3044 T3_NVRAM Nvram; /* 0x7000 */ 3045 3046 /* Unused space. */ 3047 LM_UINT8 Unused3[3072]; /* 0x7400 */ 3048 3049 /* The 32k memory window into the NIC's */ 3050 /* internal memory. The memory window is */ 3051 /* controlled by the Memory Window Base */ 3052 /* Address register. This register is located */ 3053 /* in the PCI configuration space. */ 3054 union { /* 0x8000 */ 3055 T3_FIRST_32K_SRAM First32k; 3056 3057 /* Use the memory window base address register to determine the */ 3058 /* MBUF segment. */ 3059 LM_UINT32 Mbuf[32768/4]; 3060 LM_UINT32 MemBlock32K[32768/4]; 3061 } uIntMem; 3062} T3_STD_MEM_MAP, *PT3_STD_MEM_MAP; 3063 3064 3065/******************************************************************************/ 3066/* Adapter info. */ 3067/******************************************************************************/ 3068 3069typedef struct 3070{ 3071 LM_UINT16 Svid; 3072 LM_UINT16 Ssid; 3073 LM_UINT32 PhyId; 3074 LM_UINT32 Serdes; /* 0 = copper PHY, 1 = Serdes */ 3075} LM_ADAPTER_INFO, *PLM_ADAPTER_INFO; 3076 3077 3078/******************************************************************************/ 3079/* Flash info. */ 3080/******************************************************************************/ 3081 3082typedef struct { 3083 LM_UINT8 jedecnum; 3084 LM_UINT8 romtype; 3085 #define ROM_TYPE_EEPROM 0x1 3086 #define ROM_TYPE_FLASH 0x2 3087 LM_BOOL buffered; 3088 3089 LM_UINT32 chipsize; 3090 LM_UINT32 pagesize; 3091} FLASHINFO; 3092 3093 3094#define JEDEC_ATMEL 0x1f 3095#define JEDEC_ST 0x20 3096#define JEDEC_SAIFUN 0x4f 3097#define JEDEC_SST 0xbf 3098 3099#define ATMEL_AT24C64_CHIP_SIZE (64 * 1024) 3100#define ATMEL_AT24C64_PAGE_SIZE (32) 3101#define ATMEL_AT24C64_PAGE_MASK (ATMEL_AT24C64_PAGE_SIZE - 1) 3102 3103#define ATMEL_AT24C512_CHIP_SIZE (512 * 1024) 3104#define ATMEL_AT24C512_PAGE_SIZE (128) 3105#define ATMEL_AT24C512_PAGE_MASK (ATMEL_AT24C512_PAGE_SIZE - 1) 3106 3107#define ATMEL_AT45DB0X1B_PAGE_POS 9 3108#define ATMEL_AT45DB0X1B_PAGE_SIZE 264 3109#define ATMEL_AT45DB0X1B_PAGE_MASK 0x1ff 3110#define ATMEL_AT45DB0X1B_BUFFER_WRITE_CMD 0x83 3111 3112/* Currently unsupported flash type */ 3113#define ATMEL_AT25F512_PAGE_SIZE 256 3114#define ATMEL_AT25F512_PAGE_MASK (ATMEL_AT25F512_PAGE_SIZE - 1) 3115 3116#define ST_M45PEX0_PAGE_SIZE 256 3117#define ST_M45PEX0_PAGE_MASK (ST_M45PEX0_PAGE_SIZE - 1) 3118#define ST_M45PEX0_READ_STATUS_CMD 0x05 3119#define ST_M45PEX0_PAGE_ERASE_CMD 0xDB 3120#define ST_M45PEX0_PAGE_PRGM_CMD 0x0A 3121#define ST_M45PEX0_WRENA_CMD 0x06 3122#define ST_M45PEX0_WRDIS_CMD 0x04 3123 3124#define SAIFUN_SA25F0XX_PAGE_SIZE 256 3125#define SAIFUN_SA25F0XX_PAGE_MASK (SAIFUN_SA25F0XX_PAGE_SIZE - 1) 3126#define SAIFUN_SA25F0XX_READ_STATUS_CMD 0x05 3127#define SAIFUN_SA25F0XX_PAGE_ERASE_CMD 0x81 3128#define SAIFUN_SA25F0XX_PAGE_WRITE_CMD 0x02 3129#define SAIFUN_SA25F0XX_WRENA_CMD 0x06 3130 3131/* Currently unsupported flash type */ 3132#define SST_25VF0X0_PAGE_SIZE 4098 3133#define SST_25VF0X0_PAGE_MASK (SST_25VF0X0_PAGE_SIZE - 1) 3134 3135 3136/******************************************************************************/ 3137/* Packet queues. */ 3138/******************************************************************************/ 3139 3140DECLARE_QUEUE_TYPE(LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT); 3141DECLARE_QUEUE_TYPE(LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT); 3142 3143 3144 3145/******************************************************************************/ 3146/* Tx counters. */ 3147/******************************************************************************/ 3148 3149typedef struct { 3150 LM_COUNTER TxPacketGoodCnt; 3151 LM_COUNTER TxBytesGoodCnt; 3152 LM_COUNTER TxPacketAbortedCnt; 3153 LM_COUNTER NoSendBdLeftCnt; 3154 LM_COUNTER NoMapRegisterLeftCnt; 3155 LM_COUNTER TooManyFragmentsCnt; 3156 LM_COUNTER NoTxPacketDescCnt; 3157} LM_TX_COUNTERS, *PLM_TX_COUNTERS; 3158 3159 3160 3161/******************************************************************************/ 3162/* Rx counters. */ 3163/******************************************************************************/ 3164 3165typedef struct { 3166 LM_COUNTER RxPacketGoodCnt; 3167 LM_COUNTER RxBytesGoodCnt; 3168 LM_COUNTER RxPacketErrCnt; 3169 LM_COUNTER RxErrCrcCnt; 3170 LM_COUNTER RxErrCollCnt; 3171 LM_COUNTER RxErrLinkLostCnt; 3172 LM_COUNTER RxErrPhyDecodeCnt; 3173 LM_COUNTER RxErrOddNibbleCnt; 3174 LM_COUNTER RxErrMacAbortCnt; 3175 LM_COUNTER RxErrShortPacketCnt; 3176 LM_COUNTER RxErrNoResourceCnt; 3177 LM_COUNTER RxErrLargePacketCnt; 3178} LM_RX_COUNTERS, *PLM_RX_COUNTERS; 3179 3180 3181 3182/******************************************************************************/ 3183/* Receive producer rings. */ 3184/******************************************************************************/ 3185 3186typedef enum { 3187 T3_UNKNOWN_RCV_PROD_RING = 0, 3188 T3_STD_RCV_PROD_RING = 1, 3189 T3_MINI_RCV_PROD_RING = 2, 3190 T3_JUMBO_RCV_PROD_RING = 3 3191} T3_RCV_PROD_RING, *PT3_RCV_PROD_RING; 3192 3193 3194 3195/******************************************************************************/ 3196/* Packet descriptor. */ 3197/******************************************************************************/ 3198 3199#define LM_PACKET_SIGNATURE_TX 0x6861766b 3200#define LM_PACKET_SIGNATURE_RX 0x6b766168 3201 3202typedef struct _LM_PACKET { 3203 /* Set in LM. */ 3204 LM_STATUS PacketStatus; 3205 3206 /* Set in LM for Rx, in UM for Tx. */ 3207 LM_UINT32 PacketSize; 3208 3209 LM_UINT16 Flags; 3210 3211 LM_UINT16 VlanTag; 3212 3213 union { 3214 /* Send info. */ 3215 struct { 3216 /* Set up by UM. */ 3217 LM_UINT32 FragCount; 3218 3219#if INCLUDE_TCP_SEG_SUPPORT 3220 LM_UINT32 MaxSegmentSize; 3221#endif 3222 } Tx; 3223 3224 /* Receive info. */ 3225 struct { 3226 /* This descriptor belongs to either Std, Mini, or Jumbo ring. */ 3227 LM_UINT16 RcvProdRing; 3228 LM_UINT16 RcvRingProdIdx; 3229 3230 /* Receive buffer size */ 3231 LM_UINT32 RxBufferSize; 3232 3233 /* Checksum information. */ 3234 LM_UINT16 IpChecksum; 3235 LM_UINT16 TcpUdpChecksum; 3236 3237 } Rx; 3238 } u; 3239} LM_PACKET; 3240 3241 3242 3243/******************************************************************************/ 3244/* Tigon3 device block. */ 3245/******************************************************************************/ 3246 3247typedef struct _LM_DEVICE_BLOCK { 3248 /* Memory view. */ 3249 PT3_STD_MEM_MAP pMemView; 3250 3251 /* Base address of the block of memory in which the LM_PACKET descriptors */ 3252 /* are allocated from. */ 3253 PLM_VOID pPacketDescBase; 3254 3255 LM_UINT32 MiscHostCtrl; 3256 LM_UINT32 GrcLocalCtrl; 3257 LM_UINT32 DmaReadWriteCtrl; 3258 LM_UINT32 PciState; 3259 LM_UINT32 ClockCtrl; 3260 LM_UINT32 DmaReadFifoSize; 3261 LM_UINT32 GrcMode; 3262 3263 LM_UINT32 PowerLevel; 3264 3265 LM_UINT32 Flags; 3266 3267#ifdef BCM_WL_EMULATOR 3268 LM_BOOL wl_emulate_rx; 3269 LM_BOOL wl_emulate_tx; 3270 void *wlc; 3271#endif /*BCM_WL_EMULATOR*/ 3272 3273 #define MINI_PCI_FLAG 0x1 3274 #define PCI_EXPRESS_FLAG 0x2 3275 #define BCM5788_FLAG 0x4 3276 #define FIBER_WOL_CAPABLE_FLAG 0x8 3277 #define WOL_LIMIT_10MBPS_FLAG 0x10 3278 #define ENABLE_MWI_FLAG 0x20 3279 #define USE_TAGGED_STATUS_FLAG 0x40 3280 3281 /* NIC will not compute the pseudo header checksum. The driver or OS */ 3282 /* must seed the checksum field with the pseudo checksum. */ 3283 #define NO_TX_PSEUDO_HDR_CSUM_FLAG 0x80 3284 3285 /* The receive checksum in the BD does not include the pseudo checksum. */ 3286 /* The OS or the driver must calculate the pseudo checksum and add it to */ 3287 /* the checksum in the BD. */ 3288 #define NO_RX_PSEUDO_HDR_CSUM_FLAG 0x100 3289 3290 #define ENABLE_PCIX_FIX_FLAG 0x200 3291 3292 #define TX_4G_WORKAROUND_FLAG 0x400 3293 #define UNDI_FIX_FLAG 0x800 3294 #define FLUSH_POSTED_WRITE_FLAG 0x1000 3295 #define REG_RD_BACK_FLAG 0x2000 3296 3297 /* Use NIC or Host based send BD. */ 3298 #define NIC_SEND_BD_FLAG 0x4000 3299 3300 /* Athlon fix. */ 3301 #define DELAY_PCI_GRANT_FLAG 0x8000 3302 3303 /* Enable OneDmaAtOnce */ 3304 #define ONE_DMA_AT_ONCE_FLAG 0x10000 3305 3306 /* Enable PCI-X multi split */ 3307 #define MULTI_SPLIT_ENABLE_FLAG 0x20000 3308 3309 #define RX_BD_LIMIT_64_FLAG 0x40000 3310 3311 #define DMA_WR_MODE_RX_ACCELERATE_FLAG 0x80000 3312 3313 /* write protect */ 3314 #define EEPROM_WP_FLAG 0x100000 3315 #define FLASH_DETECTED_FLAG 0x200000 3316 3317 #define DISABLE_D3HOT_FLAG 0x400000 3318 3319 /* 5753 should not output gpio2 */ 3320 #define GPIO2_DONOT_OUTPUT 0x800000 3321 3322 #define USING_MSI_FLAG 0x1000000 3323 #define JUMBO_CAPABLE_FLAG 0x2000000 3324 #define PROTECTED_NVRAM_FLAG 0x4000000 3325 #define T3_HAS_TWO_CPUS 0x8000000 3326 #define HOST_COALESCING_BUG_FIX 0x10000000 3327 3328 /* 5750 in BCM4785 */ 3329 #define SB_CORE_FLAG 0x20000000 3330 /* 5750 in RGMII mode (BCM4785) */ 3331 #define RGMII_MODE_FLAG 0x40000000 3332 /* connected to a ROBO switch */ 3333 #define ROBO_SWITCH_FLAG 0x80000000 3334 3335 /* Rx info */ 3336 LM_UINT32 RxStdDescCnt; 3337 LM_UINT32 RxStdQueuedCnt; 3338 LM_UINT32 RxStdProdIdx; 3339 3340 PT3_RCV_BD pRxStdBdVirt; 3341 LM_PHYSICAL_ADDRESS RxStdBdPhy; 3342 3343 LM_UINT32 RxPacketDescCnt; 3344 LM_RX_PACKET_Q RxPacketFreeQ; 3345 LM_RX_PACKET_Q RxPacketReceivedQ; 3346 3347 LM_PACKET *RxStdRing[T3_STD_RCV_RCB_ENTRY_COUNT]; 3348#if T3_JUMBO_RCV_RCB_ENTRY_COUNT 3349 LM_PACKET *RxJumboRing[T3_JUMBO_RCV_RCB_ENTRY_COUNT]; 3350#endif 3351 3352 /* Receive info. */ 3353 PT3_RCV_BD pRcvRetBdVirt; 3354 LM_PHYSICAL_ADDRESS RcvRetBdPhy; 3355 LM_UINT32 RcvRetConIdx; 3356 LM_UINT32 RcvRetRcbEntryCount; 3357 LM_UINT32 RcvRetRcbEntryCountMask; 3358 3359#if T3_JUMBO_RCV_RCB_ENTRY_COUNT 3360 LM_UINT32 RxJumboDescCnt; 3361 LM_UINT32 RxJumboBufferSize; 3362 LM_UINT32 RxJumboQueuedCnt; 3363 3364 LM_UINT32 RxJumboProdIdx; 3365 3366 PT3_RCV_BD pRxJumboBdVirt; 3367 LM_PHYSICAL_ADDRESS RxJumboBdPhy; 3368#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ 3369 3370 /* These values are used by the upper module to inform the protocol */ 3371 /* of the maximum transmit/receive packet size. */ 3372 LM_UINT32 TxMtu; /* Does not include CRC. */ 3373 LM_UINT32 RxMtu; /* Does not include CRC. */ 3374 3375#if INCLUDE_TCP_SEG_SUPPORT 3376 LM_UINT32 LargeSendMaxSize; 3377 LM_UINT32 LargeSendMinNumSeg; 3378#endif 3379 3380 /* We need to shadow the EMAC, Rx, Tx mode registers. With B0 silicon, */ 3381 /* we may have problems reading any MAC registers in 10mb mode. */ 3382 LM_UINT32 MacMode; 3383 LM_UINT32 RxMode; 3384 LM_UINT32 TxMode; 3385 3386 /* MiMode register. */ 3387 LM_UINT32 MiMode; 3388 3389 /* Host coalesce mode register. */ 3390 LM_UINT32 CoalesceMode; 3391 3392 /* Send info. */ 3393 LM_UINT32 TxPacketDescCnt; 3394 3395 /* Tx info. */ 3396 LM_TX_PACKET_Q TxPacketFreeQ; 3397 LM_TX_PACKET_Q TxPacketXmittedQ; 3398 3399 /* Pointers to SendBd. */ 3400 PT3_SND_BD pSendBdVirt; 3401 LM_PHYSICAL_ADDRESS SendBdPhy; /* Only valid for Host based Send BD. */ 3402 3403 /* Send producer and consumer indices. */ 3404 LM_UINT32 SendProdIdx; 3405 LM_UINT32 SendConIdx; 3406 3407 /* Number of BD left. */ 3408 MM_ATOMIC_T SendBdLeft; 3409 3410 T3_SND_BD ShadowSendBd[T3_SEND_RCB_ENTRY_COUNT]; 3411 LM_PACKET *SendRing[T3_SEND_RCB_ENTRY_COUNT]; 3412 3413 /* Counters. */ 3414 LM_RX_COUNTERS RxCounters; 3415 LM_TX_COUNTERS TxCounters; 3416 3417 /* Host coalescing parameters. */ 3418 LM_UINT32 RxCoalescingTicks; 3419 LM_UINT32 TxCoalescingTicks; 3420 LM_UINT32 RxMaxCoalescedFrames; 3421 LM_UINT32 TxMaxCoalescedFrames; 3422 LM_UINT32 StatsCoalescingTicks; 3423 LM_UINT32 RxCoalescingTicksDuringInt; 3424 LM_UINT32 TxCoalescingTicksDuringInt; 3425 LM_UINT32 RxMaxCoalescedFramesDuringInt; 3426 LM_UINT32 TxMaxCoalescedFramesDuringInt; 3427 3428 /* DMA water marks. */ 3429 LM_UINT32 DmaMbufLowMark; 3430 LM_UINT32 RxMacMbufLowMark; 3431 LM_UINT32 MbufHighMark; 3432 3433 /* Status block. */ 3434 PT3_STATUS_BLOCK pStatusBlkVirt; 3435 LM_PHYSICAL_ADDRESS StatusBlkPhy; 3436 3437 /* Statistics block. */ 3438 PT3_STATS_BLOCK pStatsBlkVirt; 3439 LM_PHYSICAL_ADDRESS StatsBlkPhy; 3440 3441 /* Current receive mask. */ 3442 LM_UINT32 ReceiveMask; 3443 3444 /* Task offload capabilities. */ 3445 LM_TASK_OFFLOAD TaskOffloadCap; 3446 3447 /* Task offload selected. */ 3448 LM_TASK_OFFLOAD TaskToOffload; 3449 3450 /* Wake up capability. */ 3451 LM_WAKE_UP_MODE WakeUpModeCap; 3452 3453 /* Wake up capability. */ 3454 LM_WAKE_UP_MODE WakeUpMode; 3455 3456 /* Flow control. */ 3457 LM_FLOW_CONTROL FlowControlCap; 3458 LM_FLOW_CONTROL FlowControl; 3459 3460 /* interrupt status tag */ 3461 LM_UINT32 LastTag; 3462 3463 /* Current node address. */ 3464 LM_UINT8 NodeAddress[8]; 3465 3466 /* The adapter's node address. */ 3467 LM_UINT8 PermanentNodeAddress[8]; 3468 3469 /* Adapter info. */ 3470 LM_UINT16 BusNum; // Init by the upper module. 3471 LM_UINT8 DevNum; // Init by the upper module. 3472 LM_UINT8 FunctNum; // Init by the upper module. 3473 LM_UINT16 PciVendorId; 3474 LM_UINT16 PciDeviceId; 3475 LM_UINT32 BondId; 3476 LM_UINT8 Irq; 3477 LM_UINT8 IntPin; 3478 LM_UINT8 CacheLineSize; 3479 LM_UINT8 PciRevId; 3480 LM_UINT32 PciCommandStatusWords; 3481 LM_UINT32 ChipRevId; 3482 LM_UINT16 SubsystemVendorId; 3483 LM_UINT16 SubsystemId; 3484 PLM_UINT8 pMappedMemBase; 3485 3486 /* Saved PCI configuration registers for restoring after a reset. */ 3487 LM_UINT32 SavedCacheLineReg; 3488 3489 /* Phy info. */ 3490 LM_UINT32 PhyAddr; 3491 LM_UINT32 PhyId; 3492 3493 /* Requested phy settings. */ 3494 LM_LINE_SPEED RequestedLineSpeed; 3495 LM_DUPLEX_MODE RequestedDuplexMode; 3496 3497 /* Disable auto-negotiation. */ 3498 LM_UINT32 DisableAutoNeg; 3499 3500 LM_UINT32 AutoNegJustInited; 3501 3502 /* Ways for the MAC to get link change interrupt. */ 3503 LM_UINT32 PhyIntMode; 3504 #define T3_PHY_INT_MODE_AUTO 0 3505 #define T3_PHY_INT_MODE_MI_INTERRUPT 1 3506 #define T3_PHY_INT_MODE_LINK_READY 2 3507 #define T3_PHY_INT_MODE_AUTO_POLLING 3 3508 3509 /* Ways to determine link change status. */ 3510 LM_UINT32 LinkChngMode; 3511 #define T3_LINK_CHNG_MODE_AUTO 0 3512 #define T3_LINK_CHNG_MODE_USE_STATUS_REG 1 3513 #define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK 2 3514 3515 LM_UINT32 LedCtrl; 3516 3517 /* WOL Speed */ 3518 LM_UINT32 WolSpeed; 3519 #define WOL_SPEED_10MB 1 3520 #define WOL_SPEED_100MB 2 3521 3522 LM_UINT32 PhyFlags; 3523 #define PHY_RESET_ON_INIT 0x01 3524 #define PHY_RESET_ON_LINKDOWN 0x02 3525 #define PHY_ADC_FIX 0x04 3526 #define PHY_CHECK_TAPS_AFTER_RESET 0x08 3527 #define PHY_5704_A0_FIX 0x10 3528 #define PHY_ETHERNET_WIRESPEED 0x20 3529 #define PHY_5705_5750_FIX 0x40 3530 #define PHY_NO_GIGABIT 0x80 3531 #define PHY_CAPACITIVE_COUPLING 0x100 3532 #define PHY_IS_FIBER 0x200 3533 #define PHY_FIBER_FALLBACK 0x400 3534 3535 3536 LM_UINT32 RestoreOnWakeUp; 3537 LM_LINE_SPEED WakeUpRequestedLineSpeed; 3538 LM_DUPLEX_MODE WakeUpRequestedDuplexMode; 3539 LM_UINT32 WakeUpDisableAutoNeg; 3540 3541 /* Current phy settings. */ 3542 LM_LINE_SPEED LineSpeed; 3543 LM_LINE_SPEED OldLineSpeed; 3544 LM_DUPLEX_MODE DuplexMode; 3545 LM_STATUS LinkStatus; 3546 LM_UINT32 advertising; 3547 LM_UINT32 advertising1000; 3548 3549 LM_UINT32 LoopBackMode; 3550 3551#define LM_MAC_LOOP_BACK_MODE 1 3552#define LM_PHY_LOOP_BACK_MODE 2 3553#define LM_EXT_LOOP_BACK_MODE 3 3554 3555 LM_LINE_SPEED SavedRequestedLineSpeed; 3556 LM_DUPLEX_MODE SavedRequestedDuplexMode; 3557 LM_UINT32 SavedDisableAutoNeg; 3558 3559 LM_UINT32 MulticastHash[4]; 3560 3561 LM_UINT32 AsfFlags; 3562 3563#define ASF_ENABLED 1 3564#define ASF_NEW_HANDSHAKE 2 /* if set, this bit implies ASF enabled as well */ 3565 3566 /* Split Mode flags */ 3567 LM_UINT32 SplitModeMaxReq; 3568 3569 #define SPLIT_MODE_5704_MAX_REQ 3 3570 3571 /* Init flag. */ 3572 LM_BOOL InitDone; 3573 3574 /* Shutdown flag. Set by the upper module. */ 3575 LM_BOOL ShuttingDown; 3576 3577 /* Flag to determine whether to call LM_QueueRxPackets or not in */ 3578 /* LM_ResetAdapter routine. */ 3579 LM_BOOL QueueRxPackets; 3580 LM_BOOL QueueAgain; 3581 3582 LM_UINT32 MbufBase; 3583 LM_UINT32 MbufSize; 3584 3585 LM_UINT32 NvramSize; 3586 3587#if INCLUDE_TBI_SUPPORT 3588 /* Autoneg state info. */ 3589 AN_STATE_INFO AnInfo; 3590 3591 LM_UINT32 TbiFlags; 3592 /* set if we have a SERDES PHY. */ 3593 #define ENABLE_TBI_FLAG 0x1 3594 #define TBI_POLLING_INTR_FLAG 0x2 3595 #define TBI_PURE_POLLING_FLAG 0x4 3596 #define TBI_POLLING_FLAGS (TBI_POLLING_INTR_FLAG | TBI_PURE_POLLING_FLAG) 3597 #define TBI_DO_PREEMPHASIS 0x8 3598 3599 LM_UINT32 IgnoreTbiLinkChange; 3600#endif 3601#ifdef BCM_NAPI_RXPOLL 3602 volatile LM_UINT32 RxPoll; 3603#endif 3604 char PartNo[24]; 3605 char BootCodeVer[16]; 3606 char IPMICodeVer[24]; 3607 char BusSpeedStr[24]; 3608 3609 FLASHINFO flashinfo; 3610 LM_UINT8 flashbuffer[256]; 3611} LM_DEVICE_BLOCK; 3612 3613 3614#define T3_REG_CPU_VIEW 0xc0000000 3615 3616#define T3_BLOCK_DMA_RD (1 << 0) 3617#define T3_BLOCK_DMA_COMP (1 << 1) 3618#define T3_BLOCK_RX_BD_INITIATOR (1 << 2) 3619#define T3_BLOCK_RX_BD_COMP (1 << 3) 3620#define T3_BLOCK_DMA_WR (1 << 4) 3621#define T3_BLOCK_MSI_HANDLER (1 << 5) 3622#define T3_BLOCK_RX_LIST_PLMT (1 << 6) 3623#define T3_BLOCK_RX_LIST_SELECTOR (1 << 7) 3624#define T3_BLOCK_RX_DATA_INITIATOR (1 << 8) 3625#define T3_BLOCK_RX_DATA_COMP (1 << 9) 3626#define T3_BLOCK_HOST_COALESING (1 << 10) 3627#define T3_BLOCK_MAC_RX_ENGINE (1 << 11) 3628#define T3_BLOCK_MBUF_CLUSTER_FREE (1 << 12) 3629#define T3_BLOCK_SEND_BD_INITIATOR (1 << 13) 3630#define T3_BLOCK_SEND_BD_COMP (1 << 14) 3631#define T3_BLOCK_SEND_BD_SELECTOR (1 << 15) 3632#define T3_BLOCK_SEND_DATA_INITIATOR (1 << 16) 3633#define T3_BLOCK_SEND_DATA_COMP (1 << 17) 3634#define T3_BLOCK_MAC_TX_ENGINE (1 << 18) 3635#define T3_BLOCK_MEM_ARBITOR (1 << 19) 3636#define T3_BLOCK_MBUF_MANAGER (1 << 20) 3637#define T3_BLOCK_MAC_GLOBAL (1 << 21) 3638 3639#define LM_ENABLE 1 3640#define LM_DISABLE 2 3641 3642#define RX_CPU_EVT_SW0 0 3643#define RX_CPU_EVT_SW1 1 3644#define RX_CPU_EVT_RLP 2 3645#define RX_CPU_EVT_SW3 3 3646#define RX_CPU_EVT_RLS 4 3647#define RX_CPU_EVT_SW4 5 3648#define RX_CPU_EVT_RX_BD_COMP 6 3649#define RX_CPU_EVT_SW5 7 3650#define RX_CPU_EVT_RDI 8 3651#define RX_CPU_EVT_DMA_WR 9 3652#define RX_CPU_EVT_DMA_RD 10 3653#define RX_CPU_EVT_SWQ 11 3654#define RX_CPU_EVT_SW6 12 3655#define RX_CPU_EVT_RDC 13 3656#define RX_CPU_EVT_SW7 14 3657#define RX_CPU_EVT_HOST_COALES 15 3658#define RX_CPU_EVT_SW8 16 3659#define RX_CPU_EVT_HIGH_DMA_WR 17 3660#define RX_CPU_EVT_HIGH_DMA_RD 18 3661#define RX_CPU_EVT_SW9 19 3662#define RX_CPU_EVT_DMA_ATTN 20 3663#define RX_CPU_EVT_LOW_P_MBOX 21 3664#define RX_CPU_EVT_HIGH_P_MBOX 22 3665#define RX_CPU_EVT_SW10 23 3666#define RX_CPU_EVT_TX_CPU_ATTN 24 3667#define RX_CPU_EVT_MAC_ATTN 25 3668#define RX_CPU_EVT_RX_CPU_ATTN 26 3669#define RX_CPU_EVT_FLOW_ATTN 27 3670#define RX_CPU_EVT_SW11 28 3671#define RX_CPU_EVT_TIMER 29 3672#define RX_CPU_EVT_SW12 30 3673#define RX_CPU_EVT_SW13 31 3674 3675/* RX-CPU event */ 3676#define RX_CPU_EVENT_SW_EVENT0 (1 << RX_CPU_EVT_SW0) 3677#define RX_CPU_EVENT_SW_EVENT1 (1 << RX_CPU_EVT_SW1) 3678#define RX_CPU_EVENT_RLP (1 << RX_CPU_EVT_RLP) 3679#define RX_CPU_EVENT_SW_EVENT3 (1 << RX_CPU_EVT_SW3) 3680#define RX_CPU_EVENT_RLS (1 << RX_CPU_EVT_RLS) 3681#define RX_CPU_EVENT_SW_EVENT4 (1 << RX_CPU_EVT_SW4) 3682#define RX_CPU_EVENT_RX_BD_COMP (1 << RX_CPU_EVT_RX_BD_COMP) 3683#define RX_CPU_EVENT_SW_EVENT5 (1 << RX_CPU_EVT_SW5) 3684#define RX_CPU_EVENT_RDI (1 << RX_CPU_EVT_RDI) 3685#define RX_CPU_EVENT_DMA_WR (1 << RX_CPU_EVT_DMA_WR) 3686#define RX_CPU_EVENT_DMA_RD (1 << RX_CPU_EVT_DMA_RD) 3687#define RX_CPU_EVENT_SWQ (1 << RX_CPU_EVT_SWQ) 3688#define RX_CPU_EVENT_SW_EVENT6 (1 << RX_CPU_EVT_SW6) 3689#define RX_CPU_EVENT_RDC (1 << RX_CPU_EVT_RDC) 3690#define RX_CPU_EVENT_SW_EVENT7 (1 << RX_CPU_EVT_SW7) 3691#define RX_CPU_EVENT_HOST_COALES (1 << RX_CPU_EVT_HOST_COALES) 3692#define RX_CPU_EVENT_SW_EVENT8 (1 << RX_CPU_EVT_SW8) 3693#define RX_CPU_EVENT_HIGH_DMA_WR (1 << RX_CPU_EVT_HIGH_DMA_WR) 3694#define RX_CPU_EVENT_HIGH_DMA_RD (1 << RX_CPU_EVT_HIGH_DMA_RD) 3695#define RX_CPU_EVENT_SW_EVENT9 (1 << RX_CPU_EVT_SW9) 3696#define RX_CPU_EVENT_DMA_ATTN (1 << RX_CPU_EVT_DMA_ATTN) 3697#define RX_CPU_EVENT_LOW_P_MBOX (1 << RX_CPU_EVT_LOW_P_MBOX) 3698#define RX_CPU_EVENT_HIGH_P_MBOX (1 << RX_CPU_EVT_HIGH_P_MBOX) 3699#define RX_CPU_EVENT_SW_EVENT10 (1 << RX_CPU_EVT_SW10) 3700#define RX_CPU_EVENT_TX_CPU_ATTN (1 << RX_CPU_EVT_TX_CPU_ATTN) 3701#define RX_CPU_EVENT_MAC_ATTN (1 << RX_CPU_EVT_MAC_ATTN) 3702#define RX_CPU_EVENT_RX_CPU_ATTN (1 << RX_CPU_EVT_RX_CPU_ATTN) 3703#define RX_CPU_EVENT_FLOW_ATTN (1 << RX_CPU_EVT_FLOW_ATTN) 3704#define RX_CPU_EVENT_SW_EVENT11 (1 << RX_CPU_EVT_SW11) 3705#define RX_CPU_EVENT_TIMER (1 << RX_CPU_EVT_TIMER) 3706#define RX_CPU_EVENT_SW_EVENT12 (1 << RX_CPU_EVT_SW12) 3707#define RX_CPU_EVENT_SW_EVENT13 (1 << RX_CPU_EVT_SW13) 3708 3709#define RX_CPU_MASK (RX_CPU_EVENT_SW_EVENT0 | \ 3710 RX_CPU_EVENT_RLP | \ 3711 RX_CPU_EVENT_RDI | \ 3712 RX_CPU_EVENT_RDC) 3713 3714#define TX_CPU_EVT_SW0 0 3715#define TX_CPU_EVT_SW1 1 3716#define TX_CPU_EVT_SW2 2 3717#define TX_CPU_EVT_SW3 3 3718#define TX_CPU_EVT_TX_MAC 4 3719#define TX_CPU_EVT_SW4 5 3720#define TX_CPU_EVT_SBDC 6 3721#define TX_CPU_EVT_SW5 7 3722#define TX_CPU_EVT_SDI 8 3723#define TX_CPU_EVT_DMA_WR 9 3724#define TX_CPU_EVT_DMA_RD 10 3725#define TX_CPU_EVT_SWQ 11 3726#define TX_CPU_EVT_SW6 12 3727#define TX_CPU_EVT_SDC 13 3728#define TX_CPU_EVT_SW7 14 3729#define TX_CPU_EVT_HOST_COALES 15 3730#define TX_CPU_EVT_SW8 16 3731#define TX_CPU_EVT_HIGH_DMA_WR 17 3732#define TX_CPU_EVT_HIGH_DMA_RD 18 3733#define TX_CPU_EVT_SW9 19 3734#define TX_CPU_EVT_DMA_ATTN 20 3735#define TX_CPU_EVT_LOW_P_MBOX 21 3736#define TX_CPU_EVT_HIGH_P_MBOX 22 3737#define TX_CPU_EVT_SW10 23 3738#define TX_CPU_EVT_RX_CPU_ATTN 24 3739#define TX_CPU_EVT_MAC_ATTN 25 3740#define TX_CPU_EVT_TX_CPU_ATTN 26 3741#define TX_CPU_EVT_FLOW_ATTN 27 3742#define TX_CPU_EVT_SW11 28 3743#define TX_CPU_EVT_TIMER 29 3744#define TX_CPU_EVT_SW12 30 3745#define TX_CPU_EVT_SW13 31 3746 3747 3748/* TX-CPU event */ 3749#define TX_CPU_EVENT_SW_EVENT0 (1 << TX_CPU_EVT_SW0) 3750#define TX_CPU_EVENT_SW_EVENT1 (1 << TX_CPU_EVT_SW1) 3751#define TX_CPU_EVENT_SW_EVENT2 (1 << TX_CPU_EVT_SW2) 3752#define TX_CPU_EVENT_SW_EVENT3 (1 << TX_CPU_EVT_SW3) 3753#define TX_CPU_EVENT_TX_MAC (1 << TX_CPU_EVT_TX_MAC) 3754#define TX_CPU_EVENT_SW_EVENT4 (1 << TX_CPU_EVT_SW4) 3755#define TX_CPU_EVENT_SBDC (1 << TX_CPU_EVT_SBDC) 3756#define TX_CPU_EVENT_SW_EVENT5 (1 << TX_CPU_EVT_SW5) 3757#define TX_CPU_EVENT_SDI (1 << TX_CPU_EVT_SDI) 3758#define TX_CPU_EVENT_DMA_WR (1 << TX_CPU_EVT_DMA_WR) 3759#define TX_CPU_EVENT_DMA_RD (1 << TX_CPU_EVT_DMA_RD) 3760#define TX_CPU_EVENT_SWQ (1 << TX_CPU_EVT_SWQ) 3761#define TX_CPU_EVENT_SW_EVENT6 (1 << TX_CPU_EVT_SW6) 3762#define TX_CPU_EVENT_SDC (1 << TX_CPU_EVT_SDC) 3763#define TX_CPU_EVENT_SW_EVENT7 (1 << TX_CPU_EVT_SW7) 3764#define TX_CPU_EVENT_HOST_COALES (1 << TX_CPU_EVT_HOST_COALES) 3765#define TX_CPU_EVENT_SW_EVENT8 (1 << TX_CPU_EVT_SW8) 3766#define TX_CPU_EVENT_HIGH_DMA_WR (1 << TX_CPU_EVT_HIGH_DMA_WR) 3767#define TX_CPU_EVENT_HIGH_DMA_RD (1 << TX_CPU_EVT_HIGH_DMA_RD) 3768#define TX_CPU_EVENT_SW_EVENT9 (1 << TX_CPU_EVT_SW9) 3769#define TX_CPU_EVENT_DMA_ATTN (1 << TX_CPU_EVT_DMA_ATTN) 3770#define TX_CPU_EVENT_LOW_P_MBOX (1 << TX_CPU_EVT_LOW_P_MBOX) 3771#define TX_CPU_EVENT_HIGH_P_MBOX (1 << TX_CPU_EVT_HIGH_P_MBOX) 3772#define TX_CPU_EVENT_SW_EVENT10 (1 << TX_CPU_EVT_SW10) 3773#define TX_CPU_EVENT_RX_CPU_ATTN (1 << TX_CPU_EVT_RX_CPU_ATTN) 3774#define TX_CPU_EVENT_MAC_ATTN (1 << TX_CPU_EVT_MAC_ATTN) 3775#define TX_CPU_EVENT_TX_CPU_ATTN (1 << TX_CPU_EVT_TX_CPU_ATTN) 3776#define TX_CPU_EVENT_FLOW_ATTN (1 << TX_CPU_EVT_FLOW_ATTN) 3777#define TX_CPU_EVENT_SW_EVENT11 (1 << TX_CPU_EVT_SW11) 3778#define TX_CPU_EVENT_TIMER (1 << TX_CPU_EVT_TIMER) 3779#define TX_CPU_EVENT_SW_EVENT12 (1 << TX_CPU_EVT_SW12) 3780#define TX_CPU_EVENT_SW_EVENT13 (1 << TX_CPU_EVT_SW13) 3781 3782 3783#define TX_CPU_MASK (TX_CPU_EVENT_SW_EVENT0 | \ 3784 TX_CPU_EVENT_SDI | \ 3785 TX_CPU_EVENT_SDC) 3786 3787 3788#define T3_FTQ_TYPE1_UNDERFLOW_BIT (1 << 29) 3789#define T3_FTQ_TYPE1_PASS_BIT (1 << 30) 3790#define T3_FTQ_TYPE1_SKIP_BIT (1 << 31) 3791 3792#define T3_FTQ_TYPE2_UNDERFLOW_BIT (1 << 13) 3793#define T3_FTQ_TYPE2_PASS_BIT (1 << 14) 3794#define T3_FTQ_TYPE2_SKIP_BIT (1 << 15) 3795 3796#define T3_QID_DMA_READ 1 3797#define T3_QID_DMA_HIGH_PRI_READ 2 3798#define T3_QID_DMA_COMP_DX 3 3799#define T3_QID_SEND_BD_COMP 4 3800#define T3_QID_SEND_DATA_INITIATOR 5 3801#define T3_QID_DMA_WRITE 6 3802#define T3_QID_DMA_HIGH_PRI_WRITE 7 3803#define T3_QID_SW_TYPE_1 8 3804#define T3_QID_SEND_DATA_COMP 9 3805#define T3_QID_HOST_COALESCING 10 3806#define T3_QID_MAC_TX 11 3807#define T3_QID_MBUF_CLUSTER_FREE 12 3808#define T3_QID_RX_BD_COMP 13 3809#define T3_QID_RX_LIST_PLM 14 3810#define T3_QID_RX_DATA_BD_INITIATOR 15 3811#define T3_QID_RX_DATA_COMP 16 3812#define T3_QID_SW_TYPE2 17 3813 3814LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice, 3815 PT3_FWIMG_INFO pFwImg, 3816 LM_UINT32 LoadCpu, 3817 LM_UINT32 StartCpu); 3818 3819/******************************************************************************/ 3820/* NIC register read/write macros. */ 3821/******************************************************************************/ 3822 3823/* MAC register access. */ 3824LM_UINT32 LM_RegRd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); 3825 3826LM_VOID LM_RegRdBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); 3827 3828LM_VOID LM_RegWr(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, 3829 LM_UINT32 Value32, LM_UINT32 ReadBack); 3830 3831LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); 3832LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, 3833 LM_UINT32 Value32); 3834 3835/* MAC memory access. */ 3836LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr); 3837 3838LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, 3839 LM_UINT32 Value32); 3840 3841#define MB_REG_WR(pDevice, OffsetName, Value32) \ 3842 ((pDevice)->Flags & UNDI_FIX_FLAG) ? \ 3843 LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600, \ 3844 Value32) : \ 3845 (void) MM_MEMWRITEL(&((pDevice)->pMemView->OffsetName), Value32) 3846 3847#define MB_REG_RD(pDevice, OffsetName) \ 3848 (((pDevice)->Flags & UNDI_FIX_FLAG) ? \ 3849 LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600) : \ 3850 MM_MEMREADL(&((pDevice)->pMemView->OffsetName))) 3851 3852#define REG_RD(pDevice, OffsetName) \ 3853 LM_RegRd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) 3854 3855#define REG_RD_BACK(pDevice, OffsetName) \ 3856 LM_RegRdBack(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) 3857 3858#define REG_WR(pDevice, OffsetName, Value32) \ 3859 LM_RegWr(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32, TRUE) 3860 3861#define RAW_REG_WR(pDevice, OffsetName, Value32) \ 3862 LM_RegWr(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32, FALSE) 3863 3864#define REG_RD_OFFSET(pDevice, Offset) \ 3865 MM_MEMREADL(((LM_UINT8 *) (pDevice)->pMemView + Offset)) 3866 3867#define REG_WR_OFFSET(pDevice, Offset, Value32) \ 3868 MM_MEMWRITEL(((LM_UINT8 *) (pDevice)->pMemView + Offset), Value32) 3869 3870#define MEM_RD(pDevice, AddrName) \ 3871 LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) 3872#define MEM_WR(pDevice, AddrName, Value32) \ 3873 LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) 3874 3875#define MEM_RD_OFFSET(pDevice, Offset) \ 3876 LM_MemRdInd(pDevice, Offset) 3877#define MEM_WR_OFFSET(pDevice, Offset, Value32) \ 3878 LM_MemWrInd(pDevice, Offset, Value32) 3879 3880 3881#endif /* TIGON3_H */ 3882 3883