1/**************************************************************************** 2 * Copyright(c) 2000-2004 Broadcom Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation. 7 * 8 * Name: nicext.h 9 * 10 * Description: Broadcom Network Interface Card Extension (NICE) is an 11 * extension to Linux NET device kernel mode drivers. 12 * NICE is designed to provide additional functionalities, 13 * such as receive packet intercept. To support Broadcom NICE, 14 * the network device driver can be modified by adding an 15 * device ioctl handler and by indicating receiving packets 16 * to the NICE receive handler. Broadcom NICE will only be 17 * enabled by a NICE-aware intermediate driver, such as 18 * Broadcom Advanced Server Program Driver (BASP). When NICE 19 * is not enabled, the modified network device drivers 20 * functions exactly as other non-NICE aware drivers. 21 * 22 * Author: Frankie Fan 23 * 24 * Created: September 17, 2000 25 * 26 ****************************************************************************/ 27#ifndef _nicext_h_ 28#define _nicext_h_ 29 30/* 31 * ioctl for NICE 32 */ 33#define SIOCNICE SIOCDEVPRIVATE+7 34 35/* 36 * SIOCNICE: 37 * 38 * The following structure needs to be less than IFNAMSIZ (16 bytes) because 39 * we're overloading ifreq.ifr_ifru. 40 * 41 * If 16 bytes is not enough, we should consider relaxing this because 42 * this is no field after ifr_ifru in the ifreq structure. But we may 43 * run into future compatiability problem in case of changing struct ifreq. 44 */ 45struct nice_req 46{ 47 __u32 cmd; 48 49 union 50 { 51#ifdef __KERNEL__ 52 /* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */ 53 /* cmd = NICE_CMD_SET_RX_NAPI or NICE_CMD_GET_RX_NAPI */ 54 struct 55 { 56 void (*nrqus1_rx)( struct sk_buff*, void* ); 57 void* nrqus1_ctx; 58 } nrqu_nrqus1; 59 60 /* cmd = NICE_CMD_QUERY_SUPPORT */ 61 struct 62 { 63 __u32 nrqus2_magic; 64 __u32 nrqus2_support_rx:1; 65 __u32 nrqus2_support_vlan:1; 66 __u32 nrqus2_support_get_speed:1; 67 __u32 nrqus2_support_rx_napi:1; 68 } nrqu_nrqus2; 69#endif 70 71 void *align_ptr; /* this field is not used, it is to align the union */ 72 /* in 64-bit user mode */ 73 74 /* cmd = NICE_CMD_GET_SPEED - in Mbps or 0 if link down */ 75 /* cmd = NICE_CMD_ENABLE_EXT_LOOPBACK - in Mbps */ 76 struct 77 { 78 unsigned int nrqus3_speed; /* 1000 = Gb, 100 = 100mbs, 10 = 10mbs */ 79 } nrqu_nrqus3; 80 81 /* cmd = NICE_CMD_BLINK_LED */ 82 struct 83 { 84 unsigned int nrqus4_blink_time; /* blink duration in seconds */ 85 } nrqu_nrqus4; 86 87 /* cmd = NICE_CMD_REG_READ */ 88 /* cmd = NICE_CMD_REG_WRITE */ 89 /* cmd = NICE_CMD_MEM_READ */ 90 /* cmd = NICE_CMD_MEM_WRITE */ 91 /* cmd = NICE_CMD_REG_READ_DIRECT */ 92 /* cmd = NICE_CMD_REG_WRITE_DIRECT */ 93 /* cmd = NICE_CMD_CFG_READ32 */ 94 /* cmd = NICE_CMD_CFG_READ16 */ 95 /* cmd = NICE_CMD_CFG_READ8 */ 96 /* cmd = NICE_CMD_CFG_WRITE32 */ 97 /* cmd = NICE_CMD_CFG_WRITE16 */ 98 /* cmd = NICE_CMD_CFG_WRITE8 */ 99 struct 100 { 101 unsigned int nrqus5_offset; /* offset */ 102 unsigned int nrqus5_data; /* value */ 103 } nrqu_nrqus5; 104 105 /* cmd = NICE_CMD_INTERRUPT_TEST */ 106 struct 107 { 108 unsigned int nrqus6_intr_test_result; /* 1 == pass */ 109 } nrqu_nrqus6; 110 111 /* cmd = NICE_CMD_KMALLOC_PHYS */ 112 /* cmd = NICE_CMD_KFREE_PHYS */ 113 /* These commands allow the diagnostics app. to allocate and free */ 114 /* PCI consistent memory for DMA tests */ 115 struct 116 { 117 unsigned int nrqus7_size; /* size(bytes) to allocate, not used */ 118 /* when cmd is NICE_CMD_KFREE_PHYS. */ 119 __u32 nrqus7_phys_addr_lo;/* CPU physical address allocated or */ 120 __u32 nrqus7_phys_addr_hi;/* to be freed. */ 121 /* PCI physical address is contained in */ 122 /* the 1st 64 bit of the allocated */ 123 /* buffer. Use open("/dev/mem")/lseek() */ 124 /* and read()/write() to a access */ 125 /* buffer in user space. */ 126 /* mmap() only works on x86. */ 127 } nrqu_nrqus7; 128 129 /* cmd = NICE_CMD_SET_WRITE_PROTECT */ 130 struct 131 { 132 unsigned int nrqus8_data; /* 1 == set write protect, 0 == clear write protect */ 133 } nrqu_nrqus8; 134 135 /* cmd = NICE_CMD_GET_STATS_BLOCK */ 136 struct 137 { 138 void *nrqus9_useraddr; /* user space address for the stats block */ 139 unsigned int nrqus9_size;/* size (in bytes) */ 140 /* (0x6c0 for the whole block) */ 141 } nrqu_nrqus9; 142 143 /* cmd = NICE_CMD_LOOPBACK_TEST */ 144 struct 145 { 146 unsigned char nrqus10_looptype; 147 unsigned char nrqus10_loopspeed; 148 } nrqu_nrqus10; 149 150 /* cmd = NICE_CMD_KMAP_PHYS/KUNMAP_PHYS */ 151 struct 152 { 153 int nrqus11_rw; /* direction */ 154 void *nrqus11_uaddr; /* ptr to mem allocated in user space */ 155 /* when cmd is NICE_CMD_KFREE_PHYS. */ 156 __u32 nrqus11_phys_addr_lo;/* CPU physical address allocated or */ 157 __u32 nrqus11_phys_addr_hi;/* to be freed. */ 158 /* PCI physical address is contained in */ 159 /* the 1st 64 bit of the allocated */ 160 /* buffer. Use open("/dev/mem")/lseek() */ 161 /* and read()/write() to a access */ 162 /* buffer in user space. */ 163 /* mmap() only works on x86. */ 164 } nrqu_nrqus11; 165 } nrq_nrqu; 166}; 167 168#define nrq_rx nrq_nrqu.nrqu_nrqus1.nrqus1_rx 169#define nrq_ctx nrq_nrqu.nrqu_nrqus1.nrqus1_ctx 170#define nrq_support_rx nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx 171#define nrq_magic nrq_nrqu.nrqu_nrqus2.nrqus2_magic 172#define nrq_support_vlan nrq_nrqu.nrqu_nrqus2.nrqus2_support_vlan 173#define nrq_support_get_speed nrq_nrqu.nrqu_nrqus2.nrqus2_support_get_speed 174#define nrq_support_rx_napi nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx_napi 175#define nrq_speed nrq_nrqu.nrqu_nrqus3.nrqus3_speed 176#define nrq_blink_time nrq_nrqu.nrqu_nrqus4.nrqus4_blink_time 177#define nrq_offset nrq_nrqu.nrqu_nrqus5.nrqus5_offset 178#define nrq_data nrq_nrqu.nrqu_nrqus5.nrqus5_data 179#define nrq_intr_test_result nrq_nrqu.nrqu_nrqus6.nrqus6_intr_test_result 180 181#define nrq_size nrq_nrqu.nrqu_nrqus7.nrqus7_size 182#define nrq_phys_addr_lo nrq_nrqu.nrqu_nrqus7.nrqus7_phys_addr_lo 183#define nrq_phys_addr_hi nrq_nrqu.nrqu_nrqus7.nrqus7_phys_addr_hi 184 185#define nrq_rw nrq_nrqu.nrqu_nrqus11.nrqus11_rw 186#define nrq_puaddr nrq_nrqu.nrqu_nrqus11.nrqus11_uaddr 187#define nrq_phys_add_lo nrq_nrqu.nrqu_nrqus11.nrqus11_phys_addr_lo 188#define nrq_phys_add_hi nrq_nrqu.nrqu_nrqus11.nrqus11_phys_addr_hi 189 190#define nrq_write_protect nrq_nrqu.nrqu_nrqus8.nrqus8_data 191#define nrq_stats_useraddr nrq_nrqu.nrqu_nrqus9.nrqus9_useraddr 192#define nrq_stats_size nrq_nrqu.nrqu_nrqus9.nrqus9_size 193 194#define nrq_looptype nrq_nrqu.nrqu_nrqus10.nrqus10_looptype 195#define nrq_loopspeed nrq_nrqu.nrqu_nrqus10.nrqus10_loopspeed 196 197/* 198 * magic constants 199 */ 200#define NICE_REQUESTOR_MAGIC 0x4543494E // NICE in ascii 201#define NICE_DEVICE_MAGIC 0x4E494345 // ECIN in ascii 202 203#define NICE_LOOPBACK_TESTTYPE_MAC 0x1 204#define NICE_LOOPBACK_TESTTYPE_PHY 0x2 205#define NICE_LOOPBACK_TESTTYPE_EXT 0x4 206 207#define NICE_LOOPBACK_TEST_SPEEDMASK 0x3 208#define NICE_LOOPBACK_TEST_10MBPS 0x1 209#define NICE_LOOPBACK_TEST_100MBPS 0x2 210#define NICE_LOOPBACK_TEST_1000MBPS 0x3 211 212 213/* 214 * command field 215 */ 216typedef enum { 217 NICE_CMD_QUERY_SUPPORT = 0x00000001, 218 NICE_CMD_SET_RX = 0x00000002, 219 NICE_CMD_GET_RX = 0x00000003, 220 NICE_CMD_GET_SPEED = 0x00000004, 221 NICE_CMD_BLINK_LED = 0x00000005, 222 NICE_CMD_DIAG_SUSPEND = 0x00000006, 223 NICE_CMD_DIAG_RESUME = 0x00000007, 224 NICE_CMD_REG_READ = 0x00000008, 225 NICE_CMD_REG_WRITE = 0x00000009, 226 NICE_CMD_MEM_READ = 0x0000000a, 227 NICE_CMD_MEM_WRITE = 0x0000000b, 228 NICE_CMD_ENABLE_MAC_LOOPBACK = 0x0000000c, 229 NICE_CMD_DISABLE_MAC_LOOPBACK = 0x0000000d, 230 NICE_CMD_ENABLE_PHY_LOOPBACK = 0x0000000e, 231 NICE_CMD_DISABLE_PHY_LOOPBACK = 0x0000000f, 232 NICE_CMD_INTERRUPT_TEST = 0x00000010, 233 NICE_CMD_SET_WRITE_PROTECT = 0x00000011, 234 NICE_CMD_SET_RX_NAPI = 0x00000012, 235 NICE_CMD_GET_RX_NAPI = 0x00000013, 236 NICE_CMD_ENABLE_EXT_LOOPBACK = 0x00000014, 237 NICE_CMD_DISABLE_EXT_LOOPBACK = 0x00000015, 238 NICE_CMD_CFG_READ32 = 0x00000016, 239 NICE_CMD_CFG_READ16 = 0x00000017, 240 NICE_CMD_CFG_READ8 = 0x00000018, 241 NICE_CMD_CFG_WRITE32 = 0x00000019, 242 NICE_CMD_CFG_WRITE16 = 0x0000001a, 243 NICE_CMD_CFG_WRITE8 = 0x0000001b, 244 245 NICE_CMD_REG_READ_DIRECT = 0x0000001e, 246 NICE_CMD_REG_WRITE_DIRECT = 0x0000001f, 247 NICE_CMD_RESET = 0x00000020, 248 NICE_CMD_KMALLOC_PHYS = 0x00000021, 249 NICE_CMD_KFREE_PHYS = 0x00000022, 250 NICE_CMD_GET_STATS_BLOCK = 0x00000023, 251 NICE_CMD_CLR_STATS_BLOCK = 0x00000024, 252 NICE_CMD_LOOPBACK_TEST = 0x00000025, 253 NICE_CMD_KMAP_PHYS = 0x00000026, 254 NICE_CMD_KUNMAP_PHYS = 0x00000027, 255 NICE_CMD_MAX 256} nice_cmds; 257 258#endif // _nicext_h_ 259 260