Searched refs:CLK_TOP_ETHPLL_500M (Results 1 - 10 of 10) sorted by relevance

/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c180 FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1),
716 GATE_ETH_HIF1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
718 GATE_ETH_HIF1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
726 GATE_ETH_HIF1(CLK_HIFSYS_USB0PHY, CLK_TOP_ETHPLL_500M, 21),
727 GATE_ETH_HIF1(CLK_HIFSYS_USB1PHY, CLK_TOP_ETHPLL_500M, 22),
728 GATE_ETH_HIF1(CLK_HIFSYS_PCIE0, CLK_TOP_ETHPLL_500M, 24),
729 GATE_ETH_HIF1(CLK_HIFSYS_PCIE1, CLK_TOP_ETHPLL_500M, 25),
730 GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h95 #define CLK_TOP_ETHPLL_500M 82 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h95 #define CLK_TOP_ETHPLL_500M 82 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h95 #define CLK_TOP_ETHPLL_500M 82 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h95 #define CLK_TOP_ETHPLL_500M 82 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h95 #define CLK_TOP_ETHPLL_500M 82 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h95 #define CLK_TOP_ETHPLL_500M 82 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h95 #define CLK_TOP_ETHPLL_500M 82 macro
/u-boot/include/dt-bindings/clock/
H A Dmt7623-clk.h95 #define CLK_TOP_ETHPLL_500M 82 macro
/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt2701-clk.h81 #define CLK_TOP_ETHPLL_500M 71 macro

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