Searched refs:CK_TOP_APLL2_D4 (Results 1 - 18 of 18) sorted by relevance
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 68 #define CK_TOP_APLL2_D4 14 macro
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H A D | mt7981-clk.h | 72 #define CK_TOP_APLL2_D4 18 macro
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/u-boot/arch/arm/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 68 #define CK_TOP_APLL2_D4 14 macro
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H A D | mt7981-clk.h | 72 #define CK_TOP_APLL2_D4 18 macro
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/u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 68 #define CK_TOP_APLL2_D4 14 macro
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H A D | mt7981-clk.h | 72 #define CK_TOP_APLL2_D4 18 macro
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/u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 68 #define CK_TOP_APLL2_D4 14 macro
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H A D | mt7981-clk.h | 72 #define CK_TOP_APLL2_D4 18 macro
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/u-boot/arch/x86/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 68 #define CK_TOP_APLL2_D4 14 macro
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H A D | mt7981-clk.h | 72 #define CK_TOP_APLL2_D4 18 macro
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/u-boot/arch/mips/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 68 #define CK_TOP_APLL2_D4 14 macro
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H A D | mt7981-clk.h | 72 #define CK_TOP_APLL2_D4 18 macro
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/u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 68 #define CK_TOP_APLL2_D4 14 macro
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H A D | mt7981-clk.h | 72 #define CK_TOP_APLL2_D4 18 macro
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/u-boot/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 68 #define CK_TOP_APLL2_D4 14 macro
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H A D | mt7981-clk.h | 72 #define CK_TOP_APLL2_D4 18 macro
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/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt7986.c | 63 PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4), 186 static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 }; 196 static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
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H A D | clk-mt7981.c | 67 PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4), 216 static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 }; 221 static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
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