Searched refs:GPA0 (Results 1 - 4 of 4) sorted by relevance
/seL4-camkes-master/projects/util_libs/libplatsupport/src/plat/exynos5/ |
H A D | mux.c | 28 { .port = GPA0, .pin = 7, .value = MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)}, 29 { .port = GPA0, .pin = 6, .value = MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)}, 60 { .port = GPA0, .pin = 0, .value = UART_MUX_VAL}, 61 { .port = GPA0, .pin = 1, .value = UART_MUX_VAL}, 65 { .port = GPA0, .pin = 2, .value = UART_MUX_VAL}, 66 { .port = GPA0, .pin = 3, .value = UART_MUX_VAL},
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/seL4-camkes-master/projects/util_libs/libplatsupport/src/plat/exynos4/ |
H A D | mux.c | 28 { .port = GPA0, .pin = 6, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)}, 29 { .port = GPA0, .pin = 7, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)}, 88 { .port = GPA0, .pin = 0, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, 89 { .port = GPA0, .pin = 1, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, 93 { .port = GPA0, .pin = 2, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, 94 { .port = GPA0, .pin = 3, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, 98 { .port = GPA0, .pin = 4, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, 99 { .port = GPA0, .pin = 5, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, 103 { .port = GPA0, .pin = 6, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)}, 104 { .port = GPA0, [all...] |
/seL4-camkes-master/projects/util_libs/libplatsupport/plat_include/exynos4/platsupport/plat/ |
H A D | gpio.h | 70 GPA0 = GPIOPORT(LEFT, 0), /* 0x000 */ enumerator in enum:gpio_port
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/seL4-camkes-master/projects/util_libs/libplatsupport/plat_include/exynos5/platsupport/plat/ |
H A D | gpio.h | 70 GPA0 = GPIOPORT(LEFT, 0), /* 0x000 */ enumerator in enum:gpio_port
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