Searched refs:PHY_REG (Results 1 - 4 of 4) sorted by relevance
/opensolaris-onvv-gate/usr/src/uts/common/io/e1000g/ |
H A D | e1000_ich8lan.h | 91 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ macro 93 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ 94 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ 95 #define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */ 96 #define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */ 104 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 105 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 106 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 107 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 122 #define HV_LED_CONFIG PHY_REG(76 [all...] |
H A D | e1000g_rx.c | 329 (void) e1000_read_phy_reg(hw, PHY_REG(770, 26), &phy_data); 332 (void) e1000_write_phy_reg(hw, PHY_REG(770, 26), phy_data);
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H A D | e1000_ich8lan.c | 946 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 953 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 1101 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 1106 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204); 1153 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 1157 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204); 2951 PHY_REG(BM_PORT_CTRL_PAGE, 27),
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H A D | e1000g_main.c | 5421 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5424 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5429 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5430 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5433 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5434 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5437 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5438 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5441 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5442 (void) e1000_write_phy_reg(hw, PHY_REG(76 [all...] |
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