Searched refs:mmATC_L2_CACHE_2M_DSM_CNTL (Results 1 - 2 of 2) sorted by relevance
| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_1_offset.h | 240 #define mmATC_L2_CACHE_2M_DSM_CNTL 0x0811 macro
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| /openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | gfx_v9_4.c | 703 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
705 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
774 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);
937 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
939 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
958 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);
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