/freebsd-10.0-release/tools/test/devrandom/ |
H A D | hammer.urandom | 11 open(ZERO, "/dev/zero") || die "Cannot open /dev/zero - $!\n"; 16 sysread(ZERO, $b, 20);
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/freebsd-10.0-release/lib/libthread_db/arch/mips/ |
H A D | libpthread_md.c | 44 memcpy(uc->uc_mcontext.mc_regs, &r->r_regs[ZERO], 54 memcpy(&r->r_regs[ZERO], uc->uc_mcontext.mc_regs,
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
H A D | R600ExpandSpecialInstrs.cpp | 81 AMDGPU::ZERO); // src1 95 AMDGPU::ZERO, 96 AMDGPU::ZERO);
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H A D | R600RegisterInfo.cpp | 33 Reserved.set(AMDGPU::ZERO);
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H A D | AMDILISelDAGToDAG.cpp | 239 ImmReg = AMDGPU::ZERO; 253 ImmReg = AMDGPU::ZERO; 271 // We can only use literal constants (e.g. AMDGPU::ZERO, 621 AMDGPU::ZERO, MVT::i32);
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/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 93 Opc = Mips::OR, ZeroReg = Mips::ZERO; 316 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 408 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; local 417 .addReg(TargetReg).addReg(ZERO); 419 .addReg(TargetReg).addReg(ZERO);
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H A D | MipsRegisterInfo.cpp | 106 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
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H A D | MipsSEFrameLowering.cpp | 255 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; local 347 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO); 371 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; local 383 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
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H A D | MipsSEISelDAGToDAG.cpp | 75 (MI.getOperand(1).getReg() == Mips::ZERO) && 78 ZeroReg = Mips::ZERO; 353 Mips::ZERO, MVT::i32);
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H A D | MipsCodeEmitter.cpp | 317 BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::SLL), Mips::ZERO) 318 .addReg(Mips::ZERO).addImm(0);
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H A D | MipsISelLowering.cpp | 891 unsigned LL, SC, AND, NOR, ZERO, BEQ; local 898 ZERO = Mips::ZERO; 906 ZERO = Mips::ZERO_64; 951 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 959 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1038 .addReg(Mips::ZERO).addImm(-4); 1044 .addReg(Mips::ZERO).addImm(MaskImm); 1047 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1077 .addReg(Mips::ZERO) 1131 unsigned LL, SC, ZERO, BNE, BEQ; local [all...] |
H A D | MipsDelaySlotFiller.cpp | 319 CallerSavedRegs.reset(Mips::ZERO); 336 AllocSet.set(Mips::ZERO);
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H A D | MipsSEISelLowering.cpp | 733 .addReg(Mips::ZERO).addImm(0); 739 .addReg(Mips::ZERO).addImm(1);
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/freebsd-10.0-release/sys/mips/include/ |
H A D | regnum.h | 46 * Location of the saved registers relative to ZERO. 50 #define ZERO 0 macro
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/freebsd-10.0-release/usr.bin/seq/ |
H A D | seq.c | 44 #define ZERO '0' macro 86 char pad = ZERO;
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/freebsd-10.0-release/contrib/binutils/opcodes/ |
H A D | mep-opc.c | 2079 { { MNEM, ' ', OP (RNC), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, 2085 { { MNEM, ' ', OP (RNS), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, 2091 { { MNEM, ' ', OP (RNL), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, 2097 { { MNEM, ' ', OP (RNC), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, 2103 { { MNEM, ' ', OP (RNS), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, 2109 { { MNEM, ' ', OP (RNL), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, 2115 { { MNEM, ' ', OP (RNUC), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, 2121 { { MNEM, ' ', OP (RNUS), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, 2127 { { MNEM, ' ', OP (CRN), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, 2133 { { MNEM, ' ', OP (CRN), ',', OP (ZERO), '(', O [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 427 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); 428 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); 515 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); 523 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); 599 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); 1195 // Zero register assumed, add a memory operand with ZERO as its base. 1197 : Mips::ZERO, member in class:Mips
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/freebsd-10.0-release/sys/contrib/dev/acpica/compiler/ |
H A D | asloperands.c | 859 Next->Asl.ParseOpcode = ZERO; 868 Next->Asl.ParseOpcode = ZERO;
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/freebsd-10.0-release/contrib/bmake/unit-tests/ |
H A D | test.exp | 290 LIST:[${ZERO}]="one two three four five six" 291 LIST:[${ZERO}x${ONE}]="one"
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/freebsd-10.0-release/contrib/gdb/gdb/ |
H A D | gdbarch.sh | 1099 /* Use default: NULL (ZERO). */ 1102 /* Use default: BFD_ENDIAN_UNKNOWN (NB: is not ZERO). */ 1105 /* Use default: NULL (ZERO). */ 1108 /* Use default: NULL (ZERO). */
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/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 818 // For some instructions, it is legal to fold ZERO into the RA register field. 829 // a ZERO into what is presented as the second argument. All we have here 869 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; 872 PPC::ZERO8 : PPC::ZERO;
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H A D | PPCRegisterInfo.cpp | 80 // when it checks for ZERO folding. 129 // The ZERO register is not really a register, but the representation of r0 131 Reserved.set(PPC::ZERO);
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H A D | PPCISelLowering.cpp | 1098 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, 1147 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, 1210 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, 5907 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; 6509 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
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/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 43 PPC::ZERO,
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/freebsd-10.0-release/sys/dev/aic7xxx/ |
H A D | aic7xxx.reg | 652 field ZERO 0x02
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