/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/ |
H A D | dcn316_clk_mgr.c | 354 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 355 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 357 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 358 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 360 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { 362 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; 365 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 368 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = 373 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 374 table->WatermarkRow[WM_DCFCLK][num_valid_set [all...] |
H A D | dcn316_smu.h | 56 WM_DCFCLK, enumerator in enum:__anon267
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/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/inc/ |
H A D | smu10_driver_if.h | 65 WM_DCFCLK, enumerator in enum:__anon649
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/ |
H A D | dcn31_clk_mgr.c | 432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 435 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 436 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 438 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { 440 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; 443 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 446 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = 451 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 452 table->WatermarkRow[WM_DCFCLK][num_valid_set [all...] |
H A D | dcn31_smu.h | 68 WM_DCFCLK, enumerator in enum:__anon250
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/ |
H A D | vg_clk_mgr.c | 397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 398 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 401 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 403 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { 405 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; 408 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 411 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = 416 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 417 table->WatermarkRow[WM_DCFCLK][num_valid_set [all...] |
H A D | dcn301_smu.h | 71 WM_DCFCLK, enumerator in enum:__anon91
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/ |
H A D | dcn314_clk_mgr.c | 447 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 448 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 451 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 453 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { 455 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; 458 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 461 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = 466 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 467 table->WatermarkRow[WM_DCFCLK][num_valid_set [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/ |
H A D | dcn315_clk_mgr.c | 392 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 393 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 395 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 396 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 398 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { 400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; 403 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 406 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = 411 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 412 table->WatermarkRow[WM_DCFCLK][num_valid_set [all...] |
H A D | dcn315_smu.h | 57 WM_DCFCLK, enumerator in enum:__anon263
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/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/ |
H A D | smu13_driver_if_v13_0_5.h | 67 WM_DCFCLK, enumerator in enum:__anon623
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H A D | smu12_driver_if.h | 67 WM_DCFCLK, enumerator in enum:__anon891
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H A D | smu13_driver_if_v13_0_4.h | 67 WM_DCFCLK, enumerator in enum:__anon612
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H A D | smu11_driver_if_vangogh.h | 66 WM_DCFCLK, enumerator in enum:__anon499
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H A D | smu13_driver_if_yellow_carp.h | 66 WM_DCFCLK, enumerator in enum:__anon716
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/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu13/ |
H A D | smu_v13_0_5_ppt.c | 416 table->WatermarkRow[WM_DCFCLK][i].MinClock = 418 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 420 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 422 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 425 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
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H A D | smu_v13_0_4_ppt.c | 672 table->WatermarkRow[WM_DCFCLK][i].MinClock = 674 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 676 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 678 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 681 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
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H A D | yellow_carp_ppt.c | 507 table->WatermarkRow[WM_DCFCLK][i].MinClock = 509 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 511 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 513 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 516 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
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/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu12/ |
H A D | renoir_ppt.c | 1057 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1059 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1061 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1063 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1066 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1068 table->WatermarkRow[WM_DCFCLK][i].WmType =
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/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu11/ |
H A D | vangogh_ppt.c | 1646 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1648 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1650 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1652 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1655 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
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/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ |
H A D | smu10_hwmgr.c | 1365 table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0;
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