/openbsd-current/gnu/usr.bin/gcc/gcc/testsuite/g++.dg/template/ |
H A D | unify1.C | 13 template< int Q1, int Q2 > 14 unit< I1 - Q1, I2 - Q2 > operator / ( const unit< Q1, Q2 >& rhs ) const { argument 15 return unit< I1 - Q1, I2 - Q2 >();
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H A D | non-type1.C | 12 template< int Q1, int Q2 > 13 unit< I1 + Q1, I2 + Q2 > operator * ( const unit< Q1, Q2 >& rhs ) const { argument 14 return unit< I1 + Q1, I2 + Q2 >(); 17 template< int Q1, int Q2 > 18 unit< I1 - Q1, I2 - Q2 > operator / ( const unit< Q1, Q2 >& rhs ) const { argument 19 return unit< I1 - Q1, I2 - Q2 >();
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/openbsd-current/gnu/llvm/llvm/lib/Support/ |
H A D | DivisionByConstantInfo.cpp | 35 APInt Q1, R1, Q2, R2; local 36 // initialize Q1 = 2P/abs(NC); R1 = rem(2P,abs(NC)) 37 APInt::udivrem(SignedMin, ANC, Q1, R1); 42 Q1 <<= 1; // update Q1 = 2P/abs(NC) 45 ++Q1; 57 } while (Q1.ult(Delta) || (Q1 == Delta && R1.isZero())); 90 APInt Q1, R1, Q2, R2; local 91 // initialize Q1 [all...] |
/openbsd-current/gnu/llvm/compiler-rt/lib/xray/ |
H A D | xray_trampoline_AArch64.S | 26 STP Q0, Q1, [SP, #-32]! 52 LDP Q0, Q1, [SP], #32 79 STP Q0, Q1, [SP, #-32]! 104 LDP Q0, Q1, [SP], #32 132 STP Q0, Q1, [SP, #-32]! 155 LDP Q0, Q1, [SP], #32
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/openbsd-current/lib/libm/src/ld80/ |
H A D | s_expm1l.c | 76 Q1 = 3.964866271411091674556850458227710004570E4L, variable 126 + Q1) * x
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/openbsd-current/lib/libm/src/ld128/ |
H A D | s_expm1l.c | 75 Q1 = -7.848989743695296475743081255027098295771E8L, variable 148 + Q6) * x + Q5) * x + Q4) * x + Q3) * x + Q2) * x + Q1) * x + Q0;
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H A D | s_log1pl.c | 91 Q1 = 2.626900195321832660448791748036714883242E5L, variable 239 + Q1) * x
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/openbsd-current/lib/libm/src/ |
H A D | s_expm1.c | 39 * R1(z) ~ 1.0 + Q1*z + Q2*z**2 + Q3*z**3 + Q4*z**4 + Q5*z**5 40 * where Q1 = -1.6666666666666567384E-2, 45 * (where z=r*r, and the values of Q1 to Q5 are listed below) 48 * | 1.0+Q1*z+...+Q5*z - R1(z) | <= 2 122 Q1 = -3.33333333333331316428e-02, /* BFA11111 111110F4 */ variable 183 r1 = one+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5))));
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H A D | s_expm1f.c | 28 Q1 = -3.3333335072e-02, /* 0xbd088889 */ variable 86 r1 = one+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5))));
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H A D | b_tgamma.c | 98 #define Q1 1.06258521948016171343454061571e+00 macro 271 q = Q0 +z*(Q1+z*(Q2+z*(Q3+z*(Q4+z*(Q5+z*(Q6+z*(Q7+z*Q8)))))));
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/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64CallingConvention.cpp | 35 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
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H A D | AArch64PBQPRegAlloc.cpp | 79 case AArch64::Q1:
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/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/ |
H A D | ARMCallingConv.cpp | 161 static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
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/openbsd-current/gnu/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.cpp | 89 Q0, Q1, Q2, Q3, 0
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H A D | HexagonISelLoweringHVX.cpp | 2591 SDValue Q1 = DAG.getSetCC(dl, PredTy, B, Zero, ISD::SETLT); 2593 SDValue X1 = getInstr(Hexagon::V6_vaddwq, dl, VecTy, {Q1, X0, A}, DAG); 2600 SDValue Q1 = DAG.getSetCC(dl, PredTy, B, Zero, ISD::SETLT); 2601 Hi = getInstr(Hexagon::V6_vsubwq, dl, VecTy, {Q1, Hi, A}, DAG); 2643 SDValue Q1 = DAG.getSetCC(dl, PredTy, B, Zero, ISD::SETLT); 2645 SDValue T1 = getInstr(Hexagon::V6_vaddwq, dl, VecTy, {Q1, T0, A}, DAG); 2724 // // "frac" is the fraction part represented as Q1.31. If it was
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/openbsd-current/gnu/usr.bin/perl/t/mro/ |
H A D | basic.t | 261 package Q1; 269 push @Q3::ISA, "Q1"; 272 push @Q3::ISA, "Q1";
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/openbsd-current/gnu/llvm/llvm/lib/Target/Sparc/Disassembler/ |
H A D | SparcDisassembler.cpp | 92 SP::Q1, SP::Q9, ~0U, ~0U,
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/openbsd-current/gnu/llvm/clang/lib/Sema/ |
H A D | SemaExprCXX.cpp | 6877 Qualifiers Q1, Q2; 6878 Composite1 = Context.getUnqualifiedArrayType(Composite1, Q1); 6885 Qualifiers Quals = Qualifiers::fromCVRUMask(Q1.getCVRUQualifiers() | 6890 if (Q1.getAddressSpace() == Q2.getAddressSpace()) { 6891 Quals.setAddressSpace(Q1.getAddressSpace()); 6893 bool MaybeQ1 = Q1.isAddressSpaceSupersetOf(Q2); 6894 bool MaybeQ2 = Q2.isAddressSpaceSupersetOf(Q1); 6898 if (isPtrSizeAddressSpace(Q1.getAddressSpace()) || 6904 Quals.setAddressSpace(MaybeQ1 ? Q1.getAddressSpace() 6911 if (Q1 [all...] |
/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCTargetDesc.cpp | 203 {codeview::RegisterId::ARM64_Q1, AArch64::Q1},
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H A D | AArch64InstPrinter.cpp | 1492 case AArch64::Q0: Reg = AArch64::Q1; break; 1493 case AArch64::Q1: Reg = AArch64::Q2; break;
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/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.cpp | 314 {codeview::RegisterId::ARM_NQ1, ARM::Q1},
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/openbsd-current/gnu/llvm/llvm/lib/Target/VE/Disassembler/ |
H A D | VEDisassembler.cpp | 93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
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/openbsd-current/gnu/llvm/llvm/lib/Target/Hexagon/Disassembler/ |
H A D | HexagonDisassembler.cpp | 661 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
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/openbsd-current/gnu/llvm/llvm/include/llvm/Demangle/ |
H A D | ItaniumDemangle.h | 401 inline Qualifiers operator|=(Qualifiers &Q1, Qualifiers Q2) { 402 return Q1 = static_cast<Qualifiers>(Q1 | Q2);
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/openbsd-current/gnu/llvm/libcxxabi/src/demangle/ |
H A D | ItaniumDemangle.h | 401 inline Qualifiers operator|=(Qualifiers &Q1, Qualifiers Q2) { 402 return Q1 = static_cast<Qualifiers>(Q1 | Q2);
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