Searched refs:IH_CNTL (Results 1 - 11 of 11) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dsi_ih.c37 u32 ih_cntl = RREG32(IH_CNTL);
42 WREG32(IH_CNTL, ih_cntl);
50 u32 ih_cntl = RREG32(IH_CNTL);
55 WREG32(IH_CNTL, ih_cntl);
93 WREG32(IH_CNTL, ih_cntl);
H A Diceland_ih.c65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
147 /* Default settings for IH_CNTL (disabled at first) */
149 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
152 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
H A Dcz_ih.c65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
147 /* Default settings for IH_CNTL (disabled at first) */
149 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
152 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
H A Dsid.h669 #define IH_CNTL 0xF86 macro
/openbsd-current/sys/dev/pci/drm/radeon/
H A Dr600.c3592 u32 ih_cntl = RREG32(IH_CNTL);
3597 WREG32(IH_CNTL, ih_cntl);
3605 u32 ih_cntl = RREG32(IH_CNTL);
3610 WREG32(IH_CNTL, ih_cntl);
3727 /* Default settings for IH_CNTL (disabled at first) */
3732 WREG32(IH_CNTL, ih_cntl);
H A Dsi.c5921 u32 ih_cntl = RREG32(IH_CNTL);
5926 WREG32(IH_CNTL, ih_cntl);
5934 u32 ih_cntl = RREG32(IH_CNTL);
5939 WREG32(IH_CNTL, ih_cntl);
6030 /* Default settings for IH_CNTL (disabled at first) */
6035 WREG32(IH_CNTL, ih_cntl);
H A Dcikd.h816 #define IH_CNTL 0x3e18 macro
H A Dsid.h666 #define IH_CNTL 0x3e18 macro
H A Dcik.c6814 u32 ih_cntl = RREG32(IH_CNTL);
6819 WREG32(IH_CNTL, ih_cntl);
6834 u32 ih_cntl = RREG32(IH_CNTL);
6839 WREG32(IH_CNTL, ih_cntl);
6988 /* Default settings for IH_CNTL (disabled at first) */
6993 WREG32(IH_CNTL, ih_cntl);
H A Devergreend.h1235 #define IH_CNTL 0x3e18 macro
H A Dr600d.h674 #define IH_CNTL 0x3e18 macro

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