Searched refs:CondBr (Results 1 - 6 of 6) sorted by relevance
/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64RedundantCopyElimination.cpp | 92 bool knownRegValInBlock(MachineInstr &CondBr, MachineBasicBlock *MBB, 113 /// is the target of a conditional branch \p CondBr with an equality comparison. 124 MachineInstr &CondBr, MachineBasicBlock *MBB, 126 unsigned Opc = CondBr.getOpcode(); 131 MBB == CondBr.getOperand(1).getMBB()) || 133 MBB != CondBr.getOperand(1).getMBB())) { 134 FirstUse = CondBr; 135 KnownRegs.push_back(RegImm(CondBr.getOperand(0).getReg(), 0)); 144 AArch64CC::CondCode CC = (AArch64CC::CondCode)CondBr.getOperand(0).getImm(); 148 MachineBasicBlock *BrTarget = CondBr 123 knownRegValInBlock( MachineInstr &CondBr, MachineBasicBlock *MBB, SmallVectorImpl<RegImm> &KnownRegs, MachineBasicBlock::iterator &FirstUse) argument [all...] |
/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/ |
H A D | RISCVRedundantCopyElimination.cpp | 143 MachineBasicBlock::iterator CondBr = PredMBB->getFirstTerminator(); 144 assert((CondBr->getOpcode() == RISCV::BEQ || 145 CondBr->getOpcode() == RISCV::BNE) && 147 assert(CondBr->getOperand(0).getReg() == TargetReg && "Unexpected register"); 151 CondBr->clearRegisterKills(TargetReg, TRI); 157 // Clear any kills of TargetReg between CondBr and the last removed COPY.
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/openbsd-current/gnu/llvm/llvm/lib/Transforms/Scalar/ |
H A D | JumpThreading.cpp | 198 // [Branch CondBr] 219 BranchInst *CondBr = dyn_cast<BranchInst>(BB->getTerminator()); local 220 if (!CondBr) 224 if (!extractBranchWeights(*CondBr, TrueWeight, FalseWeight)) 2173 BranchInst *CondBr = dyn_cast<BranchInst>(BB->getTerminator()); local 2174 if (!CondBr) 2247 BasicBlock *SuccBB = CondBr->getSuccessor(PredPredBB == ZeroPred); 2301 BranchInst *CondBr = cast<BranchInst>(BB->getTerminator()); local 2342 {{DominatorTree::Insert, NewBB, CondBr->getSuccessor(0)}, 2343 {DominatorTree::Insert, NewBB, CondBr 2849 BranchInst *CondBr = dyn_cast<BranchInst>(BB->getTerminator()); local [all...] |
/openbsd-current/gnu/llvm/llvm/lib/Transforms/Vectorize/ |
H A D | VPlanRecipes.cpp | 313 BranchInst *CondBr = local 317 CondBr->setSuccessor(1, State.CFG.VPBB2IRBB[Header]); 319 CondBr->setSuccessor(0, nullptr); 341 BranchInst *CondBr = Builder.CreateCondBr(Cond, Builder.GetInsertBlock(), local 343 CondBr->setSuccessor(0, nullptr); 961 auto *CondBr = BranchInst::Create(State.CFG.PrevBB, nullptr, ConditionBit); local 962 CondBr->setSuccessor(0, nullptr); 963 ReplaceInstWithInst(CurrentTerminator, CondBr);
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/openbsd-current/gnu/llvm/llvm/lib/Target/X86/ |
H A D | X86SpeculativeLoadHardening.cpp | 721 for (auto *CondBr : CondBrs) 722 ++SuccCounts[CondBr->getOperand(0).getMBB()]; 787 for (auto *CondBr : CondBrs) { 788 MachineBasicBlock &Succ = *CondBr->getOperand(0).getMBB(); 791 X86::CondCode Cond = X86::getCondFromBranch(*CondBr); 795 BuildCheckingBlockForSuccAndConds(MBB, Succ, SuccCount, CondBr, UncondBr,
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/openbsd-current/gnu/llvm/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 2802 MachineInstr *CondBr = local 2807 preserveCondRegFlags(CondBr->getOperand(1), Cond[1]); 2808 fixImplicitOperands(*CondBr); 2817 MachineInstr *CondBr = local 2820 fixImplicitOperands(*CondBr); 2824 MachineOperand &CondReg = CondBr->getOperand(1);
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