/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sh/kernel/cpu/sh4a/ |
H A D | clock-sh7722.c | 91 static struct clk pll_clk = { variable in typeref:struct:clk 100 &pll_clk, 118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 147 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 185 CLKDEV_CON_ID("pll_clk", &pll_clk), 261 pll_clk.parent = &dll_clk; 263 pll_clk.parent = &extal_clk;
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H A D | clock-sh7366.c | 91 static struct clk pll_clk = { variable in typeref:struct:clk 100 &pll_clk, 121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 137 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 202 CLKDEV_CON_ID("pll_clk", &pll_clk), 276 pll_clk.parent = &dll_clk; 278 pll_clk.parent = &extal_clk;
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H A D | clock-sh7785.c | 43 static struct clk pll_clk = { variable in typeref:struct:clk 51 &pll_clk, 70 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) 124 CLKDEV_CON_ID("pll_clk", &pll_clk),
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H A D | clock-sh7786.c | 45 static struct clk pll_clk = { variable in typeref:struct:clk 53 &pll_clk, 71 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) 133 CLKDEV_CON_ID("pll_clk", &pll_clk),
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H A D | clock-sh7343.c | 88 static struct clk pll_clk = { variable in typeref:struct:clk 97 &pll_clk, 118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 134 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 204 CLKDEV_CON_ID("pll_clk", &pll_clk), 287 pll_clk.parent = &dll_clk; 289 pll_clk.parent = &extal_clk;
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H A D | clock-sh7723.c | 92 static struct clk pll_clk = { variable in typeref:struct:clk 101 &pll_clk, 121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 147 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 210 CLKDEV_CON_ID("pll_clk", &pll_clk), 337 pll_clk.parent = &dll_clk; 339 pll_clk.parent = &extal_clk;
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H A D | clock-sh7724.c | 94 static struct clk pll_clk = { variable in typeref:struct:clk 111 .parent = &pll_clk, 118 &pll_clk, 147 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 231 CLKDEV_CON_ID("pll_clk", &pll_clk), 363 pll_clk.parent = &fll_clk; 365 pll_clk.parent = &extal_clk;
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/plat-stmp3xxx/ |
H A D | clock.c | 39 static struct clk pll_clk; variable in typeref:struct:clk 321 u32 f = (pll_clk.rate*18/c + rate/2) / rate; 326 s1 = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - rate; 327 s2 = pll_clk.rate*18/c/f - rate; 339 int d = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - 370 clk_set_parent(clk, &pll_clk); 400 (pll_clk.rate*18 / clkctrl_cpu + rate/2) / rate; 403 if (pll_clk.rate*18 / clkctrl_frac / clkctrl_cpu/10 == 406 } while (pll_clk.rate / 2 >= clkctrl_cpu++ * rate); 407 if (pll_clk 664 static struct clk pll_clk = { variable in typeref:struct:clk [all...] |
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-mxc91231/ |
H A D | clock.c | 125 static struct clk *pll_clk(u8 sel) function 289 return clk_get_rate(pll_clk(sel)) / 314 return pll_clk(sel);
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