Searched refs:UART_CR (Results 1 - 6 of 6) sorted by relevance
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-aaec2000/include/mach/ |
H A D | uncompress.h | 23 if (UART(UART_CR) & UART_CR_EN) break; 25 if (UART(UART_CR) & UART_CR_EN) break; 27 if (UART(UART_CR) & UART_CR_EN) break;
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H A D | aaec2000.h | 79 #define UART_CR 0x0c macro 96 /* UART_CR Bitmask */
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-netx/include/mach/ |
H A D | uncompress.h | 36 #define UART_CR 0x14 macro 47 if (REG(UART1_BASE + UART_CR) & CR_UART_EN) 49 else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) 62 if (REG(UART1_BASE + UART_CR) & CR_UART_EN) 64 else if (REG(UART2_BASE + UART_CR) & CR_UART_EN)
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/serial/ |
H A D | netx-serial.c | 51 UART_CR = 0x14, enumerator in enum:uart_regs 123 val = readl(port->membase + UART_CR); 124 writel(val & ~CR_TIE, port->membase + UART_CR); 130 val = readl(port->membase + UART_CR); 131 writel(val & ~CR_RIE, port->membase + UART_CR); 137 val = readl(port->membase + UART_CR); 138 writel(val | CR_MSIE, port->membase + UART_CR); 175 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR); 324 port->membase + UART_CR); [all...] |
H A D | msm_serial.c | 88 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 157 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 204 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); 214 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR); 216 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR); 297 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); 298 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); 299 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 300 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR); 301 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); [all...] |
H A D | msm_serial.h | 58 #define UART_CR 0x0010 macro
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