Searched refs:MIXART_MEM (Results 1 - 4 of 4) sorted by relevance
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/sound/pci/mixart/ |
H A D | mixart_core.c | 53 tailptr = readl_be(MIXART_MEM(mgr, MSG_OUTBOUND_POST_TAIL)); 54 headptr = readl_be(MIXART_MEM(mgr, MSG_OUTBOUND_POST_HEAD)); 64 *msg_frame = readl_be(MIXART_MEM(mgr, tailptr)); 70 writel_be(tailptr, MIXART_MEM(mgr, MSG_OUTBOUND_POST_TAIL)); 90 size = readl_be(MIXART_MEM(mgr, msg_frame_address)); /* size of descriptor + response */ 91 resp->message_id = readl_be(MIXART_MEM(mgr, msg_frame_address + 4)); /* dwMessageID */ 92 resp->uid.object_id = readl_be(MIXART_MEM(mgr, msg_frame_address + 8)); /* uidDest */ 93 resp->uid.desc = readl_be(MIXART_MEM(mgr, msg_frame_address + 12)); /* */ 102 memcpy_fromio(resp->data, MIXART_MEM(mgr, msg_frame_address + MSG_HEADER_SIZE ), size); 116 headptr = readl_be(MIXART_MEM(mg [all...] |
H A D | mixart_hwdep.c | 56 read = readl_be( MIXART_MEM( mgr, offset )); 121 memcpy_toio( MIXART_MEM( mgr, be32_to_cpu(elf_programheader.p_vaddr)), 342 status_xilinx = readl_be( MIXART_MEM( mgr,MIXART_PSEUDOREG_MXLX_STATUS_OFFSET )); 344 status_elf = readl_be( MIXART_MEM( mgr,MIXART_PSEUDOREG_ELF_STATUS_OFFSET )); 346 status_daught = readl_be( MIXART_MEM( mgr,MIXART_PSEUDOREG_DXLX_STATUS_OFFSET )); 376 writel_be( 1, MIXART_MEM( mgr, MIXART_PSEUDOREG_MXLX_STATUS_OFFSET )); 379 writel_be( MIXART_MOTHERBOARD_XLX_BASE_ADDRESS, MIXART_MEM( mgr,MIXART_PSEUDOREG_MXLX_BASE_ADDR_OFFSET )); 381 writel_be( dsp->size, MIXART_MEM( mgr, MIXART_PSEUDOREG_MXLX_SIZE_OFFSET )); 384 memcpy_toio( MIXART_MEM( mgr, MIXART_MOTHERBOARD_XLX_BASE_ADDRESS), dsp->data, dsp->size); 387 writel_be( 2, MIXART_MEM( mg [all...] |
H A D | mixart_hwdep.h | 34 #define MIXART_MEM(mgr,x) ((mgr)->mem[0].virt + (x)) macro
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H A D | mixart.c | 1104 if (copy_to_user_fromio(buf, MIXART_MEM(mgr, pos), count)) 1156 ref = readl_be( MIXART_MEM( chip->mgr, MIXART_PSEUDOREG_PERF_SYSTEM_LOAD_OFFSET)); 1159 u32 mailbox = 100 * readl_be( MIXART_MEM( chip->mgr, MIXART_PSEUDOREG_PERF_MAILBX_LOAD_OFFSET)) / ref; 1160 u32 streaming = 100 * readl_be( MIXART_MEM( chip->mgr, MIXART_PSEUDOREG_PERF_STREAM_LOAD_OFFSET)) / ref; 1161 u32 interr = 100 * readl_be( MIXART_MEM( chip->mgr, MIXART_PSEUDOREG_PERF_INTERR_LOAD_OFFSET)) / ref;
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