Searched refs:refcyc_per_line_delivery_pre_l (Results 1 - 12 of 12) sorted by relevance
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
H A D | amdgpu_display_rq_dlg_calc_20.c | 887 double refcyc_per_line_delivery_pre_l; local 1188 refcyc_per_line_delivery_pre_l = 0.; 1213 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib, 1241 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", 1243 refcyc_per_line_delivery_pre_l); 1499 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1503 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
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H A D | amdgpu_display_rq_dlg_calc_20v2.c | 887 double refcyc_per_line_delivery_pre_l; local 1189 refcyc_per_line_delivery_pre_l = 0.; 1214 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib, 1242 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", 1244 refcyc_per_line_delivery_pre_l); 1500 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1504 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
H A D | amdgpu_display_rq_dlg_calc_21.c | 933 double refcyc_per_line_delivery_pre_l; local 1240 refcyc_per_line_delivery_pre_l = 0.; 1266 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery( 1296 "DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", 1298 refcyc_per_line_delivery_pre_l); 1599 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor( 1600 refcyc_per_line_delivery_pre_l, 1); 1603 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
H A D | amdgpu_dcn21_hubp.c | 511 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 566 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 568 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
H A D | amdgpu_display_rq_dlg_helpers.c | 294 "DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0x%0x\n", 295 dlg_regs.refcyc_per_line_delivery_pre_l);
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H A D | display_mode_structs.h | 450 unsigned int refcyc_per_line_delivery_pre_l; member in struct:_vcs_dpi_display_dlg_regs_st
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H A D | amdgpu_dml1_display_rq_dlg_calc.c | 1101 double refcyc_per_line_delivery_pre_l; local 1627 refcyc_per_line_delivery_pre_l = 0.; 1649 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery( 1672 "DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f", 1674 refcyc_per_line_delivery_pre_l); 1680 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor( 1681 refcyc_per_line_delivery_pre_l, 1686 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
H A D | amdgpu_dcn20_hubp.c | 279 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 1119 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 1413 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 1468 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 1470 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
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H A D | amdgpu_dcn20_hwseq.c | 1274 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1292 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
H A D | amdgpu_dcn10_hw_sequencer_debug.c | 277 dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
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H A D | amdgpu_dcn10_hubp.c | 707 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 927 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
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H A D | amdgpu_dcn10_hw_sequencer.c | 244 dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l, 1762 "refcyc_per_line_delivery_pre_l: %d, \n" 1776 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
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