/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 517 unsigned NewOpc; local 520 case X86::MULX32Hrr: NewOpc = X86::MULX32rr; break; 521 case X86::MULX32Hrm: NewOpc = X86::MULX32rm; break; 522 case X86::MULX64Hrr: NewOpc = X86::MULX64rr; break; 523 case X86::MULX64Hrm: NewOpc = X86::MULX64rm; break; 525 OutMI.setOpcode(NewOpc); 549 unsigned NewOpc; local 552 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; 553 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; 554 case X86::VMOVAPDYrr: NewOpc 574 unsigned NewOpc; local 617 unsigned NewOpc; local 689 unsigned NewOpc; local 853 unsigned NewOpc; local 878 unsigned NewOpc; local [all...] |
H A D | X86EvexToVex.cpp | 149 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc, argument 151 (void)NewOpc; 158 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) && 174 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr || 175 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) && 260 unsigned NewOpc = I->VexOpcode; local 268 if (!performCustomAdjustments(MI, NewOpc, S [all...] |
H A D | X86FixupLEAs.cpp | 598 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); local 604 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) 610 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) 636 unsigned NewOpc = local 638 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) 642 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); local 643 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) 670 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); local 671 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg) 693 unsigned NewOpc local [all...] |
H A D | X86ISelDAGToDAG.cpp | 992 unsigned NewOpc; local 995 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break; 996 case ISD::STRICT_FP_ROUND: NewOpc = X86ISD::STRICT_VFPROUND; break; 997 case ISD::STRICT_FP_TO_SINT: NewOpc = X86ISD::STRICT_CVTTP2SI; break; 998 case ISD::FP_TO_SINT: NewOpc = X86ISD::CVTTP2SI; break; 999 case ISD::STRICT_FP_TO_UINT: NewOpc = X86ISD::STRICT_CVTTP2UI; break; 1000 case ISD::FP_TO_UINT: NewOpc = X86ISD::CVTTP2UI; break; 1005 CurDAG->getNode(NewOpc, SDLoc(N), {N->getValueType(0), MVT::Other}, 1009 CurDAG->getNode(NewOpc, SDLoc(N), N->getValueType(0), 1025 unsigned NewOpc; local 1047 unsigned NewOpc; local 1437 unsigned NewOpc; local 1480 unsigned NewOpc; local 3199 unsigned NewOpc = SelectOpcode(X86::NEG64m, X86::NEG32m, X86::NEG16m, local 3214 unsigned NewOpc = local 3304 unsigned NewOpc = SelectRegOpcode(Opc); local 3710 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; local 3726 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; local 3750 unsigned NewOpc = NVT == MVT::i64 ? X86::SHR64ri : X86::SHR32ri; local [all...] |
H A D | X86InstructionSelector.cpp | 530 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlign()); local 531 if (NewOpc == Opc) 537 I.setDesc(TII.get(NewOpc)); 572 unsigned NewOpc = getLeaOP(Ty, STI); local 573 I.setDesc(TII.get(NewOpc)); 623 unsigned NewOpc = getLeaOP(Ty, STI); local 625 I.setDesc(TII.get(NewOpc)); 655 unsigned NewOpc; local 658 NewOpc = X86::MOV8ri; 661 NewOpc [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonRDFOpt.cpp | 224 unsigned OpNum, NewOpc; local 227 NewOpc = Hexagon::L2_loadri_io; 231 NewOpc = Hexagon::L2_loadrd_io; 235 NewOpc = Hexagon::V6_vL32b_ai; 239 NewOpc = Hexagon::S2_storeri_io; 243 NewOpc = Hexagon::S2_storerd_io; 247 NewOpc = Hexagon::V6_vS32b_ai; 273 MI.setDesc(HII.get(NewOpc));
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H A D | HexagonGenPredicate.cpp | 389 unsigned NewOpc = getPredForm(Opc); local 391 if (NewOpc == 0) { 394 NewOpc = Hexagon::C2_not; 397 NewOpc = TargetOpcode::COPY; 424 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R);
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H A D | HexagonCopyToCombine.cpp | 874 unsigned NewOpc; local 876 NewOpc = Hexagon::A2_combinew; 879 NewOpc = Hexagon::V6_vcombine; 883 BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg)
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64PostSelectOptimize.cpp | 143 unsigned NewOpc = getNonFlagSettingVariant(II.getOpcode()); local 147 if (InsideCmpRange && NewOpc) { 151 II.setDesc(TII->get(NewOpc));
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 3610 unsigned NewOpc; local 3613 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; 3614 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; 3615 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; 3616 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; 3617 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; 3618 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; 3619 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; 3620 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; 3621 case X86::VMOVDQUYrr: NewOpc 3639 unsigned NewOpc; local 3660 unsigned NewOpc; local 3713 unsigned NewOpc; local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 595 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, argument 617 switch (NewOpc) { 619 NewOpc = Mips::BEQZC; 622 NewOpc = Mips::BNEZC; 625 NewOpc = Mips::BGEZC; 628 NewOpc = Mips::BLTZC; 631 NewOpc = Mips::BEQZC64; 634 NewOpc = Mips::BNEZC64; 639 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); 645 if (NewOpc [all...] |
H A D | MipsSEInstrInfo.h | 98 unsigned NewOpc) const;
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H A D | MipsInstrInfo.h | 152 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
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H A D | MipsSEISelLowering.h | 78 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 1346 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); local 1347 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) 1498 unsigned NewOpc; local 1500 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add); 1502 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); 1508 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add); 1510 (!isAM5 && !isLegalAddressImm(NewOpc, Offset, TII))) { 1511 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); 1512 if (isAM5 || !isLegalAddressImm(NewOpc, Offset, TII)) 1528 auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) [all...] |
H A D | Thumb2InstrInfo.cpp | 576 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 578 MI.setDesc(TII.get(NewOpc)); 609 unsigned NewOpc = Opcode; 619 NewOpc = immediateOffsetOpcode(Opcode); 631 NewOpc = negativeOffsetOpcode(Opcode); 636 NewOpc = positiveOffsetOpcode(Opcode); 696 if (NewOpc != Opcode) 697 MI.setDesc(TII.get(NewOpc)); 741 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
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H A D | ARMConstantIslandPass.cpp | 1787 unsigned NewOpc = 0; local 1794 NewOpc = ARM::tLEApcrel; 1801 NewOpc = ARM::tLDRpci; 1808 if (!NewOpc) 1821 U.MI->setDesc(TII->get(NewOpc)); 1838 unsigned NewOpc = 0; 1844 NewOpc = ARM::tB; 1849 NewOpc = ARM::tBcc; 1854 if (NewOpc) { 1859 Br.MI->setDesc(TII->get(NewOpc)); 1872 unsigned NewOpc = 0; member in struct:ImmCompare [all...] |
H A D | ARMInstructionSelector.cpp | 899 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize); local 900 if (NewOpc == I.getOpcode()) 902 I.setDesc(TII.get(NewOpc)); 1095 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); local 1096 if (NewOpc == G_LOAD || NewOpc == G_STORE) 1099 if (ValSize == 1 && NewOpc == Opcodes.STORE8) { 1117 I.setDesc(TII.get(NewOpc)); 1119 if (NewOpc == ARM::LDRH || NewOpc [all...] |
H A D | ThumbRegisterInfo.cpp | 404 unsigned NewOpc = convertToNonSPOpcode(Opcode); 405 if (NewOpc != Opcode && FrameReg != ARM::SP) 406 MI.setDesc(TII.get(NewOpc));
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
H A D | LanaiMemAluCombiner.cpp | 252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); local 255 assert(NewOpc != 0 && "Unknown merged node opcode"); 259 BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc));
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 292 unsigned NewOpc = getTransformOpcode(OldOpc); local 293 assert(OldOpc != NewOpc && "transform an instruction to itself?!"); 362 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst)
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H A D | AArch64CondBrTuning.cpp | 100 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode(), Is64Bit); local 106 TII->get(NewOpc), NewDestReg);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 235 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8; local 245 assert(MI.getOpcode() != NewOpc); 246 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags());
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H A D | SIInstrInfo.cpp | 966 int NewOpc; local 969 NewOpc = AMDGPU::getCommuteRev(Opcode); 970 if (NewOpc != -1) 972 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; 975 NewOpc = AMDGPU::getCommuteOrig(Opcode); 976 if (NewOpc != -1) 978 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; 2726 unsigned NewOpc local 2794 unsigned NewOpc = local 2879 unsigned NewOpc = local 3101 unsigned NewOpc = local 3114 unsigned NewOpc = IsFMA local 3144 unsigned NewOpc = IsFMA ? (IsF16 ? AMDGPU::V_FMA_F16_e64 local 4991 int NewOpc = AMDGPU::getGlobalVaddrOp(Opc); local 6082 unsigned NewOpc = Opc == AMDGPU::S_ADD_I32 ? local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 684 unsigned NewOpc = Node->getOpcode(); local 687 if (NewOpc == ISD::FP_TO_UINT && 689 NewOpc = ISD::FP_TO_SINT; 691 if (NewOpc == ISD::STRICT_FP_TO_UINT && 693 NewOpc = ISD::STRICT_FP_TO_SINT; 698 Promoted = DAG.getNode(NewOpc, dl, {NVT, MVT::Other}, 702 Promoted = DAG.getNode(NewOpc, dl, NVT, Node->getOperand(0)); 709 NewOpc = ISD::AssertZext; 711 NewOpc = ISD::AssertSext; 713 Promoted = DAG.getNode(NewOpc, d [all...] |