Searched refs:Cycle (Results 1 - 23 of 23) sorted by relevance

/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h18 // A schedule is, for every instruction in a block, a Cycle and a Stage. Note
22 // The Cycle of an instruction defines a partial order of the instructions in
24 // of any instruction in the same cycle. Cycle information is assumed to have
77 /// maintain a Cycle and Stage.
83 /// The instructions to be generated, in total order. Cycle provides a partial
89 DenseMap<MachineInstr *, int> Cycle; member in class:llvm::ModuloSchedule
101 /// \arg Cycle Cycle index for all instructions in ScheduledInstrs. Cycle does
103 /// Cycle
105 ModuloSchedule(MachineFunction &MF, MachineLoop *Loop, std::vector<MachineInstr *> ScheduledInstrs, DenseMap<MachineInstr *, int> Cycle, DenseMap<MachineInstr *, int> Stage) argument
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H A DMachineTraceMetrics.h77 unsigned Cycle = 0; member in struct:llvm::LiveRegUnit
H A DScheduleDAG.h299 unsigned TopReadyCycle = 0; ///< Cycle relative to start when node is ready.
300 unsigned BotReadyCycle = 0; ///< Cycle relative to end when node is ready.
546 void setCurCycle(unsigned Cycle) { argument
547 CurCycle = Cycle;
/netbsd-current/external/gpl3/gdb.old/dist/ld/testsuite/ld-ctf/
H A Dcycle-2.A.d7 #name: Cycle 2.A
H A Dcycle-2.B.d7 #name: Cycle 2.B
H A Dcycle-2.C.d7 #name: Cycle 2.C
H A Dcycle-1.d8 #name: Cycle 1
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineTraceMetrics.cpp580 // need to erase the Cycle entries. They will be overwritten when we
792 unsigned Cycle = 0;
805 Cycle = std::max(Cycle, DepCycle);
809 MICycles.Depth = Cycle;
813 TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Height);
814 LLVM_DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI);
816 LLVM_DEBUG(dbgs() << Cycle << '\t' << UseMI);
919 unsigned DepHeight = I->Cycle;
938 if (LRU.Cycle <
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H A DModuloSchedule.cpp2096 // "Stage=%d Cycle=%d".
2139 static void parseSymbolString(StringRef S, int &Cycle, int &Stage) { argument
2153 CycleTokenAndValue.second.drop_front().getAsInteger(10, Cycle);
2155 dbgs() << " Stage=" << Stage << ", Cycle=" << Cycle << "\n"; local
2163 DenseMap<MachineInstr *, int> Cycle, Stage; local
2171 parseSymbolString(Sym->getName(), Cycle[&MI], Stage[&MI]);
2175 ModuloSchedule MS(MF, &L, std::move(Instrs), std::move(Cycle),
H A DMachinePipeliner.cpp614 for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle();
615 ++Cycle) {
616 for (SUnit *SU : Schedule.getInstructions(Cycle)) {
618 Cycles[SU->getInstr()] = Cycle;
2914 for (int Cycle = getFirstCycle(), E = getFinalCycle(); Cycle <= E; ++Cycle) {
2915 std::deque<SUnit *> &cycleInstrs = ScheduledInstrs[Cycle];
H A DIfConversion.cpp287 unsigned Cycle, unsigned Extra,
289 return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra,
286 MeetIfcvtSizeLimit(MachineBasicBlock &BB, unsigned Cycle, unsigned Extra, BranchProbability Prediction) const argument
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/MCA/
H A DInstruction.h299 bool contains(unsigned Cycle) const { return Cycle >= Begin && Cycle < End; }
/netbsd-current/external/apache2/llvm/dist/clang/include/clang/AST/
H A DASTImporter.h197 using Cycle = llvm::iterator_range<VecTy::const_reverse_iterator>;
198 Cycle getCycleAtBack() const {
200 return Cycle(Nodes.rbegin(),
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h62 void notifyExecuted(unsigned Cycle);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonLoopIdiomRecognition.cpp598 bool findCycle(Value *Out, Value *In, ValueSeq &Cycle);
599 void classifyCycle(Instruction *DivI, ValueSeq &Cycle, ValueSeq &Early,
1134 ValueSeq &Cycle) {
1155 if (Cycle.count(I))
1157 Cycle.insert(I);
1158 if (findCycle(I, In, Cycle))
1160 Cycle.remove(I);
1162 return !Cycle.empty();
1166 ValueSeq &Cycle, ValueSeq &Early, ValueSeq &Late) {
1172 unsigned I, N = Cycle
1133 findCycle(Value *Out, Value *In, ValueSeq &Cycle) argument
1165 classifyCycle(Instruction *DivI, ValueSeq &Cycle, ValueSeq &Early, ValueSeq &Late) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp439 unsigned Cycle = getTransSwizzle(TransSwz, i);
444 if (Vector[Src.second][Cycle] < 0)
445 Vector[Src.second][Cycle] = Src.first;
446 if (Vector[Src.second][Cycle] != Src.first)
500 unsigned Cycle = getTransSwizzle(TransSwz, i);
503 if (ConstCount > 0 && Cycle == 0)
505 if (ConstCount > 1 && Cycle == 1)
/netbsd-current/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp36 void WriteRef::notifyExecuted(unsigned Cycle) { argument
38 WriteBackCycle = Cycle;
/netbsd-current/sys/external/bsd/acpica/dist/tools/examples/
H A Dextables.c336 [0001] Duty Cycle Offset : 00
337 [0001] Duty Cycle Width : 00
/netbsd-current/external/gpl3/gcc.old/dist/libphobos/src/std/range/
H A Dpackage.d3439 infinite (fact that would make $(D Cycle) the identity application),
3440 $(D Cycle) detects that and aliases itself to the range type
3442 If the original range has random access, $(D Cycle) offers
3444 $(D index). $(D Cycle) works with static arrays in addition to ranges,
3451 struct Cycle(R)
3527 @property Cycle save()
3529 //No need to call _original.save, because Cycle never actually modifies _original
3530 return Cycle(_original, _index);
3606 @property Cycle save()
3608 //No need to call _original.save, because Cycle neve
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/netbsd-current/external/gpl3/gcc/dist/libphobos/src/std/range/
H A Dpackage.d3871 infinite (fact that would make `Cycle` the identity application),
3872 `Cycle` detects that and aliases itself to the range type
3874 If the original range has random access, `Cycle` offers
3876 `index`. `Cycle` works with static arrays in addition to ranges,
3883 struct Cycle(R)
3959 @property Cycle save()
3961 //No need to call _original.save, because Cycle never actually modifies _original
3962 return Cycle(_original, _index);
4044 @property Cycle save()
4046 //No need to call _original.save, because Cycle neve
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/netbsd-current/external/gpl3/gdb/dist/readline/readline/doc/
H A Dtexi2dvi1144 verbose "Cycle $suite_cycle for $command_line_filename"
/netbsd-current/distrib/syspkg/mk/
H A Dbsd.syspkg.mk408 ${SHCOMMENT} Cycle through some FTP server here ;\
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp156 int Cycle = ItinData->getOperandCycle(DefClass, i); local
157 if (Cycle < 0)
160 Latency = std::max(Latency, (unsigned) Cycle);

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