Searched refs:c7 (Results 1 - 25 of 64) sorted by relevance

123

/linux-master/arch/arm/mm/
H A Dcache-v6.S43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
143 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
150 mcr p15, 0, r0, c7, c1
[all...]
H A Dcache-fa.S45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
68 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
69 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
70 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
71 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
92 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
93 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
98 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
99 mcrne p15, 0, ip, c7, c1
[all...]
H A Dproc-mohawk.S65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
66 mcr p15, 0, ip, c7, c10, 4 @ drain WB
67 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
84 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
96 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
117 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
120 mcrne p15, 0, ip, c7, c1
[all...]
H A Dproc-arm920.S80 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
81 mcr p15, 0, ip, c7, c10, 4 @ drain WB
83 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
98 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
111 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
161 1: mcr p15, 0, r0, c7, c1
[all...]
H A Dproc-fa526.S61 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
62 mcr p15, 0, ip, c7, c10, 4 @ drain WB
64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
86 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
90 mcr p15, 0, r0, c7, c10, 4 @ drain WB
108 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
110 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
112 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
113 mcr p15, 0, ip, c7, c
[all...]
H A Dproc-arm946.S63 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
64 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
65 mcr p15, 0, ip, c7, c10, 4 @ drain WB
79 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
90 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
113 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
120 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
121 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
144 mcr p15, 0, r0, c7, c
[all...]
H A Dtlb-fa.S41 mcr p15, 0, r3, c7, c10, 4 @ drain WB
44 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
48 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
55 mcr p15, 0, r3, c7, c10, 4 @ drain WB
58 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
62 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
63 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)
H A Dproc-arm922.S82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
83 mcr p15, 0, ip, c7, c10, 4 @ drain WB
85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
136 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
142 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
143 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
163 1: mcr p15, 0, r0, c7, c1
[all...]
H A Dproc-arm1020.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
149 mcr p15, 0, ip, c7, c10, 4 @ drain WB
157 mcrne p15, 0, ip, c7, c
[all...]
H A Dproc-arm1020e.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
158 mcrne p15, 0, ip, c7, c1
[all...]
H A Dproc-arm926.S72 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
73 mcr p15, 0, ip, c7, c10, 4 @ drain WB
75 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
94 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
135 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
137 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
141 mcrne p15, 0, ip, c7, c
[all...]
H A Dproc-arm1026.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
145 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
150 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
152 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
173 1: mcr p15, 0, r0, c7, c1
[all...]
H A Dproc-arm1022.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
155 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
157 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
178 1: mcr p15, 0, r0, c7, c1
[all...]
H A Dproc-arm925.S112 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
113 mcr p15, 0, ip, c7, c10, 4 @ drain WB
115 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
132 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
135 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
147 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
169 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
173 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
178 mcrne p15, 0, ip, c7, c
[all...]
H A Dcache-v4.S41 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
61 mcr p15, 0, ip, c7, c7, 0 @ flush ID cache
123 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
H A Dcache-v4wt.S49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
71 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
72 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
91 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
93 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
128 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
147 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
165 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
H A Dproc-xsc3.S69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
140 mcr p14, 0, r0, c7, c0, 0 @ go to idle
153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
177 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
178 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
200 mcrne p15, 0, r0, c7, c
[all...]
H A Dcache-v4wb.S59 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
78 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
95 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
113 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
118 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
119 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
124 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
172 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
178 mcr p15, 0, r0, c7, c
[all...]
H A Dproc-arm940.S56 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
57 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
58 mcr p15, 0, ip, c7, c10, 4 @ drain WB
72 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
115 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
119 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
126 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
127 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
174 2: mcr p15, 0, r3, c7, c1
[all...]
H A Dproc-feroceon.S75 mcr p15, 0, r0, c7, c10, 4 @ drain WB
98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
99 mcr p15, 0, ip, c7, c10, 4 @ drain WB
101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
119 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
131 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
156 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
164 mcrne p15, 0, ip, c7, c
[all...]
H A Dproc-sa110.S68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
69 mcr p15, 0, ip, c7, c10, 4 @ drain WB
71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
121 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
143 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
160 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
161 mcr p15, 0, r0, c7, c10, 4 @ drain WB
169 mcr p15, 0, r10, c7, c7
[all...]
H A Dproc-arm720.S73 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
75 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
102 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
104 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
117 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
119 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
145 mcr p15, 0, r0, c7, c
[all...]
H A Dproc-xscale.S92 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
94 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
159 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
163 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
182 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
195 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
218 mcrne p15, 0, ip, c7, c
[all...]
/linux-master/arch/arm/include/asm/vdso/
H A Dcp15.h29 #define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
30 #define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
/linux-master/arch/arm/boot/compressed/
H A Dhead-xscale.S27 mcr p15, 0, r0, c7, c10, 4 @ drain WB
28 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches

Completed in 149 milliseconds

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