Searched refs:CLK_GATE (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/clk/imx/
H A Dclk-imx8mp-audiomix.c96 #define CLK_GATE(gname, cname) \ macro
169 CLK_GATE("asrc", ASRC_IPG),
170 CLK_GATE("pdm", PDM_IPG),
171 CLK_GATE("earc", EARC_IPG),
172 CLK_GATE("ocrama", OCRAMA_IPG),
173 CLK_GATE("aud2htx", AUD2HTX_IPG),
174 CLK_GATE("earc_phy", EARC_PHY),
175 CLK_GATE("sdma2", SDMA2_ROOT),
176 CLK_GATE("sdma3", SDMA3_ROOT),
177 CLK_GATE("spba
[all...]
H A Dclk-imx95-blk-ctl.c25 CLK_GATE, enumerator in enum:__anon16
67 .type = CLK_GATE,
77 .type = CLK_GATE,
87 .type = CLK_GATE,
107 .type = CLK_GATE,
117 .type = CLK_GATE,
127 .type = CLK_GATE,
137 .type = CLK_GATE,
147 .type = CLK_GATE,
177 .type = CLK_GATE,
[all...]
/linux-master/drivers/clk/
H A Dclk-loongson2.c96 #define CLK_GATE(_id, _name, _pname, _offset, _bidx) \ macro
169 CLK_GATE(LOONGSON2_OUT0_GATE, "out0_gate", "pll_0", 0, 40),
170 CLK_GATE(LOONGSON2_GMAC_GATE, "gmac_gate", "pll_0", 0, 41),
171 CLK_GATE(LOONGSON2_RIO_GATE, "rio_gate", "pll_0", 0, 42),
172 CLK_GATE(LOONGSON2_DC_GATE, "dc_gate", "pll_1", 0x10, 40),
173 CLK_GATE(LOONGSON2_DDR_GATE, "ddr_gate", "pll_1", 0x10, 41),
174 CLK_GATE(LOONGSON2_GPU_GATE, "gpu_gate", "pll_1", 0x10, 42),
175 CLK_GATE(LOONGSON2_HDA_GATE, "hda_gate", "pll_2", 0x20, 40),
176 CLK_GATE(LOONGSON2_NODE_GATE, "node_gate", "pll_2", 0x20, 41),
177 CLK_GATE(LOONGSON2_EMMC_GAT
[all...]
/linux-master/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-core.c37 [CLK_GATE] = "camif",
531 clk_enable(camif->clock[CLK_GATE]);
544 clk_disable(camif->clock[CLK_GATE]);
H A Dcamif-core.h126 CLK_GATE, enumerator in enum:__anon164
/linux-master/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-core.c1001 ret = clk_enable(fimc->clock[CLK_GATE]);
1027 clk_enable(fimc->clock[CLK_GATE]);
1047 clk_disable(fimc->clock[CLK_GATE]);
1099 clk_disable(fimc->clock[CLK_GATE]);
H A Dfimc-core.h54 CLK_GATE, enumerator in enum:__anon362
/linux-master/drivers/clk/nxp/
H A Dclk-lpc32xx.c1048 CLK_GATE, enumerator in enum:lpc32xx_clk_type
1151 .type = CLK_GATE, \
1402 case CLK_GATE:
1423 else if (clk_hw->type == CLK_GATE)

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