Searched refs:AST_IO_VGACRI (Results 1 - 9 of 9) sorted by relevance
/linux-master/drivers/gpu/drm/ast/ |
H A D | ast_dp.c | 12 if (!ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, ASTDP_MCU_FW_EXECUTING)) 14 if (!ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, ASTDP_HPD)) 16 if (!ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDC, ASTDP_LINK_SUCCESS)) 32 if (!(ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, ASTDP_MCU_FW_EXECUTING) && 33 ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDC, ASTDP_LINK_SUCCESS) && 34 ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, ASTDP_HPD) && 35 ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xE5, 40 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, 47 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE4, 55 while ((ast_get_index_reg_mask(ast, AST_IO_VGACRI, [all...] |
H A D | ast_ddc.c | 49 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0xf1, ujcrb7); 50 jtemp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x04); 65 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0xf4, ujcrb7); 66 jtemp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x01); 102 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01; 104 val2 = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01; 109 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01; 124 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01; 126 val2 = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01; 131 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, [all...] |
H A D | ast_dp501.c | 34 sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff); 36 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0x00, sendack); 42 sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff); 44 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0x00, sendack); 52 waitack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff); 68 waitack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff); 81 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, ~0x40, 0x40); 86 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, ~0x40, 0x00); 95 waitready = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff); 113 ast_set_index_reg_mask(ast, AST_IO_VGACRI, [all...] |
H A D | ast_mode.c | 258 ast_set_index_reg(ast, AST_IO_VGACRI, 0x8c, (u8)((color_index & 0x0f) << 4)); 260 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00); 263 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0xa8); 264 ast_set_index_reg(ast, AST_IO_VGACRI, 0x92, format->cpp[0] * 8); 277 ast_set_index_reg(ast, AST_IO_VGACRI, 0x8d, refresh_rate_index & 0xff); 278 ast_set_index_reg(ast, AST_IO_VGACRI, 0x8e, mode_id & 0xff); 280 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00); 283 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0xa8); 284 ast_set_index_reg(ast, AST_IO_VGACRI, 0x93, adjusted_mode->clock / 1000); 285 ast_set_index_reg(ast, AST_IO_VGACRI, [all...] |
H A D | ast_mm.c | 42 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xaa, 0xff); 58 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x99, 0xff);
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H A D | ast_reg.h | 30 #define AST_IO_VGACRI (0x54) macro
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H A D | ast_main.c | 49 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); 86 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff); 97 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff); 116 if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, TX_TYPE_MASK) ==
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H A D | ast_drv.c | 115 __ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1, AST_IO_VGACRA1_MMIO_ENABLED); 122 __ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1, 131 __ast_write8_i(ioregs, AST_IO_VGACRI, 0x80, AST_IO_VGACR80_PASSWORD); 162 vgacrd0 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd0); 163 vgacrd1 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd1);
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H A D | ast_post.c | 52 ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00); 61 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info); 67 /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */ 70 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01); 71 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00); 77 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg); 262 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); 342 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); 366 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); /* Enable DVO */ 1579 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, [all...] |
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