Searched refs:Reg1 (Results 1 - 25 of 49) sorted by relevance

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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.h94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
H A DMipsTargetStreamer.h129 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
131 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
133 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
135 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
137 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
139 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
H A DMipsAsmPrinter.cpp836 unsigned Opcode, unsigned Reg1,
845 unsigned Temp = Reg1;
846 Reg1 = Reg2;
850 I.addOperand(MCOperand::createReg(Reg1));
856 unsigned Opcode, unsigned Reg1,
860 I.addOperand(MCOperand::createReg(Reg1));
867 unsigned MovOpc, unsigned Reg1,
871 unsigned temp = Reg1;
872 Reg1 = Reg2;
875 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg
835 EmitInstrRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2) argument
855 EmitInstrRegRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2, unsigned Reg3) argument
866 EmitMovFPIntPair(const MCSubtargetInfo &STI, unsigned MovOpc, unsigned Reg1, unsigned Reg2, unsigned FPReg1, unsigned FPReg2, bool LE) argument
[all...]
H A DMips16InstrInfo.h121 unsigned Reg1, unsigned Reg2) const;
H A DMips16InstrInfo.cpp278 unsigned Reg1, unsigned Reg2) const {
287 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
291 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
292 MIB3.addReg(Reg1);
296 MIB4.addReg(Reg1, RegState::Kill);
275 adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Reg1, unsigned Reg2) const argument
H A DMicroMipsSizeReduction.cpp377 // Returns true if the registers Reg1 and Reg2 are consecutive
378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { argument
387 if (Registers[i] == Reg1) {
406 Register Reg1 = MI1->getOperand(0).getReg();
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2)));
478 Register Reg1 = MI1->getOperand(1).getReg();
481 if (Reg1 != Reg2)
H A DMipsSEFrameLowering.cpp464 unsigned Reg1 = local
468 std::swap(Reg0, Reg1);
476 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
481 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; local
484 std::swap(Reg0, Reg1);
492 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp675 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); variable
700 Reg1 = getXRegFromWReg(Reg1);
703 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
706 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
709 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
712 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
715 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
719 Reg1 = getDRegFromBReg(Reg1);
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp427 bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
988 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
989 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, argument
1017 // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1018 // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
1028 if (parseRegister(Reg1))
1047 if (parseIntegerRegister(Reg1, RegGroup))
1102 Register Reg1, Reg2; local
1109 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1122 // If we have Reg1, i
1495 Register Reg1, Reg2; local
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp204 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2,
206 assert(Reg1 != AArch64::NoRegister);
208 bool IsFloat = AArch64::FPR64RegClass.contains(Reg1);
235 MIB.addReg(Reg1)
245 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2,
247 assert(Reg1 != AArch64::NoRegister);
249 bool IsFloat = AArch64::FPR64RegClass.contains(Reg1);
276 MIB.addReg(Reg1, getDefRegState(true))
202 emitStore(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator Pos, const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, int Offset, bool IsPreDec) argument
243 emitLoad(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator Pos, const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, int Offset, bool IsPostDec) argument
H A DAArch64FrameLowering.cpp1191 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); local
1194 .addImm(Reg1)
1204 Register Reg1 = MBBI->getOperand(2).getReg(); local
1205 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR)
1212 .addImm(RegInfo->getSEHRegNum(Reg1))
1242 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); local
1245 .addImm(Reg1)
1253 Register Reg1 = MBBI->getOperand(1).getReg(); local
1254 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR)
1261 .addImm(RegInfo->getSEHRegNum(Reg1))
1287 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); local
1300 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); local
2703 invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, bool NeedsWinCFI, bool IsFirst, const TargetRegisterInfo *TRI) argument
2734 invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, bool UsesWinAAPCS, bool NeedsWinCFI, bool NeedsFrameRecord, bool IsFirst, const TargetRegisterInfo *TRI) argument
2753 unsigned Reg1 = AArch64::NoRegister; member in struct:__anon2195::RegPairInfo
3006 unsigned Reg1 = RPI.Reg1; local
[all...]
/freebsd-current/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h82 bool contains(MCRegister Reg1, MCRegister Reg2) const { argument
83 return contains(Reg1) && contains(Reg2);
705 uint16_t Reg1 = 0; member in class:llvm::MCRegUnitRootIterator
713 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
729 Reg0 = Reg1;
730 Reg1 = 0;
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp199 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument
201 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
214 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument
220 TmpInst.addOperand(MCOperand::createReg(Reg1));
226 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument
229 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
232 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument
238 TmpInst.addOperand(MCOperand::createReg(Reg1));
245 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument
248 emitRRX(Opcode, Reg0, Reg1, MCOperan
251 emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.h103 // Union Reg1's and Reg2's groups to form a new group.
105 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
H A DMachineInstr.cpp2447 Register Reg1 = getOperand(1).getReg();
2448 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,
2449 getRegInfo()->getType(Reg1));
2455 Register Reg1 = getOperand(1).getReg();
2457 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,
2458 getRegInfo()->getType(Reg1), Reg2,
2465 Register Reg1 = getOperand(1).getReg();
2469 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),
2477 Register Reg1
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h165 unsigned Reg1, bool isKill1,
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
164 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
H A DX86CompressEVEX.cpp194 Register Reg1 = Op1.getReg();
195 if (Reg1 == Reg0)
H A DX86ExpandPseudo.cpp468 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1); local
477 .addReg(Reg1, RegState::Define | getDeadRegState(DstIsDead));
506 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1); local
521 MIBHi.addReg(Reg1, getKillRegState(SrcIsKill));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp268 unsigned Reg1 = local
273 unsigned Binary = ((Reg1 & 0x1f) << 5) | (Reg2 - Reg1);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp229 Register Reg1 = cast<RegisterSDNode>(V1)->getReg(); local
252 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
266 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp303 Register Reg1 = Op1.getReg(); local
308 MRI.getType(Reg0).isPointer() && MRI.getType(Reg1).isPointer()) {
314 Op1.setReg(convertPtrToInt(Reg1, ConvT, SpirvTy, Helper, MRI, GR));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp82 const DebugLoc &DL, unsigned Reg1,
446 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) {
452 .addReg(Reg1)
444 createRegSequence( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned Reg1, unsigned Reg2) argument
H A DThumb2SizeReduction.cpp755 Register Reg1 = MI->getOperand(1).getReg(); local
760 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
766 if (Reg1 != Reg0)
773 } else if (Reg0 != Reg1) {
/freebsd-current/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp194 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); local
217 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
232 CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, T0.getValue(1));
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h105 bool contains(Register Reg1, Register Reg2) const { argument
108 if (!Reg1.isPhysical() || !Reg2.isPhysical())
110 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg());

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