Searched refs:READ_REG32 (Results 1 - 13 of 13) sorted by relevance
/freebsd-13-stable/sys/dev/qlxgb/ |
H A D | qla_inline.h | 65 if ((READ_REG32(ha, sem_reg) & SEM_LOCK_BIT)) 87 READ_REG32(ha, sem_reg); 101 link_speed = READ_REG32(ha, Q8_LINK_SPEED_0); 141 mac_lo = READ_REG32(ha, mac_crb_addr); 142 mac_hi = READ_REG32(ha, (mac_crb_addr + 0x4));
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H A D | qla_reg.h | 230 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) macro 231 #define READ_OFFSET32(ha, off) READ_REG32(ha, off)
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H A D | qla_hw.c | 442 data = READ_REG32(ha, Q8_NX_CDRP_CMD_RSP); 451 cdrp->rsp = READ_REG32(ha, Q8_NX_CDRP_CMD_RSP); 452 cdrp->rsp_arg1 = READ_REG32(ha, Q8_NX_CDRP_ARG1); 453 cdrp->rsp_arg2 = READ_REG32(ha, Q8_NX_CDRP_ARG2); 454 cdrp->rsp_arg3 = READ_REG32(ha, Q8_NX_CDRP_ARG3); 1722 hw->txr_comp, hw->txr_free, hw->txr_next, READ_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000)))); 1758 link_state = READ_REG32(ha, Q8_LINK_STATE);
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/freebsd-13-stable/sys/dev/qlxgbe/ |
H A D | ql_inline.h | 57 if ((READ_REG32(ha, sem_reg) & BIT_0)) 79 READ_REG32(ha, sem_reg); 93 link_speed = READ_REG32(ha, Q8_LINK_SPEED_0);
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H A D | ql_isr.c | 791 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL); 797 data = READ_REG32(ha, Q8_FW_MBOX0); 807 ha->hw.cable_oui = READ_REG32(ha, (Q8_FW_MBOX0 + 4)); 809 data = READ_REG32(ha, (Q8_FW_MBOX0 + 8)); 815 data = READ_REG32(ha, (Q8_FW_MBOX0 + 12)); 837 data = READ_REG32(ha, (Q8_FW_MBOX0 + 16)); 852 ha->hw.aen_mb1 = READ_REG32(ha, (Q8_FW_MBOX0 + 4)); 853 ha->hw.aen_mb2 = READ_REG32(ha, (Q8_FW_MBOX0 + 8)); 854 ha->hw.aen_mb3 = READ_REG32(ha, (Q8_FW_MBOX0 + 12)); 855 ha->hw.aen_mb4 = READ_REG32(h [all...] |
H A D | ql_misc.c | 75 if (READ_REG32(ha, wnd_reg) == addr) 87 *val = READ_REG32(ha, Q8_WILD_CARD); 678 mem_off = (uint64_t)(READ_REG32(ha, Q8_BOOTLD_ADDR)); 679 mem_size = READ_REG32(ha, Q8_BOOTLD_SIZE); 730 data = READ_REG32(ha, Q8_CMDPEG_STATE); 764 val = READ_REG32(ha, Q8_CMDPEG_STATE); 779 val = READ_REG32(ha, Q8_CMDPEG_STATE); 786 ha->fw_ver_major = READ_REG32(ha, Q8_FW_VER_MAJOR); 787 ha->fw_ver_minor = READ_REG32(ha, Q8_FW_VER_MINOR); 788 ha->fw_ver_sub = READ_REG32(h [all...] |
H A D | ql_hw.c | 1414 data = READ_REG32(ha, Q8_HOST_MBOX_CNTRL); 1449 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL); 1452 data = READ_REG32(ha, Q8_FW_MBOX0); 1479 *fw_mbox++ = READ_REG32(ha, (Q8_FW_MBOX0 + (i << 2))); 2881 ha->hw.mbx_intr_mask_offset = READ_REG32(ha, Q8_MBOX_INT_MASK_MSIX); 3812 link_state = READ_REG32(ha, Q8_LINK_STATE); 3845 val = READ_REG32(ha, Q8_ASIC_TEMPERATURE); 3860 val = READ_REG32(ha, Q8_FIRMWARE_HEARTBEAT); 3880 peg_halt_status1 = READ_REG32(ha, Q8_PEG_HALT_STATUS1); 3881 peg_halt_status2 = READ_REG32(h [all...] |
H A D | ql_ioctl.c | 118 u.rv->val = READ_REG32(ha, u.rv->reg);
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H A D | ql_hw.h | 205 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) macro
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/freebsd-13-stable/sys/dev/qlxge/ |
H A D | qls_dump.c | 382 data = READ_REG32(ha, reg); 414 *data = READ_REG32(ha, Q81_CTL_PROC_DATA); 621 *data = READ_REG32(ha, Q81_CTL_XG_SERDES_DATA); 811 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS); 832 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS); 854 *buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE); 875 *data = READ_REG32(ha, Q81_CTL_XGMAC_DATA); 1224 lo_val = READ_REG32(ha,\ 1236 hi_val = READ_REG32(ha,\ 1427 r_idx = READ_REG32(h [all...] |
H A D | qls_isr.c | 367 status = READ_REG32(ha, Q81_CTL_STATUS); 378 status = READ_REG32(ha, Q81_CTL_INTR_STATUS1);
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H A D | qls_hw.c | 222 data32 = READ_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX); 361 data32 = READ_REG32(ha, Q81_CTL_ROUTING_INDEX); 903 ha->rev_id = READ_REG32(ha, Q81_CTL_REV_ID); 961 data32 = READ_REG32(ha, Q81_CTL_CONFIG); 1311 link_state = READ_REG32(ha, Q81_CTL_STATUS); 1761 data32 = READ_REG32(ha, Q81_CTL_FLASH_ADDR); 1799 *data = READ_REG32(ha, Q81_CTL_FLASH_DATA); 1890 data = READ_REG32(ha, Q81_CTL_SEMAPHORE); 1915 data32 = READ_REG32(ha, Q81_CTL_PROC_ADDR); 1954 *data = READ_REG32(h [all...] |
H A D | qls_hw.h | 900 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) macro
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