/freebsd-12-stable/sys/dev/ixl/ |
H A D | i40e_hmc.h | 140 wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \ 141 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \ 142 wr32((hw), I40E_PFHMC_SDCMD, val3); \ 159 wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \ 160 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \ 161 wr32((hw), I40E_PFHMC_SDCMD, val3); \ 171 wr32((hw), I40E_PFHMC_PDINV, \
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H A D | i40e_adminq.c | 305 wr32(hw, hw->aq.asq.head, 0); 306 wr32(hw, hw->aq.asq.tail, 0); 310 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | 313 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | 315 wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa)); 316 wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa)); 338 wr32(hw, hw->aq.arq.head, 0); 339 wr32(hw, hw->aq.arq.tail, 0); 343 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | 346 wr32(h [all...] |
H A D | ixl_pf_iflib.c | 49 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, i), 68 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, i), 88 wr32(hw, I40E_PFINT_DYN_CTL0, 217 wr32(hw, I40E_PFHMC_ERRORINFO, 0); 228 wr32(hw, I40E_PFINT_ICR0_ENA, mask); 252 wr32(hw, I40E_PFINT_DYN_CTLN(i), 0); 259 wr32(hw, I40E_PFINT_LNKLSTN(i), reg); 266 wr32(hw, I40E_QINT_RQCTL(i), reg); 273 wr32(hw, I40E_QINT_TQCTL(i), reg); 299 wr32(h [all...] |
H A D | ixl_pf_i2c.c | 177 wr32(hw, IXL_I2C_REG(hw), i2cctl); 214 wr32(hw, IXL_I2C_REG(hw), i2cctl); 306 wr32(hw, IXL_I2C_REG(hw), i2cctl); 327 wr32(hw, IXL_I2C_REG(hw), *i2cctl); 353 wr32(hw, IXL_I2C_REG(hw), *i2cctl); 406 wr32(hw, IXL_I2C_REG(hw), *i2cctl); 469 wr32(hw, IXL_I2C_REG(hw), i2cctl); 536 wr32(hw, IXL_I2C_REG(hw), i2cctl); 556 wr32(hw, IXL_I2C_REG(hw), i2cctl); 602 wr32(h [all...] |
H A D | ixl_iw.c | 60 wr32(hw, I40E_PFINT_LNKLSTN(vec - 1), reg); 343 wr32(hw, I40E_PFINT_AEQCTL, reg); 352 wr32(hw, I40E_PFINT_LNKLSTN(vec - 1), reg); 357 wr32(hw, I40E_PFINT_LNKLSTN(vec - 1), reg); 365 wr32(hw, I40E_PFINT_CEQCTL(i), reg);
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H A D | ixl_pf_iov.c | 263 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_num), 272 wr32(hw, I40E_VPLAN_QTABLE(i, vf->vf_num), qtable); 275 wr32(hw, I40E_VPLAN_QTABLE(i, vf->vf_num), 310 wr32(hw, vfint_reg, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK); 318 wr32(hw, vpint_reg, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK | 365 wr32(hw, I40E_PF_PCI_CIAA, IXL_PF_PCI_CIAA_VF_DEVICE_STATUS | 389 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num), vfrtrig); 423 wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_num), VIRTCHNL_VFR_COMPLETED); 427 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num), vfrtrig); 437 wr32(h [all...] |
H A D | if_iavf.c | 631 wr32(vsi->hw, rxr->tail, 0); 1134 wr32(hw, hw->aq.arq.len, reg); 1153 wr32(hw, hw->aq.asq.len, reg); 1205 wr32(hw, I40E_VFINT_ICR0_ENA1, reg); 1671 wr32(hw, I40E_VFINT_ICR0_ENA1, mask); 1704 wr32(hw, I40E_VFINT_DYN_CTL01, 0); 1705 wr32(hw, I40E_VFINT_ICR0_ENA1, 0); 1713 wr32(hw, I40E_VFINT_DYN_CTL01, 1716 wr32(hw, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA1_ADMINQ_MASK); 1729 wr32(h [all...] |
H A D | i40e_lan_hmc.c | 522 wr32(hw, I40E_GLHMC_LANTXBASE(hmc_fn_id), 524 wr32(hw, I40E_GLHMC_LANTXCNT(hmc_fn_id), obj->cnt); 528 wr32(hw, I40E_GLHMC_LANRXBASE(hmc_fn_id), 530 wr32(hw, I40E_GLHMC_LANRXCNT(hmc_fn_id), obj->cnt); 534 wr32(hw, I40E_GLHMC_FCOEDDPBASE(hmc_fn_id), 536 wr32(hw, I40E_GLHMC_FCOEDDPCNT(hmc_fn_id), obj->cnt); 540 wr32(hw, I40E_GLHMC_FCOEFBASE(hmc_fn_id), 542 wr32(hw, I40E_GLHMC_FCOEFCNT(hmc_fn_id), obj->cnt);
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H A D | ixl_pf_main.c | 592 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ 603 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 610 wr32(hw, I40E_PFINT_LNKLST0, 0x7FF); 612 wr32(hw, I40E_PFINT_ITR0(IXL_RX_ITR), 0x3E); 614 wr32(hw, I40E_PFINT_DYN_CTL0, 618 wr32(hw, I40E_PFINT_STAT_CTL0, 0); 1343 wr32(hw, I40E_QTX_ENA(pf_qidx), reg); 1377 wr32(hw, I40E_QRX_ENA(pf_qidx), reg); 1429 wr32(hw, I40E_QTX_ENA(pf_qidx), reg); 1465 wr32(h [all...] |
H A D | i40e_osdep.h | 228 #define wr32(a, reg, value) wr32_osdep((a)->back, (reg), (value)) macro
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H A D | i40e_common.c | 1175 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1381 wr32(hw, I40E_PFGEN_CTRL, 1453 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1456 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1460 wr32(hw, I40E_PFINT_LNKLST0, val); 1462 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1465 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1467 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1484 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1490 wr32(h [all...] |
H A D | ixl_txrx.c | 426 wr32(vsi->hw, txr->tail, pidx); 445 wr32(vsi->hw, txr->tail, 0); 575 wr32(vsi->hw, rxr->tail, pidx);
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H A D | if_ixl.c | 1129 wr32(hw, I40E_PFINT_LNKLST0, 0x7FF); 1376 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
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H A D | iavf_vc.c | 688 wr32(&sc->hw, I40E_VFGEN_RSTAT, VIRTCHNL_VFR_INPROGRESS);
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/freebsd-12-stable/sys/mips/malta/ |
H A D | gt_pci_bus_space.c | 223 #define wr32(a, v) writel(a, htole32(v)) macro 310 wr32(bsh + offset, value); 334 wr32(baddr, *addr++); 360 wr32(baddr, *addr++); 386 wr32(addr, value); 410 wr32(addr, value);
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/freebsd-12-stable/sys/dev/ice/ |
H A D | ice_controlq.c | 264 wr32(hw, ring->head, 0); 265 wr32(hw, ring->tail, 0); 268 wr32(hw, ring->len, (num_entries | ring->len_ena_mask)); 269 wr32(hw, ring->bal, ICE_LO_DWORD(ring->desc_buf.pa)); 270 wr32(hw, ring->bah, ICE_HI_DWORD(ring->desc_buf.pa)); 309 wr32(hw, cq->rq.tail, (u32)(cq->num_rq_entries - 1)); 478 wr32(hw, cq->sq.head, 0); 479 wr32(hw, cq->sq.tail, 0); 480 wr32(hw, cq->sq.len, 0); 481 wr32(h [all...] |
H A D | ice_iflib_txrx.c | 174 wr32(hw, txq->tail, pidx); 400 wr32(hw, rxq->tail, pidx);
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H A D | ice_lib.c | 1176 wr32(hw, QINT_RQCTL(vsi->rx_qmap[rxq->me]), val); 1201 wr32(hw, QINT_TQCTL(vsi->tx_qmap[txq->me]), val); 1232 wr32(hw, QINT_RQCTL(reg), val); 1239 wr32(hw, GLINT_DYN_CTL(rxq->irqv->me), 1269 wr32(hw, QINT_TQCTL(reg), val); 1276 wr32(hw, GLINT_DYN_CTL(txq->irqv->me), 1298 wr32(hw, GLINT_ITR(ICE_RX_ITR, rxq->irqv->me), 1322 wr32(hw, GLINT_ITR(ICE_TX_ITR, txq->irqv->me), 1504 wr32(hw, QRXFLXP_CNTXT(pf_q), regval); 1515 wr32(h [all...] |
H A D | ice_lib.h | 666 wr32(hw, GLINT_DYN_CTL(vector), dyn_ctl); 683 wr32(hw, GLINT_DYN_CTL(vector), dyn_ctl);
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H A D | ice_osdep.c | 194 * wr32 - Write a 32bit hardware register 202 wr32(struct ice_hw *hw, uint32_t reg, uint32_t val) function
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H A D | ice_osdep.h | 84 void wr32(struct ice_hw *hw, uint32_t reg, uint32_t val);
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H A D | ice_common.c | 980 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1035 wr32(hw, GLGEN_RTRIG, val); 1063 wr32(hw, QRX_CONTEXT(i, rxq_index), 1140 wr32(hw, QRX_CONTEXT(i, rxq_index), 0); 1201 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 1264 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0); 1291 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 1356 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); 4750 wr32(hw, GLV_REPC(vsi_num), 0); 4759 wr32(h [all...] |
H A D | ice_nvm.c | 1291 wr32(hw, cmd->offset, data->regval);
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/freebsd-12-stable/sys/mips/cavium/ |
H A D | octopci_bus_space.c | 204 #define wr32(a, v) cvmx_write64_uint32(a, htole32(v)) macro 358 wr32(bsh + offset, value); 392 wr32(baddr, *addr++); 430 wr32(baddr, *addr++); 466 wr32(addr, value); 500 wr32(addr, value); 558 wr32(addr2, rd32(addr1)); 563 wr32(addr2, rd32(addr1));
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/freebsd-12-stable/sys/mips/mips/ |
H A D | bus_space_generic.c | 203 #define wr32(a, v) cvmx_write64_uint32(a, v) macro 212 #define wr32(a, v) sb_big_endian_write32(a, v) macro 222 #define wr32(a, v) writel(a, v) macro 436 wr32(bsh + offset, value); 482 wr32(baddr, *addr++); 534 wr32(baddr, *addr++); 586 wr32(addr, value); 634 wr32(addr, value); 706 wr32(addr2, rd32(addr1)); 711 wr32(addr [all...] |